1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright (c) 2009-2025 Broadcom. All Rights Reserved. The term 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. 6 * 7 **************************************************************************/ 8 9 #include "vmwgfx_drv.h" 10 11 #include "vmwgfx_bo.h" 12 #include "vmwgfx_binding.h" 13 #include "vmwgfx_devcaps.h" 14 #include "vmwgfx_mksstat.h" 15 #include "vmwgfx_vkms.h" 16 #include "ttm_object.h" 17 18 #include <drm/clients/drm_client_setup.h> 19 #include <drm/drm_drv.h> 20 #include <drm/drm_fbdev_ttm.h> 21 #include <drm/drm_gem_ttm_helper.h> 22 #include <drm/drm_ioctl.h> 23 #include <drm/drm_module.h> 24 #include <drm/drm_sysfs.h> 25 #include <drm/ttm/ttm_range_manager.h> 26 #include <drm/ttm/ttm_placement.h> 27 #include <generated/utsrelease.h> 28 29 #ifdef CONFIG_X86 30 #include <asm/hypervisor.h> 31 #endif 32 33 #include <linux/aperture.h> 34 #include <linux/cc_platform.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/version.h> 39 #include <linux/vmalloc.h> 40 41 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 42 43 /* 44 * Fully encoded drm commands. Might move to vmw_drm.h 45 */ 46 47 #define DRM_IOCTL_VMW_GET_PARAM \ 48 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 49 struct drm_vmw_getparam_arg) 50 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 52 union drm_vmw_alloc_dmabuf_arg) 53 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 54 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 55 struct drm_vmw_unref_dmabuf_arg) 56 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 58 struct drm_vmw_cursor_bypass_arg) 59 60 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 61 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 62 struct drm_vmw_control_stream_arg) 63 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 64 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 65 struct drm_vmw_stream_arg) 66 #define DRM_IOCTL_VMW_UNREF_STREAM \ 67 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 68 struct drm_vmw_stream_arg) 69 70 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 71 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 72 struct drm_vmw_context_arg) 73 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 75 struct drm_vmw_context_arg) 76 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 77 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 78 union drm_vmw_surface_create_arg) 79 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 80 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 81 struct drm_vmw_surface_arg) 82 #define DRM_IOCTL_VMW_REF_SURFACE \ 83 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 84 union drm_vmw_surface_reference_arg) 85 #define DRM_IOCTL_VMW_EXECBUF \ 86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 87 struct drm_vmw_execbuf_arg) 88 #define DRM_IOCTL_VMW_GET_3D_CAP \ 89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 90 struct drm_vmw_get_3d_cap_arg) 91 #define DRM_IOCTL_VMW_FENCE_WAIT \ 92 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 93 struct drm_vmw_fence_wait_arg) 94 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 96 struct drm_vmw_fence_signaled_arg) 97 #define DRM_IOCTL_VMW_FENCE_UNREF \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 99 struct drm_vmw_fence_arg) 100 #define DRM_IOCTL_VMW_FENCE_EVENT \ 101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 102 struct drm_vmw_fence_event_arg) 103 #define DRM_IOCTL_VMW_PRESENT \ 104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 105 struct drm_vmw_present_arg) 106 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 108 struct drm_vmw_present_readback_arg) 109 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 111 struct drm_vmw_update_layout_arg) 112 #define DRM_IOCTL_VMW_CREATE_SHADER \ 113 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 114 struct drm_vmw_shader_create_arg) 115 #define DRM_IOCTL_VMW_UNREF_SHADER \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 117 struct drm_vmw_shader_arg) 118 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 119 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 120 union drm_vmw_gb_surface_create_arg) 121 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 123 union drm_vmw_gb_surface_reference_arg) 124 #define DRM_IOCTL_VMW_SYNCCPU \ 125 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 126 struct drm_vmw_synccpu_arg) 127 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 128 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 129 struct drm_vmw_context_arg) 130 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 132 union drm_vmw_gb_surface_create_ext_arg) 133 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 134 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 135 union drm_vmw_gb_surface_reference_ext_arg) 136 #define DRM_IOCTL_VMW_MSG \ 137 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 138 struct drm_vmw_msg_arg) 139 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 140 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 141 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 142 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 143 struct drm_vmw_mksstat_add_arg) 144 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 145 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 146 struct drm_vmw_mksstat_remove_arg) 147 148 /* 149 * Ioctl definitions. 150 */ 151 152 static const struct drm_ioctl_desc vmw_ioctls[] = { 153 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 154 DRM_RENDER_ALLOW), 155 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 156 DRM_RENDER_ALLOW), 157 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 158 DRM_RENDER_ALLOW), 159 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 160 vmw_kms_cursor_bypass_ioctl, 161 DRM_MASTER), 162 163 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 164 DRM_MASTER), 165 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 166 DRM_MASTER), 167 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 168 DRM_MASTER), 169 170 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 171 DRM_RENDER_ALLOW), 172 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 173 DRM_RENDER_ALLOW), 174 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 175 DRM_RENDER_ALLOW), 176 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 177 DRM_RENDER_ALLOW), 178 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 179 DRM_RENDER_ALLOW), 180 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 181 DRM_RENDER_ALLOW), 182 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 183 DRM_RENDER_ALLOW), 184 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 185 vmw_fence_obj_signaled_ioctl, 186 DRM_RENDER_ALLOW), 187 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 188 DRM_RENDER_ALLOW), 189 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 190 DRM_RENDER_ALLOW), 191 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 192 DRM_RENDER_ALLOW), 193 194 /* these allow direct access to the framebuffers mark as master only */ 195 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 196 DRM_MASTER | DRM_AUTH), 197 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 198 vmw_present_readback_ioctl, 199 DRM_MASTER | DRM_AUTH), 200 /* 201 * The permissions of the below ioctl are overridden in 202 * vmw_generic_ioctl(). We require either 203 * DRM_MASTER or capable(CAP_SYS_ADMIN). 204 */ 205 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 206 vmw_kms_update_layout_ioctl, 207 DRM_RENDER_ALLOW), 208 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 209 vmw_shader_define_ioctl, 210 DRM_RENDER_ALLOW), 211 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 212 vmw_shader_destroy_ioctl, 213 DRM_RENDER_ALLOW), 214 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 215 vmw_gb_surface_define_ioctl, 216 DRM_RENDER_ALLOW), 217 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 218 vmw_gb_surface_reference_ioctl, 219 DRM_RENDER_ALLOW), 220 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 221 vmw_user_bo_synccpu_ioctl, 222 DRM_RENDER_ALLOW), 223 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 224 vmw_extended_context_define_ioctl, 225 DRM_RENDER_ALLOW), 226 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 227 vmw_gb_surface_define_ext_ioctl, 228 DRM_RENDER_ALLOW), 229 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 230 vmw_gb_surface_reference_ext_ioctl, 231 DRM_RENDER_ALLOW), 232 DRM_IOCTL_DEF_DRV(VMW_MSG, 233 vmw_msg_ioctl, 234 DRM_RENDER_ALLOW), 235 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 236 vmw_mksstat_reset_ioctl, 237 DRM_RENDER_ALLOW), 238 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 239 vmw_mksstat_add_ioctl, 240 DRM_RENDER_ALLOW), 241 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 242 vmw_mksstat_remove_ioctl, 243 DRM_RENDER_ALLOW), 244 }; 245 246 static const struct pci_device_id vmw_pci_id_list[] = { 247 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 248 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 249 { } 250 }; 251 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 252 253 static int vmw_restrict_iommu; 254 static int vmw_force_coherent; 255 static int vmw_restrict_dma_mask; 256 static int vmw_assume_16bpp; 257 258 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 259 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 260 void *ptr); 261 262 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 263 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 264 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 265 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 266 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 267 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 268 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 269 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 270 271 272 struct bitmap_name { 273 uint32 value; 274 const char *name; 275 }; 276 277 static const struct bitmap_name cap1_names[] = { 278 { SVGA_CAP_RECT_COPY, "rect copy" }, 279 { SVGA_CAP_CURSOR, "cursor" }, 280 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 281 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 282 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 283 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 284 { SVGA_CAP_3D, "3D" }, 285 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 286 { SVGA_CAP_MULTIMON, "multimon" }, 287 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 288 { SVGA_CAP_IRQMASK, "irq mask" }, 289 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 290 { SVGA_CAP_GMR, "gmr" }, 291 { SVGA_CAP_TRACES, "traces" }, 292 { SVGA_CAP_GMR2, "gmr2" }, 293 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 294 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 295 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 296 { SVGA_CAP_GBOBJECTS, "gbobject" }, 297 { SVGA_CAP_DX, "dx" }, 298 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 299 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 300 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 301 }; 302 303 304 static const struct bitmap_name cap2_names[] = { 305 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 306 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 307 { SVGA_CAP2_DX2, "dx2" }, 308 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 309 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 310 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 311 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 312 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 313 { SVGA_CAP2_MSHINT, "mshint" }, 314 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 315 { SVGA_CAP2_DX3, "dx3" }, 316 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 317 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 318 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 319 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 320 { SVGA_CAP2_LO_STAGING, "lo staging" }, 321 }; 322 323 static void vmw_print_bitmap(struct drm_device *drm, 324 const char *prefix, uint32_t bitmap, 325 const struct bitmap_name *bnames, 326 uint32_t num_names) 327 { 328 char buf[512]; 329 uint32_t i; 330 uint32_t offset = 0; 331 for (i = 0; i < num_names; ++i) { 332 if ((bitmap & bnames[i].value) != 0) { 333 offset += snprintf(buf + offset, 334 ARRAY_SIZE(buf) - offset, 335 "%s, ", bnames[i].name); 336 bitmap &= ~bnames[i].value; 337 } 338 } 339 340 drm_info(drm, "%s: %s\n", prefix, buf); 341 if (bitmap != 0) 342 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 343 } 344 345 346 static void vmw_print_sm_type(struct vmw_private *dev_priv) 347 { 348 static const char *names[] = { 349 [VMW_SM_LEGACY] = "Legacy", 350 [VMW_SM_4] = "SM4", 351 [VMW_SM_4_1] = "SM4_1", 352 [VMW_SM_5] = "SM_5", 353 [VMW_SM_5_1X] = "SM_5_1X", 354 [VMW_SM_MAX] = "Invalid" 355 }; 356 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 357 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 358 names[dev_priv->sm_type]); 359 } 360 361 /** 362 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 363 * 364 * @dev_priv: A device private structure. 365 * 366 * This function creates a small buffer object that holds the query 367 * result for dummy queries emitted as query barriers. 368 * The function will then map the first page and initialize a pending 369 * occlusion query result structure, Finally it will unmap the buffer. 370 * No interruptible waits are done within this function. 371 * 372 * Returns an error if bo creation or initialization fails. 373 */ 374 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 375 { 376 int ret; 377 struct vmw_bo *vbo; 378 struct ttm_bo_kmap_obj map; 379 volatile SVGA3dQueryResult *result; 380 bool dummy; 381 struct vmw_bo_params bo_params = { 382 .domain = VMW_BO_DOMAIN_SYS, 383 .busy_domain = VMW_BO_DOMAIN_SYS, 384 .bo_type = ttm_bo_type_kernel, 385 .size = PAGE_SIZE, 386 .pin = true, 387 .keep_resv = true, 388 }; 389 390 /* 391 * Create the vbo as pinned, so that a tryreserve will 392 * immediately succeed. This is because we're the only 393 * user of the bo currently. 394 */ 395 ret = vmw_bo_create(dev_priv, &bo_params, &vbo); 396 if (unlikely(ret != 0)) 397 return ret; 398 399 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map); 400 if (likely(ret == 0)) { 401 result = ttm_kmap_obj_virtual(&map, &dummy); 402 result->totalSize = sizeof(*result); 403 result->state = SVGA3D_QUERYSTATE_PENDING; 404 result->result32 = 0xff; 405 ttm_bo_kunmap(&map); 406 } 407 vmw_bo_pin_reserved(vbo, false); 408 ttm_bo_unreserve(&vbo->tbo); 409 410 if (unlikely(ret != 0)) { 411 DRM_ERROR("Dummy query buffer map failed.\n"); 412 vmw_bo_unreference(&vbo); 413 } else 414 dev_priv->dummy_query_bo = vbo; 415 416 return ret; 417 } 418 419 static int vmw_device_init(struct vmw_private *dev_priv) 420 { 421 bool uses_fb_traces = false; 422 423 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 424 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 425 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 426 427 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 428 SVGA_REG_ENABLE_HIDE); 429 430 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 431 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 432 433 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 434 dev_priv->fifo = vmw_fifo_create(dev_priv); 435 if (IS_ERR(dev_priv->fifo)) { 436 int err = PTR_ERR(dev_priv->fifo); 437 dev_priv->fifo = NULL; 438 return err; 439 } else if (!dev_priv->fifo) { 440 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 441 } 442 443 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 444 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 445 return 0; 446 } 447 448 static void vmw_device_fini(struct vmw_private *vmw) 449 { 450 /* 451 * Legacy sync 452 */ 453 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 454 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 455 ; 456 457 vmw->last_read_seqno = vmw_fence_read(vmw); 458 459 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 460 vmw->config_done_state); 461 vmw_write(vmw, SVGA_REG_ENABLE, 462 vmw->enable_state); 463 vmw_write(vmw, SVGA_REG_TRACES, 464 vmw->traces_state); 465 466 vmw_fifo_destroy(vmw); 467 } 468 469 /** 470 * vmw_request_device_late - Perform late device setup 471 * 472 * @dev_priv: Pointer to device private. 473 * 474 * This function performs setup of otables and enables large command 475 * buffer submission. These tasks are split out to a separate function 476 * because it reverts vmw_release_device_early and is intended to be used 477 * by an error path in the hibernation code. 478 */ 479 static int vmw_request_device_late(struct vmw_private *dev_priv) 480 { 481 int ret; 482 483 if (dev_priv->has_mob) { 484 ret = vmw_otables_setup(dev_priv); 485 if (unlikely(ret != 0)) { 486 DRM_ERROR("Unable to initialize " 487 "guest Memory OBjects.\n"); 488 return ret; 489 } 490 } 491 492 if (dev_priv->cman) { 493 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 494 if (ret) { 495 struct vmw_cmdbuf_man *man = dev_priv->cman; 496 497 dev_priv->cman = NULL; 498 vmw_cmdbuf_man_destroy(man); 499 } 500 } 501 502 return 0; 503 } 504 505 static int vmw_request_device(struct vmw_private *dev_priv) 506 { 507 int ret; 508 509 ret = vmw_device_init(dev_priv); 510 if (unlikely(ret != 0)) { 511 DRM_ERROR("Unable to initialize the device.\n"); 512 return ret; 513 } 514 vmw_fence_fifo_up(dev_priv->fman); 515 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 516 if (IS_ERR(dev_priv->cman)) { 517 dev_priv->cman = NULL; 518 dev_priv->sm_type = VMW_SM_LEGACY; 519 } 520 521 ret = vmw_request_device_late(dev_priv); 522 if (ret) 523 goto out_no_mob; 524 525 ret = vmw_dummy_query_bo_create(dev_priv); 526 if (unlikely(ret != 0)) 527 goto out_no_query_bo; 528 529 return 0; 530 531 out_no_query_bo: 532 if (dev_priv->cman) 533 vmw_cmdbuf_remove_pool(dev_priv->cman); 534 if (dev_priv->has_mob) { 535 struct ttm_resource_manager *man; 536 537 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 538 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 539 vmw_otables_takedown(dev_priv); 540 } 541 if (dev_priv->cman) 542 vmw_cmdbuf_man_destroy(dev_priv->cman); 543 out_no_mob: 544 vmw_fence_fifo_down(dev_priv->fman); 545 vmw_device_fini(dev_priv); 546 return ret; 547 } 548 549 /** 550 * vmw_release_device_early - Early part of fifo takedown. 551 * 552 * @dev_priv: Pointer to device private struct. 553 * 554 * This is the first part of command submission takedown, to be called before 555 * buffer management is taken down. 556 */ 557 static void vmw_release_device_early(struct vmw_private *dev_priv) 558 { 559 /* 560 * Previous destructions should've released 561 * the pinned bo. 562 */ 563 564 BUG_ON(dev_priv->pinned_bo != NULL); 565 566 vmw_bo_unreference(&dev_priv->dummy_query_bo); 567 if (dev_priv->cman) 568 vmw_cmdbuf_remove_pool(dev_priv->cman); 569 570 if (dev_priv->has_mob) { 571 struct ttm_resource_manager *man; 572 573 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 574 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 575 vmw_otables_takedown(dev_priv); 576 } 577 } 578 579 /** 580 * vmw_release_device_late - Late part of fifo takedown. 581 * 582 * @dev_priv: Pointer to device private struct. 583 * 584 * This is the last part of the command submission takedown, to be called when 585 * command submission is no longer needed. It may wait on pending fences. 586 */ 587 static void vmw_release_device_late(struct vmw_private *dev_priv) 588 { 589 vmw_fence_fifo_down(dev_priv->fman); 590 if (dev_priv->cman) 591 vmw_cmdbuf_man_destroy(dev_priv->cman); 592 593 vmw_device_fini(dev_priv); 594 } 595 596 /* 597 * Sets the initial_[width|height] fields on the given vmw_private. 598 * 599 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 600 * clamping the value to fb_max_[width|height] fields and the 601 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 602 * If the values appear to be invalid, set them to 603 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 604 */ 605 static void vmw_get_initial_size(struct vmw_private *dev_priv) 606 { 607 uint32_t width; 608 uint32_t height; 609 610 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 611 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 612 613 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH); 614 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT); 615 616 if (width > dev_priv->fb_max_width || 617 height > dev_priv->fb_max_height) { 618 619 /* 620 * This is a host error and shouldn't occur. 621 */ 622 623 width = VMWGFX_MIN_INITIAL_WIDTH; 624 height = VMWGFX_MIN_INITIAL_HEIGHT; 625 } 626 627 dev_priv->initial_width = width; 628 dev_priv->initial_height = height; 629 } 630 631 /** 632 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 633 * system. 634 * 635 * @dev_priv: Pointer to a struct vmw_private 636 * 637 * This functions tries to determine what actions need to be taken by the 638 * driver to make system pages visible to the device. 639 * If this function decides that DMA is not possible, it returns -EINVAL. 640 * The driver may then try to disable features of the device that require 641 * DMA. 642 */ 643 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 644 { 645 static const char *names[vmw_dma_map_max] = { 646 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 647 [vmw_dma_map_populate] = "Caching DMA mappings.", 648 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 649 650 /* 651 * When running with SEV we always want dma mappings, because 652 * otherwise ttm tt pool pages will bounce through swiotlb running 653 * out of available space. 654 */ 655 if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 656 dev_priv->map_mode = vmw_dma_alloc_coherent; 657 else if (vmw_restrict_iommu) 658 dev_priv->map_mode = vmw_dma_map_bind; 659 else 660 dev_priv->map_mode = vmw_dma_map_populate; 661 662 drm_info(&dev_priv->drm, 663 "DMA map mode: %s\n", names[dev_priv->map_mode]); 664 return 0; 665 } 666 667 /** 668 * vmw_dma_masks - set required page- and dma masks 669 * 670 * @dev_priv: Pointer to struct drm-device 671 * 672 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 673 * restriction also for 64-bit systems. 674 */ 675 static int vmw_dma_masks(struct vmw_private *dev_priv) 676 { 677 struct drm_device *dev = &dev_priv->drm; 678 int ret = 0; 679 680 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 681 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 682 drm_info(&dev_priv->drm, 683 "Restricting DMA addresses to 44 bits.\n"); 684 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 685 } 686 687 return ret; 688 } 689 690 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 691 { 692 int ret; 693 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 694 dev_priv->vram_size >> PAGE_SHIFT); 695 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 696 return ret; 697 } 698 699 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 700 { 701 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 702 } 703 704 static int vmw_setup_pci_resources(struct vmw_private *dev, 705 u32 pci_id) 706 { 707 resource_size_t rmmio_start; 708 resource_size_t rmmio_size; 709 resource_size_t fifo_start; 710 resource_size_t fifo_size; 711 int ret; 712 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 713 714 pci_set_master(pdev); 715 716 ret = pcim_request_all_regions(pdev, "vmwgfx probe"); 717 if (ret) 718 return ret; 719 720 dev->pci_id = pci_id; 721 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 722 rmmio_start = pci_resource_start(pdev, 0); 723 rmmio_size = pci_resource_len(pdev, 0); 724 dev->vram_start = pci_resource_start(pdev, 2); 725 dev->vram_size = pci_resource_len(pdev, 2); 726 727 drm_info(&dev->drm, 728 "Register MMIO at 0x%pa size is %llu KiB\n", 729 &rmmio_start, (uint64_t)rmmio_size / 1024); 730 dev->rmmio = devm_ioremap(dev->drm.dev, 731 rmmio_start, 732 rmmio_size); 733 if (!dev->rmmio) { 734 drm_err(&dev->drm, 735 "Failed mapping registers mmio memory.\n"); 736 return -ENOMEM; 737 } 738 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 739 dev->io_start = pci_resource_start(pdev, 0); 740 dev->vram_start = pci_resource_start(pdev, 1); 741 dev->vram_size = pci_resource_len(pdev, 1); 742 fifo_start = pci_resource_start(pdev, 2); 743 fifo_size = pci_resource_len(pdev, 2); 744 745 drm_info(&dev->drm, 746 "FIFO at %pa size is %llu KiB\n", 747 &fifo_start, (uint64_t)fifo_size / 1024); 748 dev->fifo_mem = devm_memremap(dev->drm.dev, 749 fifo_start, 750 fifo_size, 751 MEMREMAP_WB); 752 753 if (IS_ERR(dev->fifo_mem)) { 754 drm_err(&dev->drm, 755 "Failed mapping FIFO memory.\n"); 756 return PTR_ERR(dev->fifo_mem); 757 } 758 } else { 759 return -EINVAL; 760 } 761 762 /* 763 * This is approximate size of the vram, the exact size will only 764 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 765 * size will be equal to or bigger than the size reported by 766 * SVGA_REG_VRAM_SIZE. 767 */ 768 drm_info(&dev->drm, 769 "VRAM at %pa size is %llu KiB\n", 770 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 771 772 return 0; 773 } 774 775 static int vmw_detect_version(struct vmw_private *dev) 776 { 777 uint32_t svga_id; 778 779 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 780 SVGA_ID_3 : SVGA_ID_2); 781 svga_id = vmw_read(dev, SVGA_REG_ID); 782 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 783 drm_err(&dev->drm, 784 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 785 svga_id, dev->pci_id); 786 return -ENOSYS; 787 } 788 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 789 drm_info(&dev->drm, 790 "Running on SVGA version %d.\n", (svga_id & 0xff)); 791 return 0; 792 } 793 794 static void vmw_write_driver_id(struct vmw_private *dev) 795 { 796 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) { 797 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 798 SVGA_REG_GUEST_DRIVER_ID_LINUX); 799 800 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1, 801 LINUX_VERSION_MAJOR << 24 | 802 LINUX_VERSION_PATCHLEVEL << 16 | 803 LINUX_VERSION_SUBLEVEL); 804 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2, 805 VMWGFX_DRIVER_MAJOR << 24 | 806 VMWGFX_DRIVER_MINOR << 16 | 807 VMWGFX_DRIVER_PATCHLEVEL); 808 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0); 809 810 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 811 SVGA_REG_GUEST_DRIVER_ID_SUBMIT); 812 } 813 } 814 815 static void vmw_sw_context_init(struct vmw_private *dev_priv) 816 { 817 struct vmw_sw_context *sw_context = &dev_priv->ctx; 818 819 hash_init(sw_context->res_ht); 820 } 821 822 static void vmw_sw_context_fini(struct vmw_private *dev_priv) 823 { 824 struct vmw_sw_context *sw_context = &dev_priv->ctx; 825 826 vfree(sw_context->cmd_bounce); 827 if (sw_context->staged_bindings) 828 vmw_binding_state_free(sw_context->staged_bindings); 829 } 830 831 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 832 { 833 int ret; 834 enum vmw_res_type i; 835 bool refuse_dma = false; 836 837 vmw_sw_context_init(dev_priv); 838 839 mutex_init(&dev_priv->cmdbuf_mutex); 840 mutex_init(&dev_priv->binding_mutex); 841 spin_lock_init(&dev_priv->resource_lock); 842 spin_lock_init(&dev_priv->hw_lock); 843 spin_lock_init(&dev_priv->waiter_lock); 844 spin_lock_init(&dev_priv->cursor_lock); 845 846 ret = vmw_setup_pci_resources(dev_priv, pci_id); 847 if (ret) 848 return ret; 849 ret = vmw_detect_version(dev_priv); 850 if (ret) 851 return ret; 852 853 854 for (i = vmw_res_context; i < vmw_res_max; ++i) { 855 idr_init_base(&dev_priv->res_idr[i], 1); 856 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 857 } 858 859 init_waitqueue_head(&dev_priv->fence_queue); 860 init_waitqueue_head(&dev_priv->fifo_queue); 861 dev_priv->fence_queue_waiters = 0; 862 dev_priv->fifo_queue_waiters = 0; 863 864 dev_priv->used_memory_size = 0; 865 866 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 867 868 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 869 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 870 dev_priv->capabilities, 871 cap1_names, ARRAY_SIZE(cap1_names)); 872 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 873 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 874 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 875 dev_priv->capabilities2, 876 cap2_names, ARRAY_SIZE(cap2_names)); 877 } 878 879 if (!vmwgfx_supported(dev_priv)) { 880 vmw_disable_backdoor(); 881 drm_err_once(&dev_priv->drm, 882 "vmwgfx seems to be running on an unsupported hypervisor."); 883 drm_err_once(&dev_priv->drm, 884 "This configuration is likely broken."); 885 drm_err_once(&dev_priv->drm, 886 "Please switch to a supported graphics device to avoid problems."); 887 } 888 889 vmw_vkms_init(dev_priv); 890 891 ret = vmw_dma_select_mode(dev_priv); 892 if (unlikely(ret != 0)) { 893 drm_info(&dev_priv->drm, 894 "Restricting capabilities since DMA not available.\n"); 895 refuse_dma = true; 896 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 897 drm_info(&dev_priv->drm, 898 "Disabling 3D acceleration.\n"); 899 } 900 901 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 902 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 903 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 904 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 905 906 vmw_get_initial_size(dev_priv); 907 908 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 909 dev_priv->max_gmr_ids = 910 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 911 dev_priv->max_gmr_pages = 912 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 913 dev_priv->memory_size = 914 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 915 dev_priv->memory_size -= dev_priv->vram_size; 916 } else { 917 /* 918 * An arbitrary limit of 512MiB on surface 919 * memory. But all HWV8 hardware supports GMR2. 920 */ 921 dev_priv->memory_size = 512*1024*1024; 922 } 923 dev_priv->max_mob_pages = 0; 924 dev_priv->max_mob_size = 0; 925 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 926 uint64_t mem_size; 927 928 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 929 mem_size = vmw_read(dev_priv, 930 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 931 else 932 mem_size = 933 vmw_read(dev_priv, 934 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 935 936 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 937 dev_priv->max_primary_mem = 938 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 939 dev_priv->max_mob_size = 940 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 941 dev_priv->stdu_max_width = 942 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 943 dev_priv->stdu_max_height = 944 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 945 946 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 947 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 948 dev_priv->texture_max_width = vmw_read(dev_priv, 949 SVGA_REG_DEV_CAP); 950 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 951 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 952 dev_priv->texture_max_height = vmw_read(dev_priv, 953 SVGA_REG_DEV_CAP); 954 } else { 955 dev_priv->texture_max_width = 8192; 956 dev_priv->texture_max_height = 8192; 957 dev_priv->max_primary_mem = dev_priv->vram_size; 958 } 959 drm_info(&dev_priv->drm, 960 "Legacy memory limits: VRAM = %llu KiB, FIFO = %llu KiB, surface = %u KiB\n", 961 (u64)dev_priv->vram_size / 1024, 962 (u64)dev_priv->fifo_mem_size / 1024, 963 dev_priv->memory_size / 1024); 964 965 drm_info(&dev_priv->drm, 966 "MOB limits: max mob size = %u KiB, max mob pages = %u\n", 967 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 968 969 ret = vmw_dma_masks(dev_priv); 970 if (unlikely(ret != 0)) 971 goto out_err0; 972 973 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 974 975 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 976 drm_info(&dev_priv->drm, 977 "Max GMR ids is %u\n", 978 (unsigned)dev_priv->max_gmr_ids); 979 drm_info(&dev_priv->drm, 980 "Max number of GMR pages is %u\n", 981 (unsigned)dev_priv->max_gmr_pages); 982 } 983 drm_info(&dev_priv->drm, 984 "Maximum display memory size is %llu KiB\n", 985 (uint64_t)dev_priv->max_primary_mem / 1024); 986 987 /* Need mmio memory to check for fifo pitchlock cap. */ 988 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 989 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 990 !vmw_fifo_have_pitchlock(dev_priv)) { 991 ret = -ENOSYS; 992 DRM_ERROR("Hardware has no pitchlock\n"); 993 goto out_err0; 994 } 995 996 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops); 997 998 if (unlikely(dev_priv->tdev == NULL)) { 999 drm_err(&dev_priv->drm, 1000 "Unable to initialize TTM object management.\n"); 1001 ret = -ENOMEM; 1002 goto out_err0; 1003 } 1004 1005 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 1006 ret = vmw_irq_install(dev_priv); 1007 if (ret != 0) { 1008 drm_err(&dev_priv->drm, 1009 "Failed installing irq: %d\n", ret); 1010 goto out_no_irq; 1011 } 1012 } 1013 1014 dev_priv->fman = vmw_fence_manager_init(dev_priv); 1015 if (unlikely(dev_priv->fman == NULL)) { 1016 ret = -ENOMEM; 1017 goto out_no_fman; 1018 } 1019 1020 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1021 dev_priv->drm.dev, 1022 dev_priv->drm.anon_inode->i_mapping, 1023 dev_priv->drm.vma_offset_manager, 1024 dev_priv->map_mode == vmw_dma_alloc_coherent, 1025 false); 1026 if (unlikely(ret != 0)) { 1027 drm_err(&dev_priv->drm, 1028 "Failed initializing TTM buffer object driver.\n"); 1029 goto out_no_bdev; 1030 } 1031 1032 /* 1033 * Enable VRAM, but initially don't use it until SVGA is enabled and 1034 * unhidden. 1035 */ 1036 1037 ret = vmw_vram_manager_init(dev_priv); 1038 if (unlikely(ret != 0)) { 1039 drm_err(&dev_priv->drm, 1040 "Failed initializing memory manager for VRAM.\n"); 1041 goto out_no_vram; 1042 } 1043 1044 ret = vmw_devcaps_create(dev_priv); 1045 if (unlikely(ret != 0)) { 1046 drm_err(&dev_priv->drm, 1047 "Failed initializing device caps.\n"); 1048 goto out_no_vram; 1049 } 1050 1051 /* 1052 * "Guest Memory Regions" is an aperture like feature with 1053 * one slot per bo. There is an upper limit of the number of 1054 * slots as well as the bo size. 1055 */ 1056 dev_priv->has_gmr = true; 1057 /* TODO: This is most likely not correct */ 1058 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1059 refuse_dma || 1060 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1061 drm_info(&dev_priv->drm, 1062 "No GMR memory available. " 1063 "Graphics memory resources are very limited.\n"); 1064 dev_priv->has_gmr = false; 1065 } 1066 1067 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1068 dev_priv->has_mob = true; 1069 1070 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1071 drm_info(&dev_priv->drm, 1072 "No MOB memory available. " 1073 "3D will be disabled.\n"); 1074 dev_priv->has_mob = false; 1075 } 1076 if (vmw_sys_man_init(dev_priv) != 0) { 1077 drm_info(&dev_priv->drm, 1078 "No MOB page table memory available. " 1079 "3D will be disabled.\n"); 1080 dev_priv->has_mob = false; 1081 } 1082 } 1083 1084 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1085 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1086 dev_priv->sm_type = VMW_SM_4; 1087 } 1088 1089 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1090 if (has_sm4_context(dev_priv) && 1091 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1092 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1093 dev_priv->sm_type = VMW_SM_4_1; 1094 if (has_sm4_1_context(dev_priv) && 1095 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1096 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1097 dev_priv->sm_type = VMW_SM_5; 1098 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1099 dev_priv->sm_type = VMW_SM_5_1X; 1100 } 1101 } 1102 } 1103 1104 ret = vmw_kms_init(dev_priv); 1105 if (unlikely(ret != 0)) 1106 goto out_no_kms; 1107 vmw_overlay_init(dev_priv); 1108 1109 ret = vmw_request_device(dev_priv); 1110 if (ret) 1111 goto out_no_fifo; 1112 1113 vmw_print_sm_type(dev_priv); 1114 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1115 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1116 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1117 vmw_write_driver_id(dev_priv); 1118 1119 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1120 register_pm_notifier(&dev_priv->pm_nb); 1121 1122 return 0; 1123 1124 out_no_fifo: 1125 vmw_overlay_close(dev_priv); 1126 vmw_kms_close(dev_priv); 1127 out_no_kms: 1128 if (dev_priv->has_mob) { 1129 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1130 vmw_sys_man_fini(dev_priv); 1131 } 1132 if (dev_priv->has_gmr) 1133 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1134 vmw_devcaps_destroy(dev_priv); 1135 vmw_vram_manager_fini(dev_priv); 1136 out_no_vram: 1137 ttm_device_fini(&dev_priv->bdev); 1138 out_no_bdev: 1139 vmw_fence_manager_takedown(dev_priv->fman); 1140 out_no_fman: 1141 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1142 vmw_irq_uninstall(&dev_priv->drm); 1143 out_no_irq: 1144 ttm_object_device_release(&dev_priv->tdev); 1145 out_err0: 1146 for (i = vmw_res_context; i < vmw_res_max; ++i) 1147 idr_destroy(&dev_priv->res_idr[i]); 1148 1149 if (dev_priv->ctx.staged_bindings) 1150 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1151 1152 return ret; 1153 } 1154 1155 static void vmw_driver_unload(struct drm_device *dev) 1156 { 1157 struct vmw_private *dev_priv = vmw_priv(dev); 1158 enum vmw_res_type i; 1159 1160 unregister_pm_notifier(&dev_priv->pm_nb); 1161 1162 vmw_sw_context_fini(dev_priv); 1163 vmw_fifo_resource_dec(dev_priv); 1164 1165 vmw_svga_disable(dev_priv); 1166 1167 vmw_vkms_cleanup(dev_priv); 1168 vmw_kms_close(dev_priv); 1169 vmw_overlay_close(dev_priv); 1170 1171 if (dev_priv->has_gmr) 1172 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1173 1174 vmw_release_device_early(dev_priv); 1175 if (dev_priv->has_mob) { 1176 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1177 vmw_sys_man_fini(dev_priv); 1178 } 1179 vmw_devcaps_destroy(dev_priv); 1180 vmw_vram_manager_fini(dev_priv); 1181 ttm_device_fini(&dev_priv->bdev); 1182 vmw_release_device_late(dev_priv); 1183 vmw_fence_manager_takedown(dev_priv->fman); 1184 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1185 vmw_irq_uninstall(&dev_priv->drm); 1186 1187 ttm_object_device_release(&dev_priv->tdev); 1188 1189 for (i = vmw_res_context; i < vmw_res_max; ++i) 1190 idr_destroy(&dev_priv->res_idr[i]); 1191 1192 vmw_mksstat_remove_all(dev_priv); 1193 } 1194 1195 static void vmw_postclose(struct drm_device *dev, 1196 struct drm_file *file_priv) 1197 { 1198 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1199 1200 ttm_object_file_release(&vmw_fp->tfile); 1201 kfree(vmw_fp); 1202 } 1203 1204 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1205 { 1206 struct vmw_private *dev_priv = vmw_priv(dev); 1207 struct vmw_fpriv *vmw_fp; 1208 int ret = -ENOMEM; 1209 1210 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1211 if (unlikely(!vmw_fp)) 1212 return ret; 1213 1214 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev); 1215 if (unlikely(vmw_fp->tfile == NULL)) 1216 goto out_no_tfile; 1217 1218 file_priv->driver_priv = vmw_fp; 1219 1220 return 0; 1221 1222 out_no_tfile: 1223 kfree(vmw_fp); 1224 return ret; 1225 } 1226 1227 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1228 unsigned long arg, 1229 long (*ioctl_func)(struct file *, unsigned int, 1230 unsigned long)) 1231 { 1232 struct drm_file *file_priv = filp->private_data; 1233 struct drm_device *dev = file_priv->minor->dev; 1234 unsigned int nr = DRM_IOCTL_NR(cmd); 1235 unsigned int flags; 1236 1237 /* 1238 * Do extra checking on driver private ioctls. 1239 */ 1240 1241 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1242 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1243 const struct drm_ioctl_desc *ioctl = 1244 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1245 1246 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1247 return ioctl_func(filp, cmd, arg); 1248 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1249 if (!drm_is_current_master(file_priv) && 1250 !capable(CAP_SYS_ADMIN)) 1251 return -EACCES; 1252 } 1253 1254 if (unlikely(ioctl->cmd != cmd)) 1255 goto out_io_encoding; 1256 1257 flags = ioctl->flags; 1258 } else if (!drm_ioctl_flags(nr, &flags)) 1259 return -EINVAL; 1260 1261 return ioctl_func(filp, cmd, arg); 1262 1263 out_io_encoding: 1264 DRM_ERROR("Invalid command format, ioctl %d\n", 1265 nr - DRM_COMMAND_BASE); 1266 1267 return -EINVAL; 1268 } 1269 1270 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1271 unsigned long arg) 1272 { 1273 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1274 } 1275 1276 #ifdef CONFIG_COMPAT 1277 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1278 unsigned long arg) 1279 { 1280 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1281 } 1282 #endif 1283 1284 static void vmw_master_set(struct drm_device *dev, 1285 struct drm_file *file_priv, 1286 bool from_open) 1287 { 1288 /* 1289 * Inform a new master that the layout may have changed while 1290 * it was gone. 1291 */ 1292 if (!from_open) 1293 drm_sysfs_hotplug_event(dev); 1294 } 1295 1296 static void vmw_master_drop(struct drm_device *dev, 1297 struct drm_file *file_priv) 1298 { 1299 } 1300 1301 bool vmwgfx_supported(struct vmw_private *vmw) 1302 { 1303 #if defined(CONFIG_X86) 1304 return hypervisor_is_type(X86_HYPER_VMWARE); 1305 #elif defined(CONFIG_ARM64) 1306 /* 1307 * On aarch64 only svga3 is supported 1308 */ 1309 return vmw->pci_id == VMWGFX_PCI_ID_SVGA3; 1310 #else 1311 drm_warn_once(&vmw->drm, 1312 "vmwgfx is running on an unknown architecture."); 1313 return false; 1314 #endif 1315 } 1316 1317 /** 1318 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1319 * 1320 * @dev_priv: Pointer to device private struct. 1321 * Needs the reservation sem to be held in non-exclusive mode. 1322 */ 1323 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1324 { 1325 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1326 1327 if (!ttm_resource_manager_used(man)) { 1328 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1329 ttm_resource_manager_set_used(man, true); 1330 } 1331 } 1332 1333 /** 1334 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1335 * 1336 * @dev_priv: Pointer to device private struct. 1337 */ 1338 void vmw_svga_enable(struct vmw_private *dev_priv) 1339 { 1340 __vmw_svga_enable(dev_priv); 1341 } 1342 1343 /** 1344 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1345 * 1346 * @dev_priv: Pointer to device private struct. 1347 * Needs the reservation sem to be held in exclusive mode. 1348 * Will not empty VRAM. VRAM must be emptied by caller. 1349 */ 1350 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1351 { 1352 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1353 1354 if (ttm_resource_manager_used(man)) { 1355 ttm_resource_manager_set_used(man, false); 1356 vmw_write(dev_priv, SVGA_REG_ENABLE, 1357 SVGA_REG_ENABLE_HIDE | 1358 SVGA_REG_ENABLE_ENABLE); 1359 } 1360 } 1361 1362 /** 1363 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1364 * running. 1365 * 1366 * @dev_priv: Pointer to device private struct. 1367 * Will empty VRAM. 1368 */ 1369 void vmw_svga_disable(struct vmw_private *dev_priv) 1370 { 1371 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1372 /* 1373 * Disabling SVGA will turn off device modesetting capabilities, so 1374 * notify KMS about that so that it doesn't cache atomic state that 1375 * isn't valid anymore, for example crtcs turned on. 1376 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1377 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1378 * end up with lock order reversal. Thus, a master may actually perform 1379 * a new modeset just after we call vmw_kms_lost_device() and race with 1380 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1381 * to be inconsistent with the device, causing modesetting problems. 1382 * 1383 */ 1384 vmw_kms_lost_device(&dev_priv->drm); 1385 if (ttm_resource_manager_used(man)) { 1386 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1387 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1388 ttm_resource_manager_set_used(man, false); 1389 vmw_write(dev_priv, SVGA_REG_ENABLE, 1390 SVGA_REG_ENABLE_HIDE | 1391 SVGA_REG_ENABLE_ENABLE); 1392 } 1393 } 1394 1395 static void vmw_remove(struct pci_dev *pdev) 1396 { 1397 struct drm_device *dev = pci_get_drvdata(pdev); 1398 1399 drm_dev_unregister(dev); 1400 vmw_driver_unload(dev); 1401 } 1402 1403 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) 1404 { 1405 struct drm_minor *minor = vmw->drm.primary; 1406 struct dentry *root = minor->debugfs_root; 1407 1408 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM), 1409 root, "system_ttm"); 1410 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM), 1411 root, "vram_ttm"); 1412 if (vmw->has_gmr) 1413 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1414 root, "gmr_ttm"); 1415 if (vmw->has_mob) { 1416 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1417 root, "mob_ttm"); 1418 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1419 root, "system_mob_ttm"); 1420 } 1421 } 1422 1423 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1424 void *ptr) 1425 { 1426 struct vmw_private *dev_priv = 1427 container_of(nb, struct vmw_private, pm_nb); 1428 1429 switch (val) { 1430 case PM_HIBERNATION_PREPARE: 1431 /* 1432 * Take the reservation sem in write mode, which will make sure 1433 * there are no other processes holding a buffer object 1434 * reservation, meaning we should be able to evict all buffer 1435 * objects if needed. 1436 * Once user-space processes have been frozen, we can release 1437 * the lock again. 1438 */ 1439 dev_priv->suspend_locked = true; 1440 break; 1441 case PM_POST_HIBERNATION: 1442 case PM_POST_RESTORE: 1443 if (READ_ONCE(dev_priv->suspend_locked)) { 1444 dev_priv->suspend_locked = false; 1445 } 1446 break; 1447 default: 1448 break; 1449 } 1450 return 0; 1451 } 1452 1453 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1454 { 1455 struct drm_device *dev = pci_get_drvdata(pdev); 1456 struct vmw_private *dev_priv = vmw_priv(dev); 1457 1458 if (dev_priv->refuse_hibernation) 1459 return -EBUSY; 1460 1461 pci_save_state(pdev); 1462 pci_disable_device(pdev); 1463 pci_set_power_state(pdev, PCI_D3hot); 1464 return 0; 1465 } 1466 1467 static int vmw_pci_resume(struct pci_dev *pdev) 1468 { 1469 pci_set_power_state(pdev, PCI_D0); 1470 pci_restore_state(pdev); 1471 return pci_enable_device(pdev); 1472 } 1473 1474 static int vmw_pm_suspend(struct device *kdev) 1475 { 1476 struct pci_dev *pdev = to_pci_dev(kdev); 1477 struct pm_message dummy; 1478 1479 dummy.event = 0; 1480 1481 return vmw_pci_suspend(pdev, dummy); 1482 } 1483 1484 static int vmw_pm_resume(struct device *kdev) 1485 { 1486 struct pci_dev *pdev = to_pci_dev(kdev); 1487 1488 return vmw_pci_resume(pdev); 1489 } 1490 1491 static int vmw_pm_freeze(struct device *kdev) 1492 { 1493 struct pci_dev *pdev = to_pci_dev(kdev); 1494 struct drm_device *dev = pci_get_drvdata(pdev); 1495 struct vmw_private *dev_priv = vmw_priv(dev); 1496 struct ttm_operation_ctx ctx = { 1497 .interruptible = false, 1498 .no_wait_gpu = false 1499 }; 1500 int ret; 1501 1502 /* 1503 * No user-space processes should be running now. 1504 */ 1505 ret = vmw_kms_suspend(&dev_priv->drm); 1506 if (ret) { 1507 DRM_ERROR("Failed to freeze modesetting.\n"); 1508 return ret; 1509 } 1510 1511 vmw_execbuf_release_pinned_bo(dev_priv); 1512 vmw_resource_evict_all(dev_priv); 1513 vmw_release_device_early(dev_priv); 1514 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1515 vmw_fifo_resource_dec(dev_priv); 1516 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1517 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1518 vmw_fifo_resource_inc(dev_priv); 1519 WARN_ON(vmw_request_device_late(dev_priv)); 1520 dev_priv->suspend_locked = false; 1521 if (dev_priv->suspend_state) 1522 vmw_kms_resume(dev); 1523 return -EBUSY; 1524 } 1525 1526 vmw_fence_fifo_down(dev_priv->fman); 1527 __vmw_svga_disable(dev_priv); 1528 1529 vmw_release_device_late(dev_priv); 1530 return 0; 1531 } 1532 1533 static int vmw_pm_restore(struct device *kdev) 1534 { 1535 struct pci_dev *pdev = to_pci_dev(kdev); 1536 struct drm_device *dev = pci_get_drvdata(pdev); 1537 struct vmw_private *dev_priv = vmw_priv(dev); 1538 int ret; 1539 1540 vmw_detect_version(dev_priv); 1541 1542 vmw_fifo_resource_inc(dev_priv); 1543 1544 ret = vmw_request_device(dev_priv); 1545 if (ret) 1546 return ret; 1547 1548 __vmw_svga_enable(dev_priv); 1549 1550 vmw_fence_fifo_up(dev_priv->fman); 1551 dev_priv->suspend_locked = false; 1552 if (dev_priv->suspend_state) 1553 vmw_kms_resume(&dev_priv->drm); 1554 1555 return 0; 1556 } 1557 1558 static const struct dev_pm_ops vmw_pm_ops = { 1559 .freeze = vmw_pm_freeze, 1560 .thaw = vmw_pm_restore, 1561 .restore = vmw_pm_restore, 1562 .suspend = vmw_pm_suspend, 1563 .resume = vmw_pm_resume, 1564 }; 1565 1566 static const struct file_operations vmwgfx_driver_fops = { 1567 .owner = THIS_MODULE, 1568 .open = drm_open, 1569 .release = drm_release, 1570 .unlocked_ioctl = vmw_unlocked_ioctl, 1571 .mmap = drm_gem_mmap, 1572 .poll = drm_poll, 1573 .read = drm_read, 1574 #if defined(CONFIG_COMPAT) 1575 .compat_ioctl = vmw_compat_ioctl, 1576 #endif 1577 .llseek = noop_llseek, 1578 .fop_flags = FOP_UNSIGNED_OFFSET, 1579 }; 1580 1581 static const struct drm_driver driver = { 1582 .driver_features = 1583 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT, 1584 .ioctls = vmw_ioctls, 1585 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1586 .master_set = vmw_master_set, 1587 .master_drop = vmw_master_drop, 1588 .open = vmw_driver_open, 1589 .postclose = vmw_postclose, 1590 1591 .dumb_create = vmw_dumb_create, 1592 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1593 1594 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1595 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1596 .gem_prime_import_sg_table = vmw_prime_import_sg_table, 1597 1598 DRM_FBDEV_TTM_DRIVER_OPS, 1599 1600 .fops = &vmwgfx_driver_fops, 1601 .name = VMWGFX_DRIVER_NAME, 1602 .desc = VMWGFX_DRIVER_DESC, 1603 .major = VMWGFX_DRIVER_MAJOR, 1604 .minor = VMWGFX_DRIVER_MINOR, 1605 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1606 }; 1607 1608 static struct pci_driver vmw_pci_driver = { 1609 .name = VMWGFX_DRIVER_NAME, 1610 .id_table = vmw_pci_id_list, 1611 .probe = vmw_probe, 1612 .remove = vmw_remove, 1613 .driver = { 1614 .pm = &vmw_pm_ops 1615 } 1616 }; 1617 1618 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1619 { 1620 struct vmw_private *vmw; 1621 int ret; 1622 1623 ret = aperture_remove_conflicting_pci_devices(pdev, driver.name); 1624 if (ret) 1625 goto out_error; 1626 1627 ret = pcim_enable_device(pdev); 1628 if (ret) 1629 goto out_error; 1630 1631 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1632 struct vmw_private, drm); 1633 if (IS_ERR(vmw)) { 1634 ret = PTR_ERR(vmw); 1635 goto out_error; 1636 } 1637 1638 pci_set_drvdata(pdev, &vmw->drm); 1639 1640 ret = vmw_driver_load(vmw, ent->device); 1641 if (ret) 1642 goto out_error; 1643 1644 ret = drm_dev_register(&vmw->drm, 0); 1645 if (ret) 1646 goto out_unload; 1647 1648 vmw_fifo_resource_inc(vmw); 1649 vmw_svga_enable(vmw); 1650 drm_client_setup(&vmw->drm, NULL); 1651 1652 vmw_debugfs_gem_init(vmw); 1653 vmw_debugfs_resource_managers_init(vmw); 1654 1655 return 0; 1656 out_unload: 1657 vmw_driver_unload(&vmw->drm); 1658 out_error: 1659 return ret; 1660 } 1661 1662 drm_module_pci_driver(vmw_pci_driver); 1663 1664 MODULE_AUTHOR("VMware Inc. and others"); 1665 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1666 MODULE_LICENSE("GPL and additional rights"); 1667 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1668 __stringify(VMWGFX_DRIVER_MINOR) "." 1669 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1670 "0"); 1671