1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 #include "vmwgfx_drv.h" 30 31 #include "vmwgfx_bo.h" 32 #include "vmwgfx_binding.h" 33 #include "vmwgfx_devcaps.h" 34 #include "vmwgfx_mksstat.h" 35 #include "ttm_object.h" 36 37 #include <drm/drm_aperture.h> 38 #include <drm/drm_drv.h> 39 #include <drm/drm_fbdev_generic.h> 40 #include <drm/drm_gem_ttm_helper.h> 41 #include <drm/drm_ioctl.h> 42 #include <drm/drm_module.h> 43 #include <drm/drm_sysfs.h> 44 #include <drm/ttm/ttm_range_manager.h> 45 #include <drm/ttm/ttm_placement.h> 46 #include <generated/utsrelease.h> 47 48 #ifdef CONFIG_X86 49 #include <asm/hypervisor.h> 50 #endif 51 #include <linux/cc_platform.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/module.h> 54 #include <linux/pci.h> 55 #include <linux/version.h> 56 #include <linux/vmalloc.h> 57 58 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 59 60 /* 61 * Fully encoded drm commands. Might move to vmw_drm.h 62 */ 63 64 #define DRM_IOCTL_VMW_GET_PARAM \ 65 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 66 struct drm_vmw_getparam_arg) 67 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 68 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 69 union drm_vmw_alloc_dmabuf_arg) 70 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 72 struct drm_vmw_unref_dmabuf_arg) 73 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 75 struct drm_vmw_cursor_bypass_arg) 76 77 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 79 struct drm_vmw_control_stream_arg) 80 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 81 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 82 struct drm_vmw_stream_arg) 83 #define DRM_IOCTL_VMW_UNREF_STREAM \ 84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 85 struct drm_vmw_stream_arg) 86 87 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 88 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 89 struct drm_vmw_context_arg) 90 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 92 struct drm_vmw_context_arg) 93 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 94 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 95 union drm_vmw_surface_create_arg) 96 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 97 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 98 struct drm_vmw_surface_arg) 99 #define DRM_IOCTL_VMW_REF_SURFACE \ 100 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 101 union drm_vmw_surface_reference_arg) 102 #define DRM_IOCTL_VMW_EXECBUF \ 103 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 104 struct drm_vmw_execbuf_arg) 105 #define DRM_IOCTL_VMW_GET_3D_CAP \ 106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 107 struct drm_vmw_get_3d_cap_arg) 108 #define DRM_IOCTL_VMW_FENCE_WAIT \ 109 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 110 struct drm_vmw_fence_wait_arg) 111 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 112 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 113 struct drm_vmw_fence_signaled_arg) 114 #define DRM_IOCTL_VMW_FENCE_UNREF \ 115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 116 struct drm_vmw_fence_arg) 117 #define DRM_IOCTL_VMW_FENCE_EVENT \ 118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 119 struct drm_vmw_fence_event_arg) 120 #define DRM_IOCTL_VMW_PRESENT \ 121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 122 struct drm_vmw_present_arg) 123 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 124 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 125 struct drm_vmw_present_readback_arg) 126 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 127 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 128 struct drm_vmw_update_layout_arg) 129 #define DRM_IOCTL_VMW_CREATE_SHADER \ 130 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 131 struct drm_vmw_shader_create_arg) 132 #define DRM_IOCTL_VMW_UNREF_SHADER \ 133 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 134 struct drm_vmw_shader_arg) 135 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 136 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 137 union drm_vmw_gb_surface_create_arg) 138 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 140 union drm_vmw_gb_surface_reference_arg) 141 #define DRM_IOCTL_VMW_SYNCCPU \ 142 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 143 struct drm_vmw_synccpu_arg) 144 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 145 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 146 struct drm_vmw_context_arg) 147 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 148 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 149 union drm_vmw_gb_surface_create_ext_arg) 150 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 151 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 152 union drm_vmw_gb_surface_reference_ext_arg) 153 #define DRM_IOCTL_VMW_MSG \ 154 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 155 struct drm_vmw_msg_arg) 156 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 157 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 158 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 159 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 160 struct drm_vmw_mksstat_add_arg) 161 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 162 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 163 struct drm_vmw_mksstat_remove_arg) 164 165 /* 166 * Ioctl definitions. 167 */ 168 169 static const struct drm_ioctl_desc vmw_ioctls[] = { 170 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 171 DRM_RENDER_ALLOW), 172 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 173 DRM_RENDER_ALLOW), 174 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 175 DRM_RENDER_ALLOW), 176 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 177 vmw_kms_cursor_bypass_ioctl, 178 DRM_MASTER), 179 180 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 181 DRM_MASTER), 182 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 183 DRM_MASTER), 184 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 185 DRM_MASTER), 186 187 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 188 DRM_RENDER_ALLOW), 189 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 190 DRM_RENDER_ALLOW), 191 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 192 DRM_RENDER_ALLOW), 193 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 194 DRM_RENDER_ALLOW), 195 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 196 DRM_RENDER_ALLOW), 197 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 198 DRM_RENDER_ALLOW), 199 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 200 DRM_RENDER_ALLOW), 201 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 202 vmw_fence_obj_signaled_ioctl, 203 DRM_RENDER_ALLOW), 204 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 205 DRM_RENDER_ALLOW), 206 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 207 DRM_RENDER_ALLOW), 208 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 209 DRM_RENDER_ALLOW), 210 211 /* these allow direct access to the framebuffers mark as master only */ 212 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 213 DRM_MASTER | DRM_AUTH), 214 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 215 vmw_present_readback_ioctl, 216 DRM_MASTER | DRM_AUTH), 217 /* 218 * The permissions of the below ioctl are overridden in 219 * vmw_generic_ioctl(). We require either 220 * DRM_MASTER or capable(CAP_SYS_ADMIN). 221 */ 222 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 223 vmw_kms_update_layout_ioctl, 224 DRM_RENDER_ALLOW), 225 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 226 vmw_shader_define_ioctl, 227 DRM_RENDER_ALLOW), 228 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 229 vmw_shader_destroy_ioctl, 230 DRM_RENDER_ALLOW), 231 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 232 vmw_gb_surface_define_ioctl, 233 DRM_RENDER_ALLOW), 234 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 235 vmw_gb_surface_reference_ioctl, 236 DRM_RENDER_ALLOW), 237 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 238 vmw_user_bo_synccpu_ioctl, 239 DRM_RENDER_ALLOW), 240 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 241 vmw_extended_context_define_ioctl, 242 DRM_RENDER_ALLOW), 243 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 244 vmw_gb_surface_define_ext_ioctl, 245 DRM_RENDER_ALLOW), 246 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 247 vmw_gb_surface_reference_ext_ioctl, 248 DRM_RENDER_ALLOW), 249 DRM_IOCTL_DEF_DRV(VMW_MSG, 250 vmw_msg_ioctl, 251 DRM_RENDER_ALLOW), 252 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 253 vmw_mksstat_reset_ioctl, 254 DRM_RENDER_ALLOW), 255 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 256 vmw_mksstat_add_ioctl, 257 DRM_RENDER_ALLOW), 258 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 259 vmw_mksstat_remove_ioctl, 260 DRM_RENDER_ALLOW), 261 }; 262 263 static const struct pci_device_id vmw_pci_id_list[] = { 264 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 265 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 266 { } 267 }; 268 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 269 270 static int vmw_restrict_iommu; 271 static int vmw_force_coherent; 272 static int vmw_restrict_dma_mask; 273 static int vmw_assume_16bpp; 274 275 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 276 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 277 void *ptr); 278 279 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 280 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 281 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 282 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 283 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 284 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 285 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 286 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 287 288 289 struct bitmap_name { 290 uint32 value; 291 const char *name; 292 }; 293 294 static const struct bitmap_name cap1_names[] = { 295 { SVGA_CAP_RECT_COPY, "rect copy" }, 296 { SVGA_CAP_CURSOR, "cursor" }, 297 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 298 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 299 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 300 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 301 { SVGA_CAP_3D, "3D" }, 302 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 303 { SVGA_CAP_MULTIMON, "multimon" }, 304 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 305 { SVGA_CAP_IRQMASK, "irq mask" }, 306 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 307 { SVGA_CAP_GMR, "gmr" }, 308 { SVGA_CAP_TRACES, "traces" }, 309 { SVGA_CAP_GMR2, "gmr2" }, 310 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 311 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 312 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 313 { SVGA_CAP_GBOBJECTS, "gbobject" }, 314 { SVGA_CAP_DX, "dx" }, 315 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 316 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 317 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 318 }; 319 320 321 static const struct bitmap_name cap2_names[] = { 322 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 323 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 324 { SVGA_CAP2_DX2, "dx2" }, 325 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 326 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 327 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 328 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 329 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 330 { SVGA_CAP2_MSHINT, "mshint" }, 331 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 332 { SVGA_CAP2_DX3, "dx3" }, 333 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 334 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 335 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 336 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 337 { SVGA_CAP2_LO_STAGING, "lo staging" }, 338 }; 339 340 static void vmw_print_bitmap(struct drm_device *drm, 341 const char *prefix, uint32_t bitmap, 342 const struct bitmap_name *bnames, 343 uint32_t num_names) 344 { 345 char buf[512]; 346 uint32_t i; 347 uint32_t offset = 0; 348 for (i = 0; i < num_names; ++i) { 349 if ((bitmap & bnames[i].value) != 0) { 350 offset += snprintf(buf + offset, 351 ARRAY_SIZE(buf) - offset, 352 "%s, ", bnames[i].name); 353 bitmap &= ~bnames[i].value; 354 } 355 } 356 357 drm_info(drm, "%s: %s\n", prefix, buf); 358 if (bitmap != 0) 359 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 360 } 361 362 363 static void vmw_print_sm_type(struct vmw_private *dev_priv) 364 { 365 static const char *names[] = { 366 [VMW_SM_LEGACY] = "Legacy", 367 [VMW_SM_4] = "SM4", 368 [VMW_SM_4_1] = "SM4_1", 369 [VMW_SM_5] = "SM_5", 370 [VMW_SM_5_1X] = "SM_5_1X", 371 [VMW_SM_MAX] = "Invalid" 372 }; 373 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 374 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 375 names[dev_priv->sm_type]); 376 } 377 378 /** 379 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 380 * 381 * @dev_priv: A device private structure. 382 * 383 * This function creates a small buffer object that holds the query 384 * result for dummy queries emitted as query barriers. 385 * The function will then map the first page and initialize a pending 386 * occlusion query result structure, Finally it will unmap the buffer. 387 * No interruptible waits are done within this function. 388 * 389 * Returns an error if bo creation or initialization fails. 390 */ 391 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 392 { 393 int ret; 394 struct vmw_bo *vbo; 395 struct ttm_bo_kmap_obj map; 396 volatile SVGA3dQueryResult *result; 397 bool dummy; 398 struct vmw_bo_params bo_params = { 399 .domain = VMW_BO_DOMAIN_SYS, 400 .busy_domain = VMW_BO_DOMAIN_SYS, 401 .bo_type = ttm_bo_type_kernel, 402 .size = PAGE_SIZE, 403 .pin = true 404 }; 405 406 /* 407 * Create the vbo as pinned, so that a tryreserve will 408 * immediately succeed. This is because we're the only 409 * user of the bo currently. 410 */ 411 ret = vmw_bo_create(dev_priv, &bo_params, &vbo); 412 if (unlikely(ret != 0)) 413 return ret; 414 415 ret = ttm_bo_reserve(&vbo->tbo, false, true, NULL); 416 BUG_ON(ret != 0); 417 vmw_bo_pin_reserved(vbo, true); 418 419 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map); 420 if (likely(ret == 0)) { 421 result = ttm_kmap_obj_virtual(&map, &dummy); 422 result->totalSize = sizeof(*result); 423 result->state = SVGA3D_QUERYSTATE_PENDING; 424 result->result32 = 0xff; 425 ttm_bo_kunmap(&map); 426 } 427 vmw_bo_pin_reserved(vbo, false); 428 ttm_bo_unreserve(&vbo->tbo); 429 430 if (unlikely(ret != 0)) { 431 DRM_ERROR("Dummy query buffer map failed.\n"); 432 vmw_bo_unreference(&vbo); 433 } else 434 dev_priv->dummy_query_bo = vbo; 435 436 return ret; 437 } 438 439 static int vmw_device_init(struct vmw_private *dev_priv) 440 { 441 bool uses_fb_traces = false; 442 443 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 444 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 445 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 446 447 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 448 SVGA_REG_ENABLE_HIDE); 449 450 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 451 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 452 453 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 454 dev_priv->fifo = vmw_fifo_create(dev_priv); 455 if (IS_ERR(dev_priv->fifo)) { 456 int err = PTR_ERR(dev_priv->fifo); 457 dev_priv->fifo = NULL; 458 return err; 459 } else if (!dev_priv->fifo) { 460 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 461 } 462 463 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 464 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 465 return 0; 466 } 467 468 static void vmw_device_fini(struct vmw_private *vmw) 469 { 470 /* 471 * Legacy sync 472 */ 473 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 474 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 475 ; 476 477 vmw->last_read_seqno = vmw_fence_read(vmw); 478 479 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 480 vmw->config_done_state); 481 vmw_write(vmw, SVGA_REG_ENABLE, 482 vmw->enable_state); 483 vmw_write(vmw, SVGA_REG_TRACES, 484 vmw->traces_state); 485 486 vmw_fifo_destroy(vmw); 487 } 488 489 /** 490 * vmw_request_device_late - Perform late device setup 491 * 492 * @dev_priv: Pointer to device private. 493 * 494 * This function performs setup of otables and enables large command 495 * buffer submission. These tasks are split out to a separate function 496 * because it reverts vmw_release_device_early and is intended to be used 497 * by an error path in the hibernation code. 498 */ 499 static int vmw_request_device_late(struct vmw_private *dev_priv) 500 { 501 int ret; 502 503 if (dev_priv->has_mob) { 504 ret = vmw_otables_setup(dev_priv); 505 if (unlikely(ret != 0)) { 506 DRM_ERROR("Unable to initialize " 507 "guest Memory OBjects.\n"); 508 return ret; 509 } 510 } 511 512 if (dev_priv->cman) { 513 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 514 if (ret) { 515 struct vmw_cmdbuf_man *man = dev_priv->cman; 516 517 dev_priv->cman = NULL; 518 vmw_cmdbuf_man_destroy(man); 519 } 520 } 521 522 return 0; 523 } 524 525 static int vmw_request_device(struct vmw_private *dev_priv) 526 { 527 int ret; 528 529 ret = vmw_device_init(dev_priv); 530 if (unlikely(ret != 0)) { 531 DRM_ERROR("Unable to initialize the device.\n"); 532 return ret; 533 } 534 vmw_fence_fifo_up(dev_priv->fman); 535 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 536 if (IS_ERR(dev_priv->cman)) { 537 dev_priv->cman = NULL; 538 dev_priv->sm_type = VMW_SM_LEGACY; 539 } 540 541 ret = vmw_request_device_late(dev_priv); 542 if (ret) 543 goto out_no_mob; 544 545 ret = vmw_dummy_query_bo_create(dev_priv); 546 if (unlikely(ret != 0)) 547 goto out_no_query_bo; 548 549 return 0; 550 551 out_no_query_bo: 552 if (dev_priv->cman) 553 vmw_cmdbuf_remove_pool(dev_priv->cman); 554 if (dev_priv->has_mob) { 555 struct ttm_resource_manager *man; 556 557 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 558 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 559 vmw_otables_takedown(dev_priv); 560 } 561 if (dev_priv->cman) 562 vmw_cmdbuf_man_destroy(dev_priv->cman); 563 out_no_mob: 564 vmw_fence_fifo_down(dev_priv->fman); 565 vmw_device_fini(dev_priv); 566 return ret; 567 } 568 569 /** 570 * vmw_release_device_early - Early part of fifo takedown. 571 * 572 * @dev_priv: Pointer to device private struct. 573 * 574 * This is the first part of command submission takedown, to be called before 575 * buffer management is taken down. 576 */ 577 static void vmw_release_device_early(struct vmw_private *dev_priv) 578 { 579 /* 580 * Previous destructions should've released 581 * the pinned bo. 582 */ 583 584 BUG_ON(dev_priv->pinned_bo != NULL); 585 586 vmw_bo_unreference(&dev_priv->dummy_query_bo); 587 if (dev_priv->cman) 588 vmw_cmdbuf_remove_pool(dev_priv->cman); 589 590 if (dev_priv->has_mob) { 591 struct ttm_resource_manager *man; 592 593 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 594 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 595 vmw_otables_takedown(dev_priv); 596 } 597 } 598 599 /** 600 * vmw_release_device_late - Late part of fifo takedown. 601 * 602 * @dev_priv: Pointer to device private struct. 603 * 604 * This is the last part of the command submission takedown, to be called when 605 * command submission is no longer needed. It may wait on pending fences. 606 */ 607 static void vmw_release_device_late(struct vmw_private *dev_priv) 608 { 609 vmw_fence_fifo_down(dev_priv->fman); 610 if (dev_priv->cman) 611 vmw_cmdbuf_man_destroy(dev_priv->cman); 612 613 vmw_device_fini(dev_priv); 614 } 615 616 /* 617 * Sets the initial_[width|height] fields on the given vmw_private. 618 * 619 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 620 * clamping the value to fb_max_[width|height] fields and the 621 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 622 * If the values appear to be invalid, set them to 623 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 624 */ 625 static void vmw_get_initial_size(struct vmw_private *dev_priv) 626 { 627 uint32_t width; 628 uint32_t height; 629 630 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 631 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 632 633 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH); 634 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT); 635 636 if (width > dev_priv->fb_max_width || 637 height > dev_priv->fb_max_height) { 638 639 /* 640 * This is a host error and shouldn't occur. 641 */ 642 643 width = VMWGFX_MIN_INITIAL_WIDTH; 644 height = VMWGFX_MIN_INITIAL_HEIGHT; 645 } 646 647 dev_priv->initial_width = width; 648 dev_priv->initial_height = height; 649 } 650 651 /** 652 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 653 * system. 654 * 655 * @dev_priv: Pointer to a struct vmw_private 656 * 657 * This functions tries to determine what actions need to be taken by the 658 * driver to make system pages visible to the device. 659 * If this function decides that DMA is not possible, it returns -EINVAL. 660 * The driver may then try to disable features of the device that require 661 * DMA. 662 */ 663 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 664 { 665 static const char *names[vmw_dma_map_max] = { 666 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 667 [vmw_dma_map_populate] = "Caching DMA mappings.", 668 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 669 670 /* 671 * When running with SEV we always want dma mappings, because 672 * otherwise ttm tt pool pages will bounce through swiotlb running 673 * out of available space. 674 */ 675 if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 676 dev_priv->map_mode = vmw_dma_alloc_coherent; 677 else if (vmw_restrict_iommu) 678 dev_priv->map_mode = vmw_dma_map_bind; 679 else 680 dev_priv->map_mode = vmw_dma_map_populate; 681 682 drm_info(&dev_priv->drm, 683 "DMA map mode: %s\n", names[dev_priv->map_mode]); 684 return 0; 685 } 686 687 /** 688 * vmw_dma_masks - set required page- and dma masks 689 * 690 * @dev_priv: Pointer to struct drm-device 691 * 692 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 693 * restriction also for 64-bit systems. 694 */ 695 static int vmw_dma_masks(struct vmw_private *dev_priv) 696 { 697 struct drm_device *dev = &dev_priv->drm; 698 int ret = 0; 699 700 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 701 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 702 drm_info(&dev_priv->drm, 703 "Restricting DMA addresses to 44 bits.\n"); 704 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 705 } 706 707 return ret; 708 } 709 710 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 711 { 712 int ret; 713 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 714 dev_priv->vram_size >> PAGE_SHIFT); 715 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 716 return ret; 717 } 718 719 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 720 { 721 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 722 } 723 724 static int vmw_setup_pci_resources(struct vmw_private *dev, 725 u32 pci_id) 726 { 727 resource_size_t rmmio_start; 728 resource_size_t rmmio_size; 729 resource_size_t fifo_start; 730 resource_size_t fifo_size; 731 int ret; 732 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 733 734 pci_set_master(pdev); 735 736 ret = pci_request_regions(pdev, "vmwgfx probe"); 737 if (ret) 738 return ret; 739 740 dev->pci_id = pci_id; 741 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 742 rmmio_start = pci_resource_start(pdev, 0); 743 rmmio_size = pci_resource_len(pdev, 0); 744 dev->vram_start = pci_resource_start(pdev, 2); 745 dev->vram_size = pci_resource_len(pdev, 2); 746 747 drm_info(&dev->drm, 748 "Register MMIO at 0x%pa size is %llu kiB\n", 749 &rmmio_start, (uint64_t)rmmio_size / 1024); 750 dev->rmmio = devm_ioremap(dev->drm.dev, 751 rmmio_start, 752 rmmio_size); 753 if (!dev->rmmio) { 754 drm_err(&dev->drm, 755 "Failed mapping registers mmio memory.\n"); 756 pci_release_regions(pdev); 757 return -ENOMEM; 758 } 759 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 760 dev->io_start = pci_resource_start(pdev, 0); 761 dev->vram_start = pci_resource_start(pdev, 1); 762 dev->vram_size = pci_resource_len(pdev, 1); 763 fifo_start = pci_resource_start(pdev, 2); 764 fifo_size = pci_resource_len(pdev, 2); 765 766 drm_info(&dev->drm, 767 "FIFO at %pa size is %llu kiB\n", 768 &fifo_start, (uint64_t)fifo_size / 1024); 769 dev->fifo_mem = devm_memremap(dev->drm.dev, 770 fifo_start, 771 fifo_size, 772 MEMREMAP_WB); 773 774 if (IS_ERR(dev->fifo_mem)) { 775 drm_err(&dev->drm, 776 "Failed mapping FIFO memory.\n"); 777 pci_release_regions(pdev); 778 return PTR_ERR(dev->fifo_mem); 779 } 780 } else { 781 pci_release_regions(pdev); 782 return -EINVAL; 783 } 784 785 /* 786 * This is approximate size of the vram, the exact size will only 787 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 788 * size will be equal to or bigger than the size reported by 789 * SVGA_REG_VRAM_SIZE. 790 */ 791 drm_info(&dev->drm, 792 "VRAM at %pa size is %llu kiB\n", 793 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 794 795 return 0; 796 } 797 798 static int vmw_detect_version(struct vmw_private *dev) 799 { 800 uint32_t svga_id; 801 802 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 803 SVGA_ID_3 : SVGA_ID_2); 804 svga_id = vmw_read(dev, SVGA_REG_ID); 805 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 806 drm_err(&dev->drm, 807 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 808 svga_id, dev->pci_id); 809 return -ENOSYS; 810 } 811 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 812 drm_info(&dev->drm, 813 "Running on SVGA version %d.\n", (svga_id & 0xff)); 814 return 0; 815 } 816 817 static void vmw_write_driver_id(struct vmw_private *dev) 818 { 819 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) { 820 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 821 SVGA_REG_GUEST_DRIVER_ID_LINUX); 822 823 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1, 824 LINUX_VERSION_MAJOR << 24 | 825 LINUX_VERSION_PATCHLEVEL << 16 | 826 LINUX_VERSION_SUBLEVEL); 827 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2, 828 VMWGFX_DRIVER_MAJOR << 24 | 829 VMWGFX_DRIVER_MINOR << 16 | 830 VMWGFX_DRIVER_PATCHLEVEL); 831 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0); 832 833 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 834 SVGA_REG_GUEST_DRIVER_ID_SUBMIT); 835 } 836 } 837 838 static void vmw_sw_context_init(struct vmw_private *dev_priv) 839 { 840 struct vmw_sw_context *sw_context = &dev_priv->ctx; 841 842 hash_init(sw_context->res_ht); 843 } 844 845 static void vmw_sw_context_fini(struct vmw_private *dev_priv) 846 { 847 struct vmw_sw_context *sw_context = &dev_priv->ctx; 848 849 vfree(sw_context->cmd_bounce); 850 if (sw_context->staged_bindings) 851 vmw_binding_state_free(sw_context->staged_bindings); 852 } 853 854 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 855 { 856 int ret; 857 enum vmw_res_type i; 858 bool refuse_dma = false; 859 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 860 861 dev_priv->drm.dev_private = dev_priv; 862 863 vmw_sw_context_init(dev_priv); 864 865 mutex_init(&dev_priv->cmdbuf_mutex); 866 mutex_init(&dev_priv->binding_mutex); 867 spin_lock_init(&dev_priv->resource_lock); 868 spin_lock_init(&dev_priv->hw_lock); 869 spin_lock_init(&dev_priv->waiter_lock); 870 spin_lock_init(&dev_priv->cursor_lock); 871 872 ret = vmw_setup_pci_resources(dev_priv, pci_id); 873 if (ret) 874 return ret; 875 ret = vmw_detect_version(dev_priv); 876 if (ret) 877 goto out_no_pci_or_version; 878 879 880 for (i = vmw_res_context; i < vmw_res_max; ++i) { 881 idr_init_base(&dev_priv->res_idr[i], 1); 882 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 883 } 884 885 init_waitqueue_head(&dev_priv->fence_queue); 886 init_waitqueue_head(&dev_priv->fifo_queue); 887 dev_priv->fence_queue_waiters = 0; 888 dev_priv->fifo_queue_waiters = 0; 889 890 dev_priv->used_memory_size = 0; 891 892 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 893 894 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 895 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 896 dev_priv->capabilities, 897 cap1_names, ARRAY_SIZE(cap1_names)); 898 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 899 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 900 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 901 dev_priv->capabilities2, 902 cap2_names, ARRAY_SIZE(cap2_names)); 903 } 904 905 if (!vmwgfx_supported(dev_priv)) { 906 vmw_disable_backdoor(); 907 drm_err_once(&dev_priv->drm, 908 "vmwgfx seems to be running on an unsupported hypervisor."); 909 drm_err_once(&dev_priv->drm, 910 "This configuration is likely broken."); 911 drm_err_once(&dev_priv->drm, 912 "Please switch to a supported graphics device to avoid problems."); 913 } 914 915 ret = vmw_dma_select_mode(dev_priv); 916 if (unlikely(ret != 0)) { 917 drm_info(&dev_priv->drm, 918 "Restricting capabilities since DMA not available.\n"); 919 refuse_dma = true; 920 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 921 drm_info(&dev_priv->drm, 922 "Disabling 3D acceleration.\n"); 923 } 924 925 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 926 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 927 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 928 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 929 930 vmw_get_initial_size(dev_priv); 931 932 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 933 dev_priv->max_gmr_ids = 934 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 935 dev_priv->max_gmr_pages = 936 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 937 dev_priv->memory_size = 938 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 939 dev_priv->memory_size -= dev_priv->vram_size; 940 } else { 941 /* 942 * An arbitrary limit of 512MiB on surface 943 * memory. But all HWV8 hardware supports GMR2. 944 */ 945 dev_priv->memory_size = 512*1024*1024; 946 } 947 dev_priv->max_mob_pages = 0; 948 dev_priv->max_mob_size = 0; 949 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 950 uint64_t mem_size; 951 952 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 953 mem_size = vmw_read(dev_priv, 954 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 955 else 956 mem_size = 957 vmw_read(dev_priv, 958 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 959 960 /* 961 * Workaround for low memory 2D VMs to compensate for the 962 * allocation taken by fbdev 963 */ 964 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 965 mem_size *= 3; 966 967 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 968 dev_priv->max_primary_mem = 969 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 970 dev_priv->max_mob_size = 971 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 972 dev_priv->stdu_max_width = 973 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 974 dev_priv->stdu_max_height = 975 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 976 977 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 978 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 979 dev_priv->texture_max_width = vmw_read(dev_priv, 980 SVGA_REG_DEV_CAP); 981 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 982 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 983 dev_priv->texture_max_height = vmw_read(dev_priv, 984 SVGA_REG_DEV_CAP); 985 } else { 986 dev_priv->texture_max_width = 8192; 987 dev_priv->texture_max_height = 8192; 988 dev_priv->max_primary_mem = dev_priv->vram_size; 989 } 990 drm_info(&dev_priv->drm, 991 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n", 992 (u64)dev_priv->vram_size / 1024, 993 (u64)dev_priv->fifo_mem_size / 1024, 994 dev_priv->memory_size / 1024); 995 996 drm_info(&dev_priv->drm, 997 "MOB limits: max mob size = %u kB, max mob pages = %u\n", 998 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 999 1000 ret = vmw_dma_masks(dev_priv); 1001 if (unlikely(ret != 0)) 1002 goto out_err0; 1003 1004 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 1005 1006 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 1007 drm_info(&dev_priv->drm, 1008 "Max GMR ids is %u\n", 1009 (unsigned)dev_priv->max_gmr_ids); 1010 drm_info(&dev_priv->drm, 1011 "Max number of GMR pages is %u\n", 1012 (unsigned)dev_priv->max_gmr_pages); 1013 } 1014 drm_info(&dev_priv->drm, 1015 "Maximum display memory size is %llu kiB\n", 1016 (uint64_t)dev_priv->max_primary_mem / 1024); 1017 1018 /* Need mmio memory to check for fifo pitchlock cap. */ 1019 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 1020 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 1021 !vmw_fifo_have_pitchlock(dev_priv)) { 1022 ret = -ENOSYS; 1023 DRM_ERROR("Hardware has no pitchlock\n"); 1024 goto out_err0; 1025 } 1026 1027 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops); 1028 1029 if (unlikely(dev_priv->tdev == NULL)) { 1030 drm_err(&dev_priv->drm, 1031 "Unable to initialize TTM object management.\n"); 1032 ret = -ENOMEM; 1033 goto out_err0; 1034 } 1035 1036 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 1037 ret = vmw_irq_install(dev_priv); 1038 if (ret != 0) { 1039 drm_err(&dev_priv->drm, 1040 "Failed installing irq: %d\n", ret); 1041 goto out_no_irq; 1042 } 1043 } 1044 1045 dev_priv->fman = vmw_fence_manager_init(dev_priv); 1046 if (unlikely(dev_priv->fman == NULL)) { 1047 ret = -ENOMEM; 1048 goto out_no_fman; 1049 } 1050 1051 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1052 dev_priv->drm.dev, 1053 dev_priv->drm.anon_inode->i_mapping, 1054 dev_priv->drm.vma_offset_manager, 1055 dev_priv->map_mode == vmw_dma_alloc_coherent, 1056 false); 1057 if (unlikely(ret != 0)) { 1058 drm_err(&dev_priv->drm, 1059 "Failed initializing TTM buffer object driver.\n"); 1060 goto out_no_bdev; 1061 } 1062 1063 /* 1064 * Enable VRAM, but initially don't use it until SVGA is enabled and 1065 * unhidden. 1066 */ 1067 1068 ret = vmw_vram_manager_init(dev_priv); 1069 if (unlikely(ret != 0)) { 1070 drm_err(&dev_priv->drm, 1071 "Failed initializing memory manager for VRAM.\n"); 1072 goto out_no_vram; 1073 } 1074 1075 ret = vmw_devcaps_create(dev_priv); 1076 if (unlikely(ret != 0)) { 1077 drm_err(&dev_priv->drm, 1078 "Failed initializing device caps.\n"); 1079 goto out_no_vram; 1080 } 1081 1082 /* 1083 * "Guest Memory Regions" is an aperture like feature with 1084 * one slot per bo. There is an upper limit of the number of 1085 * slots as well as the bo size. 1086 */ 1087 dev_priv->has_gmr = true; 1088 /* TODO: This is most likely not correct */ 1089 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1090 refuse_dma || 1091 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1092 drm_info(&dev_priv->drm, 1093 "No GMR memory available. " 1094 "Graphics memory resources are very limited.\n"); 1095 dev_priv->has_gmr = false; 1096 } 1097 1098 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1099 dev_priv->has_mob = true; 1100 1101 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1102 drm_info(&dev_priv->drm, 1103 "No MOB memory available. " 1104 "3D will be disabled.\n"); 1105 dev_priv->has_mob = false; 1106 } 1107 if (vmw_sys_man_init(dev_priv) != 0) { 1108 drm_info(&dev_priv->drm, 1109 "No MOB page table memory available. " 1110 "3D will be disabled.\n"); 1111 dev_priv->has_mob = false; 1112 } 1113 } 1114 1115 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1116 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1117 dev_priv->sm_type = VMW_SM_4; 1118 } 1119 1120 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1121 if (has_sm4_context(dev_priv) && 1122 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1123 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1124 dev_priv->sm_type = VMW_SM_4_1; 1125 if (has_sm4_1_context(dev_priv) && 1126 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1127 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1128 dev_priv->sm_type = VMW_SM_5; 1129 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1130 dev_priv->sm_type = VMW_SM_5_1X; 1131 } 1132 } 1133 } 1134 1135 ret = vmw_kms_init(dev_priv); 1136 if (unlikely(ret != 0)) 1137 goto out_no_kms; 1138 vmw_overlay_init(dev_priv); 1139 1140 ret = vmw_request_device(dev_priv); 1141 if (ret) 1142 goto out_no_fifo; 1143 1144 vmw_print_sm_type(dev_priv); 1145 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1146 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1147 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1148 vmw_write_driver_id(dev_priv); 1149 1150 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1151 register_pm_notifier(&dev_priv->pm_nb); 1152 1153 return 0; 1154 1155 out_no_fifo: 1156 vmw_overlay_close(dev_priv); 1157 vmw_kms_close(dev_priv); 1158 out_no_kms: 1159 if (dev_priv->has_mob) { 1160 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1161 vmw_sys_man_fini(dev_priv); 1162 } 1163 if (dev_priv->has_gmr) 1164 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1165 vmw_devcaps_destroy(dev_priv); 1166 vmw_vram_manager_fini(dev_priv); 1167 out_no_vram: 1168 ttm_device_fini(&dev_priv->bdev); 1169 out_no_bdev: 1170 vmw_fence_manager_takedown(dev_priv->fman); 1171 out_no_fman: 1172 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1173 vmw_irq_uninstall(&dev_priv->drm); 1174 out_no_irq: 1175 ttm_object_device_release(&dev_priv->tdev); 1176 out_err0: 1177 for (i = vmw_res_context; i < vmw_res_max; ++i) 1178 idr_destroy(&dev_priv->res_idr[i]); 1179 1180 if (dev_priv->ctx.staged_bindings) 1181 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1182 out_no_pci_or_version: 1183 pci_release_regions(pdev); 1184 return ret; 1185 } 1186 1187 static void vmw_driver_unload(struct drm_device *dev) 1188 { 1189 struct vmw_private *dev_priv = vmw_priv(dev); 1190 struct pci_dev *pdev = to_pci_dev(dev->dev); 1191 enum vmw_res_type i; 1192 1193 unregister_pm_notifier(&dev_priv->pm_nb); 1194 1195 vmw_sw_context_fini(dev_priv); 1196 vmw_fifo_resource_dec(dev_priv); 1197 1198 vmw_svga_disable(dev_priv); 1199 1200 vmw_kms_close(dev_priv); 1201 vmw_overlay_close(dev_priv); 1202 1203 if (dev_priv->has_gmr) 1204 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1205 1206 vmw_release_device_early(dev_priv); 1207 if (dev_priv->has_mob) { 1208 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1209 vmw_sys_man_fini(dev_priv); 1210 } 1211 vmw_devcaps_destroy(dev_priv); 1212 vmw_vram_manager_fini(dev_priv); 1213 ttm_device_fini(&dev_priv->bdev); 1214 vmw_release_device_late(dev_priv); 1215 vmw_fence_manager_takedown(dev_priv->fman); 1216 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1217 vmw_irq_uninstall(&dev_priv->drm); 1218 1219 ttm_object_device_release(&dev_priv->tdev); 1220 1221 for (i = vmw_res_context; i < vmw_res_max; ++i) 1222 idr_destroy(&dev_priv->res_idr[i]); 1223 1224 vmw_mksstat_remove_all(dev_priv); 1225 1226 pci_release_regions(pdev); 1227 } 1228 1229 static void vmw_postclose(struct drm_device *dev, 1230 struct drm_file *file_priv) 1231 { 1232 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1233 1234 ttm_object_file_release(&vmw_fp->tfile); 1235 kfree(vmw_fp); 1236 } 1237 1238 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1239 { 1240 struct vmw_private *dev_priv = vmw_priv(dev); 1241 struct vmw_fpriv *vmw_fp; 1242 int ret = -ENOMEM; 1243 1244 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1245 if (unlikely(!vmw_fp)) 1246 return ret; 1247 1248 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev); 1249 if (unlikely(vmw_fp->tfile == NULL)) 1250 goto out_no_tfile; 1251 1252 file_priv->driver_priv = vmw_fp; 1253 1254 return 0; 1255 1256 out_no_tfile: 1257 kfree(vmw_fp); 1258 return ret; 1259 } 1260 1261 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1262 unsigned long arg, 1263 long (*ioctl_func)(struct file *, unsigned int, 1264 unsigned long)) 1265 { 1266 struct drm_file *file_priv = filp->private_data; 1267 struct drm_device *dev = file_priv->minor->dev; 1268 unsigned int nr = DRM_IOCTL_NR(cmd); 1269 unsigned int flags; 1270 1271 /* 1272 * Do extra checking on driver private ioctls. 1273 */ 1274 1275 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1276 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1277 const struct drm_ioctl_desc *ioctl = 1278 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1279 1280 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1281 return ioctl_func(filp, cmd, arg); 1282 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1283 if (!drm_is_current_master(file_priv) && 1284 !capable(CAP_SYS_ADMIN)) 1285 return -EACCES; 1286 } 1287 1288 if (unlikely(ioctl->cmd != cmd)) 1289 goto out_io_encoding; 1290 1291 flags = ioctl->flags; 1292 } else if (!drm_ioctl_flags(nr, &flags)) 1293 return -EINVAL; 1294 1295 return ioctl_func(filp, cmd, arg); 1296 1297 out_io_encoding: 1298 DRM_ERROR("Invalid command format, ioctl %d\n", 1299 nr - DRM_COMMAND_BASE); 1300 1301 return -EINVAL; 1302 } 1303 1304 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1305 unsigned long arg) 1306 { 1307 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1308 } 1309 1310 #ifdef CONFIG_COMPAT 1311 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1312 unsigned long arg) 1313 { 1314 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1315 } 1316 #endif 1317 1318 static void vmw_master_set(struct drm_device *dev, 1319 struct drm_file *file_priv, 1320 bool from_open) 1321 { 1322 /* 1323 * Inform a new master that the layout may have changed while 1324 * it was gone. 1325 */ 1326 if (!from_open) 1327 drm_sysfs_hotplug_event(dev); 1328 } 1329 1330 static void vmw_master_drop(struct drm_device *dev, 1331 struct drm_file *file_priv) 1332 { 1333 struct vmw_private *dev_priv = vmw_priv(dev); 1334 1335 vmw_kms_legacy_hotspot_clear(dev_priv); 1336 } 1337 1338 bool vmwgfx_supported(struct vmw_private *vmw) 1339 { 1340 #if defined(CONFIG_X86) 1341 return hypervisor_is_type(X86_HYPER_VMWARE); 1342 #elif defined(CONFIG_ARM64) 1343 /* 1344 * On aarch64 only svga3 is supported 1345 */ 1346 return vmw->pci_id == VMWGFX_PCI_ID_SVGA3; 1347 #else 1348 drm_warn_once(&vmw->drm, 1349 "vmwgfx is running on an unknown architecture."); 1350 return false; 1351 #endif 1352 } 1353 1354 /** 1355 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1356 * 1357 * @dev_priv: Pointer to device private struct. 1358 * Needs the reservation sem to be held in non-exclusive mode. 1359 */ 1360 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1361 { 1362 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1363 1364 if (!ttm_resource_manager_used(man)) { 1365 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1366 ttm_resource_manager_set_used(man, true); 1367 } 1368 } 1369 1370 /** 1371 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1372 * 1373 * @dev_priv: Pointer to device private struct. 1374 */ 1375 void vmw_svga_enable(struct vmw_private *dev_priv) 1376 { 1377 __vmw_svga_enable(dev_priv); 1378 } 1379 1380 /** 1381 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1382 * 1383 * @dev_priv: Pointer to device private struct. 1384 * Needs the reservation sem to be held in exclusive mode. 1385 * Will not empty VRAM. VRAM must be emptied by caller. 1386 */ 1387 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1388 { 1389 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1390 1391 if (ttm_resource_manager_used(man)) { 1392 ttm_resource_manager_set_used(man, false); 1393 vmw_write(dev_priv, SVGA_REG_ENABLE, 1394 SVGA_REG_ENABLE_HIDE | 1395 SVGA_REG_ENABLE_ENABLE); 1396 } 1397 } 1398 1399 /** 1400 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1401 * running. 1402 * 1403 * @dev_priv: Pointer to device private struct. 1404 * Will empty VRAM. 1405 */ 1406 void vmw_svga_disable(struct vmw_private *dev_priv) 1407 { 1408 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1409 /* 1410 * Disabling SVGA will turn off device modesetting capabilities, so 1411 * notify KMS about that so that it doesn't cache atomic state that 1412 * isn't valid anymore, for example crtcs turned on. 1413 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1414 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1415 * end up with lock order reversal. Thus, a master may actually perform 1416 * a new modeset just after we call vmw_kms_lost_device() and race with 1417 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1418 * to be inconsistent with the device, causing modesetting problems. 1419 * 1420 */ 1421 vmw_kms_lost_device(&dev_priv->drm); 1422 if (ttm_resource_manager_used(man)) { 1423 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1424 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1425 ttm_resource_manager_set_used(man, false); 1426 vmw_write(dev_priv, SVGA_REG_ENABLE, 1427 SVGA_REG_ENABLE_HIDE | 1428 SVGA_REG_ENABLE_ENABLE); 1429 } 1430 } 1431 1432 static void vmw_remove(struct pci_dev *pdev) 1433 { 1434 struct drm_device *dev = pci_get_drvdata(pdev); 1435 1436 drm_dev_unregister(dev); 1437 vmw_driver_unload(dev); 1438 } 1439 1440 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) 1441 { 1442 struct drm_minor *minor = vmw->drm.primary; 1443 struct dentry *root = minor->debugfs_root; 1444 1445 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM), 1446 root, "system_ttm"); 1447 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM), 1448 root, "vram_ttm"); 1449 if (vmw->has_gmr) 1450 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1451 root, "gmr_ttm"); 1452 if (vmw->has_mob) { 1453 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1454 root, "mob_ttm"); 1455 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1456 root, "system_mob_ttm"); 1457 } 1458 } 1459 1460 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1461 void *ptr) 1462 { 1463 struct vmw_private *dev_priv = 1464 container_of(nb, struct vmw_private, pm_nb); 1465 1466 switch (val) { 1467 case PM_HIBERNATION_PREPARE: 1468 /* 1469 * Take the reservation sem in write mode, which will make sure 1470 * there are no other processes holding a buffer object 1471 * reservation, meaning we should be able to evict all buffer 1472 * objects if needed. 1473 * Once user-space processes have been frozen, we can release 1474 * the lock again. 1475 */ 1476 dev_priv->suspend_locked = true; 1477 break; 1478 case PM_POST_HIBERNATION: 1479 case PM_POST_RESTORE: 1480 if (READ_ONCE(dev_priv->suspend_locked)) { 1481 dev_priv->suspend_locked = false; 1482 } 1483 break; 1484 default: 1485 break; 1486 } 1487 return 0; 1488 } 1489 1490 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1491 { 1492 struct drm_device *dev = pci_get_drvdata(pdev); 1493 struct vmw_private *dev_priv = vmw_priv(dev); 1494 1495 if (dev_priv->refuse_hibernation) 1496 return -EBUSY; 1497 1498 pci_save_state(pdev); 1499 pci_disable_device(pdev); 1500 pci_set_power_state(pdev, PCI_D3hot); 1501 return 0; 1502 } 1503 1504 static int vmw_pci_resume(struct pci_dev *pdev) 1505 { 1506 pci_set_power_state(pdev, PCI_D0); 1507 pci_restore_state(pdev); 1508 return pci_enable_device(pdev); 1509 } 1510 1511 static int vmw_pm_suspend(struct device *kdev) 1512 { 1513 struct pci_dev *pdev = to_pci_dev(kdev); 1514 struct pm_message dummy; 1515 1516 dummy.event = 0; 1517 1518 return vmw_pci_suspend(pdev, dummy); 1519 } 1520 1521 static int vmw_pm_resume(struct device *kdev) 1522 { 1523 struct pci_dev *pdev = to_pci_dev(kdev); 1524 1525 return vmw_pci_resume(pdev); 1526 } 1527 1528 static int vmw_pm_freeze(struct device *kdev) 1529 { 1530 struct pci_dev *pdev = to_pci_dev(kdev); 1531 struct drm_device *dev = pci_get_drvdata(pdev); 1532 struct vmw_private *dev_priv = vmw_priv(dev); 1533 struct ttm_operation_ctx ctx = { 1534 .interruptible = false, 1535 .no_wait_gpu = false 1536 }; 1537 int ret; 1538 1539 /* 1540 * No user-space processes should be running now. 1541 */ 1542 ret = vmw_kms_suspend(&dev_priv->drm); 1543 if (ret) { 1544 DRM_ERROR("Failed to freeze modesetting.\n"); 1545 return ret; 1546 } 1547 1548 vmw_execbuf_release_pinned_bo(dev_priv); 1549 vmw_resource_evict_all(dev_priv); 1550 vmw_release_device_early(dev_priv); 1551 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1552 vmw_fifo_resource_dec(dev_priv); 1553 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1554 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1555 vmw_fifo_resource_inc(dev_priv); 1556 WARN_ON(vmw_request_device_late(dev_priv)); 1557 dev_priv->suspend_locked = false; 1558 if (dev_priv->suspend_state) 1559 vmw_kms_resume(dev); 1560 return -EBUSY; 1561 } 1562 1563 vmw_fence_fifo_down(dev_priv->fman); 1564 __vmw_svga_disable(dev_priv); 1565 1566 vmw_release_device_late(dev_priv); 1567 return 0; 1568 } 1569 1570 static int vmw_pm_restore(struct device *kdev) 1571 { 1572 struct pci_dev *pdev = to_pci_dev(kdev); 1573 struct drm_device *dev = pci_get_drvdata(pdev); 1574 struct vmw_private *dev_priv = vmw_priv(dev); 1575 int ret; 1576 1577 vmw_detect_version(dev_priv); 1578 1579 vmw_fifo_resource_inc(dev_priv); 1580 1581 ret = vmw_request_device(dev_priv); 1582 if (ret) 1583 return ret; 1584 1585 __vmw_svga_enable(dev_priv); 1586 1587 vmw_fence_fifo_up(dev_priv->fman); 1588 dev_priv->suspend_locked = false; 1589 if (dev_priv->suspend_state) 1590 vmw_kms_resume(&dev_priv->drm); 1591 1592 return 0; 1593 } 1594 1595 static const struct dev_pm_ops vmw_pm_ops = { 1596 .freeze = vmw_pm_freeze, 1597 .thaw = vmw_pm_restore, 1598 .restore = vmw_pm_restore, 1599 .suspend = vmw_pm_suspend, 1600 .resume = vmw_pm_resume, 1601 }; 1602 1603 static const struct file_operations vmwgfx_driver_fops = { 1604 .owner = THIS_MODULE, 1605 .open = drm_open, 1606 .release = drm_release, 1607 .unlocked_ioctl = vmw_unlocked_ioctl, 1608 .mmap = drm_gem_mmap, 1609 .poll = drm_poll, 1610 .read = drm_read, 1611 #if defined(CONFIG_COMPAT) 1612 .compat_ioctl = vmw_compat_ioctl, 1613 #endif 1614 .llseek = noop_llseek, 1615 }; 1616 1617 static const struct drm_driver driver = { 1618 .driver_features = 1619 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT, 1620 .ioctls = vmw_ioctls, 1621 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1622 .master_set = vmw_master_set, 1623 .master_drop = vmw_master_drop, 1624 .open = vmw_driver_open, 1625 .postclose = vmw_postclose, 1626 1627 .dumb_create = vmw_dumb_create, 1628 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1629 1630 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1631 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1632 1633 .fops = &vmwgfx_driver_fops, 1634 .name = VMWGFX_DRIVER_NAME, 1635 .desc = VMWGFX_DRIVER_DESC, 1636 .date = VMWGFX_DRIVER_DATE, 1637 .major = VMWGFX_DRIVER_MAJOR, 1638 .minor = VMWGFX_DRIVER_MINOR, 1639 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1640 }; 1641 1642 static struct pci_driver vmw_pci_driver = { 1643 .name = VMWGFX_DRIVER_NAME, 1644 .id_table = vmw_pci_id_list, 1645 .probe = vmw_probe, 1646 .remove = vmw_remove, 1647 .driver = { 1648 .pm = &vmw_pm_ops 1649 } 1650 }; 1651 1652 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1653 { 1654 struct vmw_private *vmw; 1655 int ret; 1656 1657 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver); 1658 if (ret) 1659 goto out_error; 1660 1661 ret = pcim_enable_device(pdev); 1662 if (ret) 1663 goto out_error; 1664 1665 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1666 struct vmw_private, drm); 1667 if (IS_ERR(vmw)) { 1668 ret = PTR_ERR(vmw); 1669 goto out_error; 1670 } 1671 1672 pci_set_drvdata(pdev, &vmw->drm); 1673 1674 ret = vmw_driver_load(vmw, ent->device); 1675 if (ret) 1676 goto out_error; 1677 1678 ret = drm_dev_register(&vmw->drm, 0); 1679 if (ret) 1680 goto out_unload; 1681 1682 vmw_fifo_resource_inc(vmw); 1683 vmw_svga_enable(vmw); 1684 drm_fbdev_generic_setup(&vmw->drm, 0); 1685 1686 vmw_debugfs_gem_init(vmw); 1687 vmw_debugfs_resource_managers_init(vmw); 1688 1689 return 0; 1690 out_unload: 1691 vmw_driver_unload(&vmw->drm); 1692 out_error: 1693 return ret; 1694 } 1695 1696 drm_module_pci_driver(vmw_pci_driver); 1697 1698 MODULE_AUTHOR("VMware Inc. and others"); 1699 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1700 MODULE_LICENSE("GPL and additional rights"); 1701 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1702 __stringify(VMWGFX_DRIVER_MINOR) "." 1703 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1704 "0"); 1705