1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 #include "vmwgfx_drv.h" 30 31 #include "vmwgfx_bo.h" 32 #include "vmwgfx_binding.h" 33 #include "vmwgfx_devcaps.h" 34 #include "vmwgfx_mksstat.h" 35 #include "vmwgfx_vkms.h" 36 #include "ttm_object.h" 37 38 #include <drm/drm_aperture.h> 39 #include <drm/drm_client_setup.h> 40 #include <drm/drm_drv.h> 41 #include <drm/drm_fbdev_ttm.h> 42 #include <drm/drm_gem_ttm_helper.h> 43 #include <drm/drm_ioctl.h> 44 #include <drm/drm_module.h> 45 #include <drm/drm_sysfs.h> 46 #include <drm/ttm/ttm_range_manager.h> 47 #include <drm/ttm/ttm_placement.h> 48 #include <generated/utsrelease.h> 49 50 #ifdef CONFIG_X86 51 #include <asm/hypervisor.h> 52 #endif 53 #include <linux/cc_platform.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/module.h> 56 #include <linux/pci.h> 57 #include <linux/version.h> 58 #include <linux/vmalloc.h> 59 60 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 61 62 /* 63 * Fully encoded drm commands. Might move to vmw_drm.h 64 */ 65 66 #define DRM_IOCTL_VMW_GET_PARAM \ 67 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 68 struct drm_vmw_getparam_arg) 69 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 70 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 71 union drm_vmw_alloc_dmabuf_arg) 72 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 73 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 74 struct drm_vmw_unref_dmabuf_arg) 75 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 76 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 77 struct drm_vmw_cursor_bypass_arg) 78 79 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 80 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 81 struct drm_vmw_control_stream_arg) 82 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 83 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 84 struct drm_vmw_stream_arg) 85 #define DRM_IOCTL_VMW_UNREF_STREAM \ 86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 87 struct drm_vmw_stream_arg) 88 89 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 90 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 91 struct drm_vmw_context_arg) 92 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 93 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 94 struct drm_vmw_context_arg) 95 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 96 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 97 union drm_vmw_surface_create_arg) 98 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 99 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 100 struct drm_vmw_surface_arg) 101 #define DRM_IOCTL_VMW_REF_SURFACE \ 102 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 103 union drm_vmw_surface_reference_arg) 104 #define DRM_IOCTL_VMW_EXECBUF \ 105 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 106 struct drm_vmw_execbuf_arg) 107 #define DRM_IOCTL_VMW_GET_3D_CAP \ 108 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 109 struct drm_vmw_get_3d_cap_arg) 110 #define DRM_IOCTL_VMW_FENCE_WAIT \ 111 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 112 struct drm_vmw_fence_wait_arg) 113 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 114 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 115 struct drm_vmw_fence_signaled_arg) 116 #define DRM_IOCTL_VMW_FENCE_UNREF \ 117 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 118 struct drm_vmw_fence_arg) 119 #define DRM_IOCTL_VMW_FENCE_EVENT \ 120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 121 struct drm_vmw_fence_event_arg) 122 #define DRM_IOCTL_VMW_PRESENT \ 123 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 124 struct drm_vmw_present_arg) 125 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 126 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 127 struct drm_vmw_present_readback_arg) 128 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 129 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 130 struct drm_vmw_update_layout_arg) 131 #define DRM_IOCTL_VMW_CREATE_SHADER \ 132 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 133 struct drm_vmw_shader_create_arg) 134 #define DRM_IOCTL_VMW_UNREF_SHADER \ 135 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 136 struct drm_vmw_shader_arg) 137 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 138 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 139 union drm_vmw_gb_surface_create_arg) 140 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 141 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 142 union drm_vmw_gb_surface_reference_arg) 143 #define DRM_IOCTL_VMW_SYNCCPU \ 144 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 145 struct drm_vmw_synccpu_arg) 146 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 147 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 148 struct drm_vmw_context_arg) 149 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 150 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 151 union drm_vmw_gb_surface_create_ext_arg) 152 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 153 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 154 union drm_vmw_gb_surface_reference_ext_arg) 155 #define DRM_IOCTL_VMW_MSG \ 156 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 157 struct drm_vmw_msg_arg) 158 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 159 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 160 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 161 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 162 struct drm_vmw_mksstat_add_arg) 163 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 164 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 165 struct drm_vmw_mksstat_remove_arg) 166 167 /* 168 * Ioctl definitions. 169 */ 170 171 static const struct drm_ioctl_desc vmw_ioctls[] = { 172 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 173 DRM_RENDER_ALLOW), 174 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 175 DRM_RENDER_ALLOW), 176 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 177 DRM_RENDER_ALLOW), 178 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 179 vmw_kms_cursor_bypass_ioctl, 180 DRM_MASTER), 181 182 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 183 DRM_MASTER), 184 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 185 DRM_MASTER), 186 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 187 DRM_MASTER), 188 189 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 190 DRM_RENDER_ALLOW), 191 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 192 DRM_RENDER_ALLOW), 193 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 194 DRM_RENDER_ALLOW), 195 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 196 DRM_RENDER_ALLOW), 197 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 198 DRM_RENDER_ALLOW), 199 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 200 DRM_RENDER_ALLOW), 201 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 202 DRM_RENDER_ALLOW), 203 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 204 vmw_fence_obj_signaled_ioctl, 205 DRM_RENDER_ALLOW), 206 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 207 DRM_RENDER_ALLOW), 208 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 209 DRM_RENDER_ALLOW), 210 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 211 DRM_RENDER_ALLOW), 212 213 /* these allow direct access to the framebuffers mark as master only */ 214 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 215 DRM_MASTER | DRM_AUTH), 216 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 217 vmw_present_readback_ioctl, 218 DRM_MASTER | DRM_AUTH), 219 /* 220 * The permissions of the below ioctl are overridden in 221 * vmw_generic_ioctl(). We require either 222 * DRM_MASTER or capable(CAP_SYS_ADMIN). 223 */ 224 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 225 vmw_kms_update_layout_ioctl, 226 DRM_RENDER_ALLOW), 227 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 228 vmw_shader_define_ioctl, 229 DRM_RENDER_ALLOW), 230 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 231 vmw_shader_destroy_ioctl, 232 DRM_RENDER_ALLOW), 233 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 234 vmw_gb_surface_define_ioctl, 235 DRM_RENDER_ALLOW), 236 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 237 vmw_gb_surface_reference_ioctl, 238 DRM_RENDER_ALLOW), 239 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 240 vmw_user_bo_synccpu_ioctl, 241 DRM_RENDER_ALLOW), 242 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 243 vmw_extended_context_define_ioctl, 244 DRM_RENDER_ALLOW), 245 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 246 vmw_gb_surface_define_ext_ioctl, 247 DRM_RENDER_ALLOW), 248 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 249 vmw_gb_surface_reference_ext_ioctl, 250 DRM_RENDER_ALLOW), 251 DRM_IOCTL_DEF_DRV(VMW_MSG, 252 vmw_msg_ioctl, 253 DRM_RENDER_ALLOW), 254 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 255 vmw_mksstat_reset_ioctl, 256 DRM_RENDER_ALLOW), 257 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 258 vmw_mksstat_add_ioctl, 259 DRM_RENDER_ALLOW), 260 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 261 vmw_mksstat_remove_ioctl, 262 DRM_RENDER_ALLOW), 263 }; 264 265 static const struct pci_device_id vmw_pci_id_list[] = { 266 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 267 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 268 { } 269 }; 270 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 271 272 static int vmw_restrict_iommu; 273 static int vmw_force_coherent; 274 static int vmw_restrict_dma_mask; 275 static int vmw_assume_16bpp; 276 277 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 278 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 279 void *ptr); 280 281 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 282 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 283 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 284 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 285 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 286 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 287 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 288 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 289 290 291 struct bitmap_name { 292 uint32 value; 293 const char *name; 294 }; 295 296 static const struct bitmap_name cap1_names[] = { 297 { SVGA_CAP_RECT_COPY, "rect copy" }, 298 { SVGA_CAP_CURSOR, "cursor" }, 299 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 300 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 301 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 302 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 303 { SVGA_CAP_3D, "3D" }, 304 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 305 { SVGA_CAP_MULTIMON, "multimon" }, 306 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 307 { SVGA_CAP_IRQMASK, "irq mask" }, 308 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 309 { SVGA_CAP_GMR, "gmr" }, 310 { SVGA_CAP_TRACES, "traces" }, 311 { SVGA_CAP_GMR2, "gmr2" }, 312 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 313 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 314 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 315 { SVGA_CAP_GBOBJECTS, "gbobject" }, 316 { SVGA_CAP_DX, "dx" }, 317 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 318 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 319 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 320 }; 321 322 323 static const struct bitmap_name cap2_names[] = { 324 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 325 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 326 { SVGA_CAP2_DX2, "dx2" }, 327 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 328 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 329 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 330 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 331 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 332 { SVGA_CAP2_MSHINT, "mshint" }, 333 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 334 { SVGA_CAP2_DX3, "dx3" }, 335 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 336 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 337 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 338 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 339 { SVGA_CAP2_LO_STAGING, "lo staging" }, 340 }; 341 342 static void vmw_print_bitmap(struct drm_device *drm, 343 const char *prefix, uint32_t bitmap, 344 const struct bitmap_name *bnames, 345 uint32_t num_names) 346 { 347 char buf[512]; 348 uint32_t i; 349 uint32_t offset = 0; 350 for (i = 0; i < num_names; ++i) { 351 if ((bitmap & bnames[i].value) != 0) { 352 offset += snprintf(buf + offset, 353 ARRAY_SIZE(buf) - offset, 354 "%s, ", bnames[i].name); 355 bitmap &= ~bnames[i].value; 356 } 357 } 358 359 drm_info(drm, "%s: %s\n", prefix, buf); 360 if (bitmap != 0) 361 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 362 } 363 364 365 static void vmw_print_sm_type(struct vmw_private *dev_priv) 366 { 367 static const char *names[] = { 368 [VMW_SM_LEGACY] = "Legacy", 369 [VMW_SM_4] = "SM4", 370 [VMW_SM_4_1] = "SM4_1", 371 [VMW_SM_5] = "SM_5", 372 [VMW_SM_5_1X] = "SM_5_1X", 373 [VMW_SM_MAX] = "Invalid" 374 }; 375 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 376 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 377 names[dev_priv->sm_type]); 378 } 379 380 /** 381 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 382 * 383 * @dev_priv: A device private structure. 384 * 385 * This function creates a small buffer object that holds the query 386 * result for dummy queries emitted as query barriers. 387 * The function will then map the first page and initialize a pending 388 * occlusion query result structure, Finally it will unmap the buffer. 389 * No interruptible waits are done within this function. 390 * 391 * Returns an error if bo creation or initialization fails. 392 */ 393 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 394 { 395 int ret; 396 struct vmw_bo *vbo; 397 struct ttm_bo_kmap_obj map; 398 volatile SVGA3dQueryResult *result; 399 bool dummy; 400 struct vmw_bo_params bo_params = { 401 .domain = VMW_BO_DOMAIN_SYS, 402 .busy_domain = VMW_BO_DOMAIN_SYS, 403 .bo_type = ttm_bo_type_kernel, 404 .size = PAGE_SIZE, 405 .pin = true 406 }; 407 408 /* 409 * Create the vbo as pinned, so that a tryreserve will 410 * immediately succeed. This is because we're the only 411 * user of the bo currently. 412 */ 413 ret = vmw_bo_create(dev_priv, &bo_params, &vbo); 414 if (unlikely(ret != 0)) 415 return ret; 416 417 ret = ttm_bo_reserve(&vbo->tbo, false, true, NULL); 418 BUG_ON(ret != 0); 419 vmw_bo_pin_reserved(vbo, true); 420 421 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map); 422 if (likely(ret == 0)) { 423 result = ttm_kmap_obj_virtual(&map, &dummy); 424 result->totalSize = sizeof(*result); 425 result->state = SVGA3D_QUERYSTATE_PENDING; 426 result->result32 = 0xff; 427 ttm_bo_kunmap(&map); 428 } 429 vmw_bo_pin_reserved(vbo, false); 430 ttm_bo_unreserve(&vbo->tbo); 431 432 if (unlikely(ret != 0)) { 433 DRM_ERROR("Dummy query buffer map failed.\n"); 434 vmw_bo_unreference(&vbo); 435 } else 436 dev_priv->dummy_query_bo = vbo; 437 438 return ret; 439 } 440 441 static int vmw_device_init(struct vmw_private *dev_priv) 442 { 443 bool uses_fb_traces = false; 444 445 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 446 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 447 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 448 449 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 450 SVGA_REG_ENABLE_HIDE); 451 452 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 453 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 454 455 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 456 dev_priv->fifo = vmw_fifo_create(dev_priv); 457 if (IS_ERR(dev_priv->fifo)) { 458 int err = PTR_ERR(dev_priv->fifo); 459 dev_priv->fifo = NULL; 460 return err; 461 } else if (!dev_priv->fifo) { 462 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 463 } 464 465 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 466 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 467 return 0; 468 } 469 470 static void vmw_device_fini(struct vmw_private *vmw) 471 { 472 /* 473 * Legacy sync 474 */ 475 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 476 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 477 ; 478 479 vmw->last_read_seqno = vmw_fence_read(vmw); 480 481 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 482 vmw->config_done_state); 483 vmw_write(vmw, SVGA_REG_ENABLE, 484 vmw->enable_state); 485 vmw_write(vmw, SVGA_REG_TRACES, 486 vmw->traces_state); 487 488 vmw_fifo_destroy(vmw); 489 } 490 491 /** 492 * vmw_request_device_late - Perform late device setup 493 * 494 * @dev_priv: Pointer to device private. 495 * 496 * This function performs setup of otables and enables large command 497 * buffer submission. These tasks are split out to a separate function 498 * because it reverts vmw_release_device_early and is intended to be used 499 * by an error path in the hibernation code. 500 */ 501 static int vmw_request_device_late(struct vmw_private *dev_priv) 502 { 503 int ret; 504 505 if (dev_priv->has_mob) { 506 ret = vmw_otables_setup(dev_priv); 507 if (unlikely(ret != 0)) { 508 DRM_ERROR("Unable to initialize " 509 "guest Memory OBjects.\n"); 510 return ret; 511 } 512 } 513 514 if (dev_priv->cman) { 515 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 516 if (ret) { 517 struct vmw_cmdbuf_man *man = dev_priv->cman; 518 519 dev_priv->cman = NULL; 520 vmw_cmdbuf_man_destroy(man); 521 } 522 } 523 524 return 0; 525 } 526 527 static int vmw_request_device(struct vmw_private *dev_priv) 528 { 529 int ret; 530 531 ret = vmw_device_init(dev_priv); 532 if (unlikely(ret != 0)) { 533 DRM_ERROR("Unable to initialize the device.\n"); 534 return ret; 535 } 536 vmw_fence_fifo_up(dev_priv->fman); 537 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 538 if (IS_ERR(dev_priv->cman)) { 539 dev_priv->cman = NULL; 540 dev_priv->sm_type = VMW_SM_LEGACY; 541 } 542 543 ret = vmw_request_device_late(dev_priv); 544 if (ret) 545 goto out_no_mob; 546 547 ret = vmw_dummy_query_bo_create(dev_priv); 548 if (unlikely(ret != 0)) 549 goto out_no_query_bo; 550 551 return 0; 552 553 out_no_query_bo: 554 if (dev_priv->cman) 555 vmw_cmdbuf_remove_pool(dev_priv->cman); 556 if (dev_priv->has_mob) { 557 struct ttm_resource_manager *man; 558 559 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 560 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 561 vmw_otables_takedown(dev_priv); 562 } 563 if (dev_priv->cman) 564 vmw_cmdbuf_man_destroy(dev_priv->cman); 565 out_no_mob: 566 vmw_fence_fifo_down(dev_priv->fman); 567 vmw_device_fini(dev_priv); 568 return ret; 569 } 570 571 /** 572 * vmw_release_device_early - Early part of fifo takedown. 573 * 574 * @dev_priv: Pointer to device private struct. 575 * 576 * This is the first part of command submission takedown, to be called before 577 * buffer management is taken down. 578 */ 579 static void vmw_release_device_early(struct vmw_private *dev_priv) 580 { 581 /* 582 * Previous destructions should've released 583 * the pinned bo. 584 */ 585 586 BUG_ON(dev_priv->pinned_bo != NULL); 587 588 vmw_bo_unreference(&dev_priv->dummy_query_bo); 589 if (dev_priv->cman) 590 vmw_cmdbuf_remove_pool(dev_priv->cman); 591 592 if (dev_priv->has_mob) { 593 struct ttm_resource_manager *man; 594 595 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 596 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 597 vmw_otables_takedown(dev_priv); 598 } 599 } 600 601 /** 602 * vmw_release_device_late - Late part of fifo takedown. 603 * 604 * @dev_priv: Pointer to device private struct. 605 * 606 * This is the last part of the command submission takedown, to be called when 607 * command submission is no longer needed. It may wait on pending fences. 608 */ 609 static void vmw_release_device_late(struct vmw_private *dev_priv) 610 { 611 vmw_fence_fifo_down(dev_priv->fman); 612 if (dev_priv->cman) 613 vmw_cmdbuf_man_destroy(dev_priv->cman); 614 615 vmw_device_fini(dev_priv); 616 } 617 618 /* 619 * Sets the initial_[width|height] fields on the given vmw_private. 620 * 621 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 622 * clamping the value to fb_max_[width|height] fields and the 623 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 624 * If the values appear to be invalid, set them to 625 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 626 */ 627 static void vmw_get_initial_size(struct vmw_private *dev_priv) 628 { 629 uint32_t width; 630 uint32_t height; 631 632 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 633 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 634 635 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH); 636 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT); 637 638 if (width > dev_priv->fb_max_width || 639 height > dev_priv->fb_max_height) { 640 641 /* 642 * This is a host error and shouldn't occur. 643 */ 644 645 width = VMWGFX_MIN_INITIAL_WIDTH; 646 height = VMWGFX_MIN_INITIAL_HEIGHT; 647 } 648 649 dev_priv->initial_width = width; 650 dev_priv->initial_height = height; 651 } 652 653 /** 654 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 655 * system. 656 * 657 * @dev_priv: Pointer to a struct vmw_private 658 * 659 * This functions tries to determine what actions need to be taken by the 660 * driver to make system pages visible to the device. 661 * If this function decides that DMA is not possible, it returns -EINVAL. 662 * The driver may then try to disable features of the device that require 663 * DMA. 664 */ 665 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 666 { 667 static const char *names[vmw_dma_map_max] = { 668 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 669 [vmw_dma_map_populate] = "Caching DMA mappings.", 670 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 671 672 /* 673 * When running with SEV we always want dma mappings, because 674 * otherwise ttm tt pool pages will bounce through swiotlb running 675 * out of available space. 676 */ 677 if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 678 dev_priv->map_mode = vmw_dma_alloc_coherent; 679 else if (vmw_restrict_iommu) 680 dev_priv->map_mode = vmw_dma_map_bind; 681 else 682 dev_priv->map_mode = vmw_dma_map_populate; 683 684 drm_info(&dev_priv->drm, 685 "DMA map mode: %s\n", names[dev_priv->map_mode]); 686 return 0; 687 } 688 689 /** 690 * vmw_dma_masks - set required page- and dma masks 691 * 692 * @dev_priv: Pointer to struct drm-device 693 * 694 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 695 * restriction also for 64-bit systems. 696 */ 697 static int vmw_dma_masks(struct vmw_private *dev_priv) 698 { 699 struct drm_device *dev = &dev_priv->drm; 700 int ret = 0; 701 702 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 703 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 704 drm_info(&dev_priv->drm, 705 "Restricting DMA addresses to 44 bits.\n"); 706 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 707 } 708 709 return ret; 710 } 711 712 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 713 { 714 int ret; 715 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 716 dev_priv->vram_size >> PAGE_SHIFT); 717 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 718 return ret; 719 } 720 721 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 722 { 723 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 724 } 725 726 static int vmw_setup_pci_resources(struct vmw_private *dev, 727 u32 pci_id) 728 { 729 resource_size_t rmmio_start; 730 resource_size_t rmmio_size; 731 resource_size_t fifo_start; 732 resource_size_t fifo_size; 733 int ret; 734 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 735 736 pci_set_master(pdev); 737 738 ret = pci_request_regions(pdev, "vmwgfx probe"); 739 if (ret) 740 return ret; 741 742 dev->pci_id = pci_id; 743 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 744 rmmio_start = pci_resource_start(pdev, 0); 745 rmmio_size = pci_resource_len(pdev, 0); 746 dev->vram_start = pci_resource_start(pdev, 2); 747 dev->vram_size = pci_resource_len(pdev, 2); 748 749 drm_info(&dev->drm, 750 "Register MMIO at 0x%pa size is %llu KiB\n", 751 &rmmio_start, (uint64_t)rmmio_size / 1024); 752 dev->rmmio = devm_ioremap(dev->drm.dev, 753 rmmio_start, 754 rmmio_size); 755 if (!dev->rmmio) { 756 drm_err(&dev->drm, 757 "Failed mapping registers mmio memory.\n"); 758 pci_release_regions(pdev); 759 return -ENOMEM; 760 } 761 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 762 dev->io_start = pci_resource_start(pdev, 0); 763 dev->vram_start = pci_resource_start(pdev, 1); 764 dev->vram_size = pci_resource_len(pdev, 1); 765 fifo_start = pci_resource_start(pdev, 2); 766 fifo_size = pci_resource_len(pdev, 2); 767 768 drm_info(&dev->drm, 769 "FIFO at %pa size is %llu KiB\n", 770 &fifo_start, (uint64_t)fifo_size / 1024); 771 dev->fifo_mem = devm_memremap(dev->drm.dev, 772 fifo_start, 773 fifo_size, 774 MEMREMAP_WB); 775 776 if (IS_ERR(dev->fifo_mem)) { 777 drm_err(&dev->drm, 778 "Failed mapping FIFO memory.\n"); 779 pci_release_regions(pdev); 780 return PTR_ERR(dev->fifo_mem); 781 } 782 } else { 783 pci_release_regions(pdev); 784 return -EINVAL; 785 } 786 787 /* 788 * This is approximate size of the vram, the exact size will only 789 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 790 * size will be equal to or bigger than the size reported by 791 * SVGA_REG_VRAM_SIZE. 792 */ 793 drm_info(&dev->drm, 794 "VRAM at %pa size is %llu KiB\n", 795 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 796 797 return 0; 798 } 799 800 static int vmw_detect_version(struct vmw_private *dev) 801 { 802 uint32_t svga_id; 803 804 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 805 SVGA_ID_3 : SVGA_ID_2); 806 svga_id = vmw_read(dev, SVGA_REG_ID); 807 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 808 drm_err(&dev->drm, 809 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 810 svga_id, dev->pci_id); 811 return -ENOSYS; 812 } 813 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 814 drm_info(&dev->drm, 815 "Running on SVGA version %d.\n", (svga_id & 0xff)); 816 return 0; 817 } 818 819 static void vmw_write_driver_id(struct vmw_private *dev) 820 { 821 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) { 822 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 823 SVGA_REG_GUEST_DRIVER_ID_LINUX); 824 825 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1, 826 LINUX_VERSION_MAJOR << 24 | 827 LINUX_VERSION_PATCHLEVEL << 16 | 828 LINUX_VERSION_SUBLEVEL); 829 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2, 830 VMWGFX_DRIVER_MAJOR << 24 | 831 VMWGFX_DRIVER_MINOR << 16 | 832 VMWGFX_DRIVER_PATCHLEVEL); 833 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0); 834 835 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 836 SVGA_REG_GUEST_DRIVER_ID_SUBMIT); 837 } 838 } 839 840 static void vmw_sw_context_init(struct vmw_private *dev_priv) 841 { 842 struct vmw_sw_context *sw_context = &dev_priv->ctx; 843 844 hash_init(sw_context->res_ht); 845 } 846 847 static void vmw_sw_context_fini(struct vmw_private *dev_priv) 848 { 849 struct vmw_sw_context *sw_context = &dev_priv->ctx; 850 851 vfree(sw_context->cmd_bounce); 852 if (sw_context->staged_bindings) 853 vmw_binding_state_free(sw_context->staged_bindings); 854 } 855 856 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 857 { 858 int ret; 859 enum vmw_res_type i; 860 bool refuse_dma = false; 861 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 862 863 vmw_sw_context_init(dev_priv); 864 865 mutex_init(&dev_priv->cmdbuf_mutex); 866 mutex_init(&dev_priv->binding_mutex); 867 spin_lock_init(&dev_priv->resource_lock); 868 spin_lock_init(&dev_priv->hw_lock); 869 spin_lock_init(&dev_priv->waiter_lock); 870 spin_lock_init(&dev_priv->cursor_lock); 871 872 ret = vmw_setup_pci_resources(dev_priv, pci_id); 873 if (ret) 874 return ret; 875 ret = vmw_detect_version(dev_priv); 876 if (ret) 877 goto out_no_pci_or_version; 878 879 880 for (i = vmw_res_context; i < vmw_res_max; ++i) { 881 idr_init_base(&dev_priv->res_idr[i], 1); 882 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 883 } 884 885 init_waitqueue_head(&dev_priv->fence_queue); 886 init_waitqueue_head(&dev_priv->fifo_queue); 887 dev_priv->fence_queue_waiters = 0; 888 dev_priv->fifo_queue_waiters = 0; 889 890 dev_priv->used_memory_size = 0; 891 892 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 893 894 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 895 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 896 dev_priv->capabilities, 897 cap1_names, ARRAY_SIZE(cap1_names)); 898 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 899 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 900 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 901 dev_priv->capabilities2, 902 cap2_names, ARRAY_SIZE(cap2_names)); 903 } 904 905 if (!vmwgfx_supported(dev_priv)) { 906 vmw_disable_backdoor(); 907 drm_err_once(&dev_priv->drm, 908 "vmwgfx seems to be running on an unsupported hypervisor."); 909 drm_err_once(&dev_priv->drm, 910 "This configuration is likely broken."); 911 drm_err_once(&dev_priv->drm, 912 "Please switch to a supported graphics device to avoid problems."); 913 } 914 915 vmw_vkms_init(dev_priv); 916 917 ret = vmw_dma_select_mode(dev_priv); 918 if (unlikely(ret != 0)) { 919 drm_info(&dev_priv->drm, 920 "Restricting capabilities since DMA not available.\n"); 921 refuse_dma = true; 922 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 923 drm_info(&dev_priv->drm, 924 "Disabling 3D acceleration.\n"); 925 } 926 927 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 928 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 929 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 930 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 931 932 vmw_get_initial_size(dev_priv); 933 934 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 935 dev_priv->max_gmr_ids = 936 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 937 dev_priv->max_gmr_pages = 938 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 939 dev_priv->memory_size = 940 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 941 dev_priv->memory_size -= dev_priv->vram_size; 942 } else { 943 /* 944 * An arbitrary limit of 512MiB on surface 945 * memory. But all HWV8 hardware supports GMR2. 946 */ 947 dev_priv->memory_size = 512*1024*1024; 948 } 949 dev_priv->max_mob_pages = 0; 950 dev_priv->max_mob_size = 0; 951 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 952 uint64_t mem_size; 953 954 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 955 mem_size = vmw_read(dev_priv, 956 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 957 else 958 mem_size = 959 vmw_read(dev_priv, 960 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 961 962 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 963 dev_priv->max_primary_mem = 964 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 965 dev_priv->max_mob_size = 966 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 967 dev_priv->stdu_max_width = 968 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 969 dev_priv->stdu_max_height = 970 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 971 972 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 973 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 974 dev_priv->texture_max_width = vmw_read(dev_priv, 975 SVGA_REG_DEV_CAP); 976 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 977 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 978 dev_priv->texture_max_height = vmw_read(dev_priv, 979 SVGA_REG_DEV_CAP); 980 } else { 981 dev_priv->texture_max_width = 8192; 982 dev_priv->texture_max_height = 8192; 983 dev_priv->max_primary_mem = dev_priv->vram_size; 984 } 985 drm_info(&dev_priv->drm, 986 "Legacy memory limits: VRAM = %llu KiB, FIFO = %llu KiB, surface = %u KiB\n", 987 (u64)dev_priv->vram_size / 1024, 988 (u64)dev_priv->fifo_mem_size / 1024, 989 dev_priv->memory_size / 1024); 990 991 drm_info(&dev_priv->drm, 992 "MOB limits: max mob size = %u KiB, max mob pages = %u\n", 993 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 994 995 ret = vmw_dma_masks(dev_priv); 996 if (unlikely(ret != 0)) 997 goto out_err0; 998 999 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 1000 1001 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 1002 drm_info(&dev_priv->drm, 1003 "Max GMR ids is %u\n", 1004 (unsigned)dev_priv->max_gmr_ids); 1005 drm_info(&dev_priv->drm, 1006 "Max number of GMR pages is %u\n", 1007 (unsigned)dev_priv->max_gmr_pages); 1008 } 1009 drm_info(&dev_priv->drm, 1010 "Maximum display memory size is %llu KiB\n", 1011 (uint64_t)dev_priv->max_primary_mem / 1024); 1012 1013 /* Need mmio memory to check for fifo pitchlock cap. */ 1014 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 1015 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 1016 !vmw_fifo_have_pitchlock(dev_priv)) { 1017 ret = -ENOSYS; 1018 DRM_ERROR("Hardware has no pitchlock\n"); 1019 goto out_err0; 1020 } 1021 1022 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops); 1023 1024 if (unlikely(dev_priv->tdev == NULL)) { 1025 drm_err(&dev_priv->drm, 1026 "Unable to initialize TTM object management.\n"); 1027 ret = -ENOMEM; 1028 goto out_err0; 1029 } 1030 1031 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 1032 ret = vmw_irq_install(dev_priv); 1033 if (ret != 0) { 1034 drm_err(&dev_priv->drm, 1035 "Failed installing irq: %d\n", ret); 1036 goto out_no_irq; 1037 } 1038 } 1039 1040 dev_priv->fman = vmw_fence_manager_init(dev_priv); 1041 if (unlikely(dev_priv->fman == NULL)) { 1042 ret = -ENOMEM; 1043 goto out_no_fman; 1044 } 1045 1046 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1047 dev_priv->drm.dev, 1048 dev_priv->drm.anon_inode->i_mapping, 1049 dev_priv->drm.vma_offset_manager, 1050 dev_priv->map_mode == vmw_dma_alloc_coherent, 1051 false); 1052 if (unlikely(ret != 0)) { 1053 drm_err(&dev_priv->drm, 1054 "Failed initializing TTM buffer object driver.\n"); 1055 goto out_no_bdev; 1056 } 1057 1058 /* 1059 * Enable VRAM, but initially don't use it until SVGA is enabled and 1060 * unhidden. 1061 */ 1062 1063 ret = vmw_vram_manager_init(dev_priv); 1064 if (unlikely(ret != 0)) { 1065 drm_err(&dev_priv->drm, 1066 "Failed initializing memory manager for VRAM.\n"); 1067 goto out_no_vram; 1068 } 1069 1070 ret = vmw_devcaps_create(dev_priv); 1071 if (unlikely(ret != 0)) { 1072 drm_err(&dev_priv->drm, 1073 "Failed initializing device caps.\n"); 1074 goto out_no_vram; 1075 } 1076 1077 /* 1078 * "Guest Memory Regions" is an aperture like feature with 1079 * one slot per bo. There is an upper limit of the number of 1080 * slots as well as the bo size. 1081 */ 1082 dev_priv->has_gmr = true; 1083 /* TODO: This is most likely not correct */ 1084 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1085 refuse_dma || 1086 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1087 drm_info(&dev_priv->drm, 1088 "No GMR memory available. " 1089 "Graphics memory resources are very limited.\n"); 1090 dev_priv->has_gmr = false; 1091 } 1092 1093 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1094 dev_priv->has_mob = true; 1095 1096 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1097 drm_info(&dev_priv->drm, 1098 "No MOB memory available. " 1099 "3D will be disabled.\n"); 1100 dev_priv->has_mob = false; 1101 } 1102 if (vmw_sys_man_init(dev_priv) != 0) { 1103 drm_info(&dev_priv->drm, 1104 "No MOB page table memory available. " 1105 "3D will be disabled.\n"); 1106 dev_priv->has_mob = false; 1107 } 1108 } 1109 1110 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1111 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1112 dev_priv->sm_type = VMW_SM_4; 1113 } 1114 1115 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1116 if (has_sm4_context(dev_priv) && 1117 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1118 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1119 dev_priv->sm_type = VMW_SM_4_1; 1120 if (has_sm4_1_context(dev_priv) && 1121 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1122 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1123 dev_priv->sm_type = VMW_SM_5; 1124 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1125 dev_priv->sm_type = VMW_SM_5_1X; 1126 } 1127 } 1128 } 1129 1130 ret = vmw_kms_init(dev_priv); 1131 if (unlikely(ret != 0)) 1132 goto out_no_kms; 1133 vmw_overlay_init(dev_priv); 1134 1135 ret = vmw_request_device(dev_priv); 1136 if (ret) 1137 goto out_no_fifo; 1138 1139 vmw_print_sm_type(dev_priv); 1140 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1141 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1142 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1143 vmw_write_driver_id(dev_priv); 1144 1145 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1146 register_pm_notifier(&dev_priv->pm_nb); 1147 1148 return 0; 1149 1150 out_no_fifo: 1151 vmw_overlay_close(dev_priv); 1152 vmw_kms_close(dev_priv); 1153 out_no_kms: 1154 if (dev_priv->has_mob) { 1155 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1156 vmw_sys_man_fini(dev_priv); 1157 } 1158 if (dev_priv->has_gmr) 1159 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1160 vmw_devcaps_destroy(dev_priv); 1161 vmw_vram_manager_fini(dev_priv); 1162 out_no_vram: 1163 ttm_device_fini(&dev_priv->bdev); 1164 out_no_bdev: 1165 vmw_fence_manager_takedown(dev_priv->fman); 1166 out_no_fman: 1167 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1168 vmw_irq_uninstall(&dev_priv->drm); 1169 out_no_irq: 1170 ttm_object_device_release(&dev_priv->tdev); 1171 out_err0: 1172 for (i = vmw_res_context; i < vmw_res_max; ++i) 1173 idr_destroy(&dev_priv->res_idr[i]); 1174 1175 if (dev_priv->ctx.staged_bindings) 1176 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1177 out_no_pci_or_version: 1178 pci_release_regions(pdev); 1179 return ret; 1180 } 1181 1182 static void vmw_driver_unload(struct drm_device *dev) 1183 { 1184 struct vmw_private *dev_priv = vmw_priv(dev); 1185 struct pci_dev *pdev = to_pci_dev(dev->dev); 1186 enum vmw_res_type i; 1187 1188 unregister_pm_notifier(&dev_priv->pm_nb); 1189 1190 vmw_sw_context_fini(dev_priv); 1191 vmw_fifo_resource_dec(dev_priv); 1192 1193 vmw_svga_disable(dev_priv); 1194 1195 vmw_vkms_cleanup(dev_priv); 1196 vmw_kms_close(dev_priv); 1197 vmw_overlay_close(dev_priv); 1198 1199 if (dev_priv->has_gmr) 1200 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1201 1202 vmw_release_device_early(dev_priv); 1203 if (dev_priv->has_mob) { 1204 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1205 vmw_sys_man_fini(dev_priv); 1206 } 1207 vmw_devcaps_destroy(dev_priv); 1208 vmw_vram_manager_fini(dev_priv); 1209 ttm_device_fini(&dev_priv->bdev); 1210 vmw_release_device_late(dev_priv); 1211 vmw_fence_manager_takedown(dev_priv->fman); 1212 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1213 vmw_irq_uninstall(&dev_priv->drm); 1214 1215 ttm_object_device_release(&dev_priv->tdev); 1216 1217 for (i = vmw_res_context; i < vmw_res_max; ++i) 1218 idr_destroy(&dev_priv->res_idr[i]); 1219 1220 vmw_mksstat_remove_all(dev_priv); 1221 1222 pci_release_regions(pdev); 1223 } 1224 1225 static void vmw_postclose(struct drm_device *dev, 1226 struct drm_file *file_priv) 1227 { 1228 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1229 1230 ttm_object_file_release(&vmw_fp->tfile); 1231 kfree(vmw_fp); 1232 } 1233 1234 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1235 { 1236 struct vmw_private *dev_priv = vmw_priv(dev); 1237 struct vmw_fpriv *vmw_fp; 1238 int ret = -ENOMEM; 1239 1240 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1241 if (unlikely(!vmw_fp)) 1242 return ret; 1243 1244 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev); 1245 if (unlikely(vmw_fp->tfile == NULL)) 1246 goto out_no_tfile; 1247 1248 file_priv->driver_priv = vmw_fp; 1249 1250 return 0; 1251 1252 out_no_tfile: 1253 kfree(vmw_fp); 1254 return ret; 1255 } 1256 1257 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1258 unsigned long arg, 1259 long (*ioctl_func)(struct file *, unsigned int, 1260 unsigned long)) 1261 { 1262 struct drm_file *file_priv = filp->private_data; 1263 struct drm_device *dev = file_priv->minor->dev; 1264 unsigned int nr = DRM_IOCTL_NR(cmd); 1265 unsigned int flags; 1266 1267 /* 1268 * Do extra checking on driver private ioctls. 1269 */ 1270 1271 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1272 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1273 const struct drm_ioctl_desc *ioctl = 1274 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1275 1276 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1277 return ioctl_func(filp, cmd, arg); 1278 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1279 if (!drm_is_current_master(file_priv) && 1280 !capable(CAP_SYS_ADMIN)) 1281 return -EACCES; 1282 } 1283 1284 if (unlikely(ioctl->cmd != cmd)) 1285 goto out_io_encoding; 1286 1287 flags = ioctl->flags; 1288 } else if (!drm_ioctl_flags(nr, &flags)) 1289 return -EINVAL; 1290 1291 return ioctl_func(filp, cmd, arg); 1292 1293 out_io_encoding: 1294 DRM_ERROR("Invalid command format, ioctl %d\n", 1295 nr - DRM_COMMAND_BASE); 1296 1297 return -EINVAL; 1298 } 1299 1300 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1301 unsigned long arg) 1302 { 1303 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1304 } 1305 1306 #ifdef CONFIG_COMPAT 1307 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1308 unsigned long arg) 1309 { 1310 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1311 } 1312 #endif 1313 1314 static void vmw_master_set(struct drm_device *dev, 1315 struct drm_file *file_priv, 1316 bool from_open) 1317 { 1318 /* 1319 * Inform a new master that the layout may have changed while 1320 * it was gone. 1321 */ 1322 if (!from_open) 1323 drm_sysfs_hotplug_event(dev); 1324 } 1325 1326 static void vmw_master_drop(struct drm_device *dev, 1327 struct drm_file *file_priv) 1328 { 1329 struct vmw_private *dev_priv = vmw_priv(dev); 1330 1331 vmw_kms_legacy_hotspot_clear(dev_priv); 1332 } 1333 1334 bool vmwgfx_supported(struct vmw_private *vmw) 1335 { 1336 #if defined(CONFIG_X86) 1337 return hypervisor_is_type(X86_HYPER_VMWARE); 1338 #elif defined(CONFIG_ARM64) 1339 /* 1340 * On aarch64 only svga3 is supported 1341 */ 1342 return vmw->pci_id == VMWGFX_PCI_ID_SVGA3; 1343 #else 1344 drm_warn_once(&vmw->drm, 1345 "vmwgfx is running on an unknown architecture."); 1346 return false; 1347 #endif 1348 } 1349 1350 /** 1351 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1352 * 1353 * @dev_priv: Pointer to device private struct. 1354 * Needs the reservation sem to be held in non-exclusive mode. 1355 */ 1356 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1357 { 1358 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1359 1360 if (!ttm_resource_manager_used(man)) { 1361 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1362 ttm_resource_manager_set_used(man, true); 1363 } 1364 } 1365 1366 /** 1367 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1368 * 1369 * @dev_priv: Pointer to device private struct. 1370 */ 1371 void vmw_svga_enable(struct vmw_private *dev_priv) 1372 { 1373 __vmw_svga_enable(dev_priv); 1374 } 1375 1376 /** 1377 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1378 * 1379 * @dev_priv: Pointer to device private struct. 1380 * Needs the reservation sem to be held in exclusive mode. 1381 * Will not empty VRAM. VRAM must be emptied by caller. 1382 */ 1383 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1384 { 1385 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1386 1387 if (ttm_resource_manager_used(man)) { 1388 ttm_resource_manager_set_used(man, false); 1389 vmw_write(dev_priv, SVGA_REG_ENABLE, 1390 SVGA_REG_ENABLE_HIDE | 1391 SVGA_REG_ENABLE_ENABLE); 1392 } 1393 } 1394 1395 /** 1396 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1397 * running. 1398 * 1399 * @dev_priv: Pointer to device private struct. 1400 * Will empty VRAM. 1401 */ 1402 void vmw_svga_disable(struct vmw_private *dev_priv) 1403 { 1404 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1405 /* 1406 * Disabling SVGA will turn off device modesetting capabilities, so 1407 * notify KMS about that so that it doesn't cache atomic state that 1408 * isn't valid anymore, for example crtcs turned on. 1409 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1410 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1411 * end up with lock order reversal. Thus, a master may actually perform 1412 * a new modeset just after we call vmw_kms_lost_device() and race with 1413 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1414 * to be inconsistent with the device, causing modesetting problems. 1415 * 1416 */ 1417 vmw_kms_lost_device(&dev_priv->drm); 1418 if (ttm_resource_manager_used(man)) { 1419 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1420 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1421 ttm_resource_manager_set_used(man, false); 1422 vmw_write(dev_priv, SVGA_REG_ENABLE, 1423 SVGA_REG_ENABLE_HIDE | 1424 SVGA_REG_ENABLE_ENABLE); 1425 } 1426 } 1427 1428 static void vmw_remove(struct pci_dev *pdev) 1429 { 1430 struct drm_device *dev = pci_get_drvdata(pdev); 1431 1432 drm_dev_unregister(dev); 1433 vmw_driver_unload(dev); 1434 } 1435 1436 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) 1437 { 1438 struct drm_minor *minor = vmw->drm.primary; 1439 struct dentry *root = minor->debugfs_root; 1440 1441 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM), 1442 root, "system_ttm"); 1443 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM), 1444 root, "vram_ttm"); 1445 if (vmw->has_gmr) 1446 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1447 root, "gmr_ttm"); 1448 if (vmw->has_mob) { 1449 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1450 root, "mob_ttm"); 1451 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1452 root, "system_mob_ttm"); 1453 } 1454 } 1455 1456 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1457 void *ptr) 1458 { 1459 struct vmw_private *dev_priv = 1460 container_of(nb, struct vmw_private, pm_nb); 1461 1462 switch (val) { 1463 case PM_HIBERNATION_PREPARE: 1464 /* 1465 * Take the reservation sem in write mode, which will make sure 1466 * there are no other processes holding a buffer object 1467 * reservation, meaning we should be able to evict all buffer 1468 * objects if needed. 1469 * Once user-space processes have been frozen, we can release 1470 * the lock again. 1471 */ 1472 dev_priv->suspend_locked = true; 1473 break; 1474 case PM_POST_HIBERNATION: 1475 case PM_POST_RESTORE: 1476 if (READ_ONCE(dev_priv->suspend_locked)) { 1477 dev_priv->suspend_locked = false; 1478 } 1479 break; 1480 default: 1481 break; 1482 } 1483 return 0; 1484 } 1485 1486 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1487 { 1488 struct drm_device *dev = pci_get_drvdata(pdev); 1489 struct vmw_private *dev_priv = vmw_priv(dev); 1490 1491 if (dev_priv->refuse_hibernation) 1492 return -EBUSY; 1493 1494 pci_save_state(pdev); 1495 pci_disable_device(pdev); 1496 pci_set_power_state(pdev, PCI_D3hot); 1497 return 0; 1498 } 1499 1500 static int vmw_pci_resume(struct pci_dev *pdev) 1501 { 1502 pci_set_power_state(pdev, PCI_D0); 1503 pci_restore_state(pdev); 1504 return pci_enable_device(pdev); 1505 } 1506 1507 static int vmw_pm_suspend(struct device *kdev) 1508 { 1509 struct pci_dev *pdev = to_pci_dev(kdev); 1510 struct pm_message dummy; 1511 1512 dummy.event = 0; 1513 1514 return vmw_pci_suspend(pdev, dummy); 1515 } 1516 1517 static int vmw_pm_resume(struct device *kdev) 1518 { 1519 struct pci_dev *pdev = to_pci_dev(kdev); 1520 1521 return vmw_pci_resume(pdev); 1522 } 1523 1524 static int vmw_pm_freeze(struct device *kdev) 1525 { 1526 struct pci_dev *pdev = to_pci_dev(kdev); 1527 struct drm_device *dev = pci_get_drvdata(pdev); 1528 struct vmw_private *dev_priv = vmw_priv(dev); 1529 struct ttm_operation_ctx ctx = { 1530 .interruptible = false, 1531 .no_wait_gpu = false 1532 }; 1533 int ret; 1534 1535 /* 1536 * No user-space processes should be running now. 1537 */ 1538 ret = vmw_kms_suspend(&dev_priv->drm); 1539 if (ret) { 1540 DRM_ERROR("Failed to freeze modesetting.\n"); 1541 return ret; 1542 } 1543 1544 vmw_execbuf_release_pinned_bo(dev_priv); 1545 vmw_resource_evict_all(dev_priv); 1546 vmw_release_device_early(dev_priv); 1547 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1548 vmw_fifo_resource_dec(dev_priv); 1549 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1550 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1551 vmw_fifo_resource_inc(dev_priv); 1552 WARN_ON(vmw_request_device_late(dev_priv)); 1553 dev_priv->suspend_locked = false; 1554 if (dev_priv->suspend_state) 1555 vmw_kms_resume(dev); 1556 return -EBUSY; 1557 } 1558 1559 vmw_fence_fifo_down(dev_priv->fman); 1560 __vmw_svga_disable(dev_priv); 1561 1562 vmw_release_device_late(dev_priv); 1563 return 0; 1564 } 1565 1566 static int vmw_pm_restore(struct device *kdev) 1567 { 1568 struct pci_dev *pdev = to_pci_dev(kdev); 1569 struct drm_device *dev = pci_get_drvdata(pdev); 1570 struct vmw_private *dev_priv = vmw_priv(dev); 1571 int ret; 1572 1573 vmw_detect_version(dev_priv); 1574 1575 vmw_fifo_resource_inc(dev_priv); 1576 1577 ret = vmw_request_device(dev_priv); 1578 if (ret) 1579 return ret; 1580 1581 __vmw_svga_enable(dev_priv); 1582 1583 vmw_fence_fifo_up(dev_priv->fman); 1584 dev_priv->suspend_locked = false; 1585 if (dev_priv->suspend_state) 1586 vmw_kms_resume(&dev_priv->drm); 1587 1588 return 0; 1589 } 1590 1591 static const struct dev_pm_ops vmw_pm_ops = { 1592 .freeze = vmw_pm_freeze, 1593 .thaw = vmw_pm_restore, 1594 .restore = vmw_pm_restore, 1595 .suspend = vmw_pm_suspend, 1596 .resume = vmw_pm_resume, 1597 }; 1598 1599 static const struct file_operations vmwgfx_driver_fops = { 1600 .owner = THIS_MODULE, 1601 .open = drm_open, 1602 .release = drm_release, 1603 .unlocked_ioctl = vmw_unlocked_ioctl, 1604 .mmap = drm_gem_mmap, 1605 .poll = drm_poll, 1606 .read = drm_read, 1607 #if defined(CONFIG_COMPAT) 1608 .compat_ioctl = vmw_compat_ioctl, 1609 #endif 1610 .llseek = noop_llseek, 1611 .fop_flags = FOP_UNSIGNED_OFFSET, 1612 }; 1613 1614 static const struct drm_driver driver = { 1615 .driver_features = 1616 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT, 1617 .ioctls = vmw_ioctls, 1618 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1619 .master_set = vmw_master_set, 1620 .master_drop = vmw_master_drop, 1621 .open = vmw_driver_open, 1622 .postclose = vmw_postclose, 1623 1624 .dumb_create = vmw_dumb_create, 1625 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1626 1627 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1628 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1629 .gem_prime_import_sg_table = vmw_prime_import_sg_table, 1630 1631 DRM_FBDEV_TTM_DRIVER_OPS, 1632 1633 .fops = &vmwgfx_driver_fops, 1634 .name = VMWGFX_DRIVER_NAME, 1635 .desc = VMWGFX_DRIVER_DESC, 1636 .date = VMWGFX_DRIVER_DATE, 1637 .major = VMWGFX_DRIVER_MAJOR, 1638 .minor = VMWGFX_DRIVER_MINOR, 1639 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1640 }; 1641 1642 static struct pci_driver vmw_pci_driver = { 1643 .name = VMWGFX_DRIVER_NAME, 1644 .id_table = vmw_pci_id_list, 1645 .probe = vmw_probe, 1646 .remove = vmw_remove, 1647 .driver = { 1648 .pm = &vmw_pm_ops 1649 } 1650 }; 1651 1652 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1653 { 1654 struct vmw_private *vmw; 1655 int ret; 1656 1657 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver); 1658 if (ret) 1659 goto out_error; 1660 1661 ret = pcim_enable_device(pdev); 1662 if (ret) 1663 goto out_error; 1664 1665 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1666 struct vmw_private, drm); 1667 if (IS_ERR(vmw)) { 1668 ret = PTR_ERR(vmw); 1669 goto out_error; 1670 } 1671 1672 pci_set_drvdata(pdev, &vmw->drm); 1673 1674 ret = vmw_driver_load(vmw, ent->device); 1675 if (ret) 1676 goto out_error; 1677 1678 ret = drm_dev_register(&vmw->drm, 0); 1679 if (ret) 1680 goto out_unload; 1681 1682 vmw_fifo_resource_inc(vmw); 1683 vmw_svga_enable(vmw); 1684 drm_client_setup(&vmw->drm, NULL); 1685 1686 vmw_debugfs_gem_init(vmw); 1687 vmw_debugfs_resource_managers_init(vmw); 1688 1689 return 0; 1690 out_unload: 1691 vmw_driver_unload(&vmw->drm); 1692 out_error: 1693 return ret; 1694 } 1695 1696 drm_module_pci_driver(vmw_pci_driver); 1697 1698 MODULE_AUTHOR("VMware Inc. and others"); 1699 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1700 MODULE_LICENSE("GPL and additional rights"); 1701 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1702 __stringify(VMWGFX_DRIVER_MINOR) "." 1703 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1704 "0"); 1705