1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 #include "vmwgfx_drv.h" 30 31 #include "vmwgfx_bo.h" 32 #include "vmwgfx_binding.h" 33 #include "vmwgfx_devcaps.h" 34 #include "vmwgfx_mksstat.h" 35 #include "vmwgfx_vkms.h" 36 #include "ttm_object.h" 37 38 #include <drm/drm_aperture.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_fbdev_generic.h> 41 #include <drm/drm_gem_ttm_helper.h> 42 #include <drm/drm_ioctl.h> 43 #include <drm/drm_module.h> 44 #include <drm/drm_sysfs.h> 45 #include <drm/ttm/ttm_range_manager.h> 46 #include <drm/ttm/ttm_placement.h> 47 #include <generated/utsrelease.h> 48 49 #ifdef CONFIG_X86 50 #include <asm/hypervisor.h> 51 #endif 52 #include <linux/cc_platform.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/module.h> 55 #include <linux/pci.h> 56 #include <linux/version.h> 57 #include <linux/vmalloc.h> 58 59 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 60 61 /* 62 * Fully encoded drm commands. Might move to vmw_drm.h 63 */ 64 65 #define DRM_IOCTL_VMW_GET_PARAM \ 66 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 67 struct drm_vmw_getparam_arg) 68 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 69 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 70 union drm_vmw_alloc_dmabuf_arg) 71 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 73 struct drm_vmw_unref_dmabuf_arg) 74 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 75 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 76 struct drm_vmw_cursor_bypass_arg) 77 78 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 80 struct drm_vmw_control_stream_arg) 81 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 82 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 83 struct drm_vmw_stream_arg) 84 #define DRM_IOCTL_VMW_UNREF_STREAM \ 85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 86 struct drm_vmw_stream_arg) 87 88 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 89 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 90 struct drm_vmw_context_arg) 91 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 93 struct drm_vmw_context_arg) 94 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 96 union drm_vmw_surface_create_arg) 97 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 99 struct drm_vmw_surface_arg) 100 #define DRM_IOCTL_VMW_REF_SURFACE \ 101 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 102 union drm_vmw_surface_reference_arg) 103 #define DRM_IOCTL_VMW_EXECBUF \ 104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 105 struct drm_vmw_execbuf_arg) 106 #define DRM_IOCTL_VMW_GET_3D_CAP \ 107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 108 struct drm_vmw_get_3d_cap_arg) 109 #define DRM_IOCTL_VMW_FENCE_WAIT \ 110 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 111 struct drm_vmw_fence_wait_arg) 112 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 113 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 114 struct drm_vmw_fence_signaled_arg) 115 #define DRM_IOCTL_VMW_FENCE_UNREF \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 117 struct drm_vmw_fence_arg) 118 #define DRM_IOCTL_VMW_FENCE_EVENT \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 120 struct drm_vmw_fence_event_arg) 121 #define DRM_IOCTL_VMW_PRESENT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 123 struct drm_vmw_present_arg) 124 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 125 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 126 struct drm_vmw_present_readback_arg) 127 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 129 struct drm_vmw_update_layout_arg) 130 #define DRM_IOCTL_VMW_CREATE_SHADER \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 132 struct drm_vmw_shader_create_arg) 133 #define DRM_IOCTL_VMW_UNREF_SHADER \ 134 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 135 struct drm_vmw_shader_arg) 136 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 137 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 138 union drm_vmw_gb_surface_create_arg) 139 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 141 union drm_vmw_gb_surface_reference_arg) 142 #define DRM_IOCTL_VMW_SYNCCPU \ 143 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 144 struct drm_vmw_synccpu_arg) 145 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 147 struct drm_vmw_context_arg) 148 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 149 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 150 union drm_vmw_gb_surface_create_ext_arg) 151 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 152 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 153 union drm_vmw_gb_surface_reference_ext_arg) 154 #define DRM_IOCTL_VMW_MSG \ 155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 156 struct drm_vmw_msg_arg) 157 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 158 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 159 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 160 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 161 struct drm_vmw_mksstat_add_arg) 162 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 163 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 164 struct drm_vmw_mksstat_remove_arg) 165 166 /* 167 * Ioctl definitions. 168 */ 169 170 static const struct drm_ioctl_desc vmw_ioctls[] = { 171 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 172 DRM_RENDER_ALLOW), 173 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 174 DRM_RENDER_ALLOW), 175 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 176 DRM_RENDER_ALLOW), 177 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 178 vmw_kms_cursor_bypass_ioctl, 179 DRM_MASTER), 180 181 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 182 DRM_MASTER), 183 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 184 DRM_MASTER), 185 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 186 DRM_MASTER), 187 188 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 189 DRM_RENDER_ALLOW), 190 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 191 DRM_RENDER_ALLOW), 192 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 193 DRM_RENDER_ALLOW), 194 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 195 DRM_RENDER_ALLOW), 196 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 197 DRM_RENDER_ALLOW), 198 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 199 DRM_RENDER_ALLOW), 200 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 201 DRM_RENDER_ALLOW), 202 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 203 vmw_fence_obj_signaled_ioctl, 204 DRM_RENDER_ALLOW), 205 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 206 DRM_RENDER_ALLOW), 207 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 208 DRM_RENDER_ALLOW), 209 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 210 DRM_RENDER_ALLOW), 211 212 /* these allow direct access to the framebuffers mark as master only */ 213 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 214 DRM_MASTER | DRM_AUTH), 215 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 216 vmw_present_readback_ioctl, 217 DRM_MASTER | DRM_AUTH), 218 /* 219 * The permissions of the below ioctl are overridden in 220 * vmw_generic_ioctl(). We require either 221 * DRM_MASTER or capable(CAP_SYS_ADMIN). 222 */ 223 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 224 vmw_kms_update_layout_ioctl, 225 DRM_RENDER_ALLOW), 226 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 227 vmw_shader_define_ioctl, 228 DRM_RENDER_ALLOW), 229 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 230 vmw_shader_destroy_ioctl, 231 DRM_RENDER_ALLOW), 232 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 233 vmw_gb_surface_define_ioctl, 234 DRM_RENDER_ALLOW), 235 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 236 vmw_gb_surface_reference_ioctl, 237 DRM_RENDER_ALLOW), 238 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 239 vmw_user_bo_synccpu_ioctl, 240 DRM_RENDER_ALLOW), 241 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 242 vmw_extended_context_define_ioctl, 243 DRM_RENDER_ALLOW), 244 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 245 vmw_gb_surface_define_ext_ioctl, 246 DRM_RENDER_ALLOW), 247 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 248 vmw_gb_surface_reference_ext_ioctl, 249 DRM_RENDER_ALLOW), 250 DRM_IOCTL_DEF_DRV(VMW_MSG, 251 vmw_msg_ioctl, 252 DRM_RENDER_ALLOW), 253 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 254 vmw_mksstat_reset_ioctl, 255 DRM_RENDER_ALLOW), 256 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 257 vmw_mksstat_add_ioctl, 258 DRM_RENDER_ALLOW), 259 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 260 vmw_mksstat_remove_ioctl, 261 DRM_RENDER_ALLOW), 262 }; 263 264 static const struct pci_device_id vmw_pci_id_list[] = { 265 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 266 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 267 { } 268 }; 269 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 270 271 static int vmw_restrict_iommu; 272 static int vmw_force_coherent; 273 static int vmw_restrict_dma_mask; 274 static int vmw_assume_16bpp; 275 276 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 277 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 278 void *ptr); 279 280 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 281 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 282 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 283 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 284 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 285 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 286 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 287 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 288 289 290 struct bitmap_name { 291 uint32 value; 292 const char *name; 293 }; 294 295 static const struct bitmap_name cap1_names[] = { 296 { SVGA_CAP_RECT_COPY, "rect copy" }, 297 { SVGA_CAP_CURSOR, "cursor" }, 298 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 299 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 300 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 301 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 302 { SVGA_CAP_3D, "3D" }, 303 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 304 { SVGA_CAP_MULTIMON, "multimon" }, 305 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 306 { SVGA_CAP_IRQMASK, "irq mask" }, 307 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 308 { SVGA_CAP_GMR, "gmr" }, 309 { SVGA_CAP_TRACES, "traces" }, 310 { SVGA_CAP_GMR2, "gmr2" }, 311 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 312 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 313 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 314 { SVGA_CAP_GBOBJECTS, "gbobject" }, 315 { SVGA_CAP_DX, "dx" }, 316 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 317 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 318 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 319 }; 320 321 322 static const struct bitmap_name cap2_names[] = { 323 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 324 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 325 { SVGA_CAP2_DX2, "dx2" }, 326 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 327 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 328 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 329 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 330 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 331 { SVGA_CAP2_MSHINT, "mshint" }, 332 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 333 { SVGA_CAP2_DX3, "dx3" }, 334 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 335 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 336 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 337 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 338 { SVGA_CAP2_LO_STAGING, "lo staging" }, 339 }; 340 341 static void vmw_print_bitmap(struct drm_device *drm, 342 const char *prefix, uint32_t bitmap, 343 const struct bitmap_name *bnames, 344 uint32_t num_names) 345 { 346 char buf[512]; 347 uint32_t i; 348 uint32_t offset = 0; 349 for (i = 0; i < num_names; ++i) { 350 if ((bitmap & bnames[i].value) != 0) { 351 offset += snprintf(buf + offset, 352 ARRAY_SIZE(buf) - offset, 353 "%s, ", bnames[i].name); 354 bitmap &= ~bnames[i].value; 355 } 356 } 357 358 drm_info(drm, "%s: %s\n", prefix, buf); 359 if (bitmap != 0) 360 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 361 } 362 363 364 static void vmw_print_sm_type(struct vmw_private *dev_priv) 365 { 366 static const char *names[] = { 367 [VMW_SM_LEGACY] = "Legacy", 368 [VMW_SM_4] = "SM4", 369 [VMW_SM_4_1] = "SM4_1", 370 [VMW_SM_5] = "SM_5", 371 [VMW_SM_5_1X] = "SM_5_1X", 372 [VMW_SM_MAX] = "Invalid" 373 }; 374 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 375 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 376 names[dev_priv->sm_type]); 377 } 378 379 /** 380 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 381 * 382 * @dev_priv: A device private structure. 383 * 384 * This function creates a small buffer object that holds the query 385 * result for dummy queries emitted as query barriers. 386 * The function will then map the first page and initialize a pending 387 * occlusion query result structure, Finally it will unmap the buffer. 388 * No interruptible waits are done within this function. 389 * 390 * Returns an error if bo creation or initialization fails. 391 */ 392 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 393 { 394 int ret; 395 struct vmw_bo *vbo; 396 struct ttm_bo_kmap_obj map; 397 volatile SVGA3dQueryResult *result; 398 bool dummy; 399 struct vmw_bo_params bo_params = { 400 .domain = VMW_BO_DOMAIN_SYS, 401 .busy_domain = VMW_BO_DOMAIN_SYS, 402 .bo_type = ttm_bo_type_kernel, 403 .size = PAGE_SIZE, 404 .pin = true 405 }; 406 407 /* 408 * Create the vbo as pinned, so that a tryreserve will 409 * immediately succeed. This is because we're the only 410 * user of the bo currently. 411 */ 412 ret = vmw_bo_create(dev_priv, &bo_params, &vbo); 413 if (unlikely(ret != 0)) 414 return ret; 415 416 ret = ttm_bo_reserve(&vbo->tbo, false, true, NULL); 417 BUG_ON(ret != 0); 418 vmw_bo_pin_reserved(vbo, true); 419 420 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map); 421 if (likely(ret == 0)) { 422 result = ttm_kmap_obj_virtual(&map, &dummy); 423 result->totalSize = sizeof(*result); 424 result->state = SVGA3D_QUERYSTATE_PENDING; 425 result->result32 = 0xff; 426 ttm_bo_kunmap(&map); 427 } 428 vmw_bo_pin_reserved(vbo, false); 429 ttm_bo_unreserve(&vbo->tbo); 430 431 if (unlikely(ret != 0)) { 432 DRM_ERROR("Dummy query buffer map failed.\n"); 433 vmw_bo_unreference(&vbo); 434 } else 435 dev_priv->dummy_query_bo = vbo; 436 437 return ret; 438 } 439 440 static int vmw_device_init(struct vmw_private *dev_priv) 441 { 442 bool uses_fb_traces = false; 443 444 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 445 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 446 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 447 448 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 449 SVGA_REG_ENABLE_HIDE); 450 451 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 452 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 453 454 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 455 dev_priv->fifo = vmw_fifo_create(dev_priv); 456 if (IS_ERR(dev_priv->fifo)) { 457 int err = PTR_ERR(dev_priv->fifo); 458 dev_priv->fifo = NULL; 459 return err; 460 } else if (!dev_priv->fifo) { 461 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 462 } 463 464 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 465 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 466 return 0; 467 } 468 469 static void vmw_device_fini(struct vmw_private *vmw) 470 { 471 /* 472 * Legacy sync 473 */ 474 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 475 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 476 ; 477 478 vmw->last_read_seqno = vmw_fence_read(vmw); 479 480 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 481 vmw->config_done_state); 482 vmw_write(vmw, SVGA_REG_ENABLE, 483 vmw->enable_state); 484 vmw_write(vmw, SVGA_REG_TRACES, 485 vmw->traces_state); 486 487 vmw_fifo_destroy(vmw); 488 } 489 490 /** 491 * vmw_request_device_late - Perform late device setup 492 * 493 * @dev_priv: Pointer to device private. 494 * 495 * This function performs setup of otables and enables large command 496 * buffer submission. These tasks are split out to a separate function 497 * because it reverts vmw_release_device_early and is intended to be used 498 * by an error path in the hibernation code. 499 */ 500 static int vmw_request_device_late(struct vmw_private *dev_priv) 501 { 502 int ret; 503 504 if (dev_priv->has_mob) { 505 ret = vmw_otables_setup(dev_priv); 506 if (unlikely(ret != 0)) { 507 DRM_ERROR("Unable to initialize " 508 "guest Memory OBjects.\n"); 509 return ret; 510 } 511 } 512 513 if (dev_priv->cman) { 514 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 515 if (ret) { 516 struct vmw_cmdbuf_man *man = dev_priv->cman; 517 518 dev_priv->cman = NULL; 519 vmw_cmdbuf_man_destroy(man); 520 } 521 } 522 523 return 0; 524 } 525 526 static int vmw_request_device(struct vmw_private *dev_priv) 527 { 528 int ret; 529 530 ret = vmw_device_init(dev_priv); 531 if (unlikely(ret != 0)) { 532 DRM_ERROR("Unable to initialize the device.\n"); 533 return ret; 534 } 535 vmw_fence_fifo_up(dev_priv->fman); 536 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 537 if (IS_ERR(dev_priv->cman)) { 538 dev_priv->cman = NULL; 539 dev_priv->sm_type = VMW_SM_LEGACY; 540 } 541 542 ret = vmw_request_device_late(dev_priv); 543 if (ret) 544 goto out_no_mob; 545 546 ret = vmw_dummy_query_bo_create(dev_priv); 547 if (unlikely(ret != 0)) 548 goto out_no_query_bo; 549 550 return 0; 551 552 out_no_query_bo: 553 if (dev_priv->cman) 554 vmw_cmdbuf_remove_pool(dev_priv->cman); 555 if (dev_priv->has_mob) { 556 struct ttm_resource_manager *man; 557 558 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 559 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 560 vmw_otables_takedown(dev_priv); 561 } 562 if (dev_priv->cman) 563 vmw_cmdbuf_man_destroy(dev_priv->cman); 564 out_no_mob: 565 vmw_fence_fifo_down(dev_priv->fman); 566 vmw_device_fini(dev_priv); 567 return ret; 568 } 569 570 /** 571 * vmw_release_device_early - Early part of fifo takedown. 572 * 573 * @dev_priv: Pointer to device private struct. 574 * 575 * This is the first part of command submission takedown, to be called before 576 * buffer management is taken down. 577 */ 578 static void vmw_release_device_early(struct vmw_private *dev_priv) 579 { 580 /* 581 * Previous destructions should've released 582 * the pinned bo. 583 */ 584 585 BUG_ON(dev_priv->pinned_bo != NULL); 586 587 vmw_bo_unreference(&dev_priv->dummy_query_bo); 588 if (dev_priv->cman) 589 vmw_cmdbuf_remove_pool(dev_priv->cman); 590 591 if (dev_priv->has_mob) { 592 struct ttm_resource_manager *man; 593 594 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 595 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 596 vmw_otables_takedown(dev_priv); 597 } 598 } 599 600 /** 601 * vmw_release_device_late - Late part of fifo takedown. 602 * 603 * @dev_priv: Pointer to device private struct. 604 * 605 * This is the last part of the command submission takedown, to be called when 606 * command submission is no longer needed. It may wait on pending fences. 607 */ 608 static void vmw_release_device_late(struct vmw_private *dev_priv) 609 { 610 vmw_fence_fifo_down(dev_priv->fman); 611 if (dev_priv->cman) 612 vmw_cmdbuf_man_destroy(dev_priv->cman); 613 614 vmw_device_fini(dev_priv); 615 } 616 617 /* 618 * Sets the initial_[width|height] fields on the given vmw_private. 619 * 620 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 621 * clamping the value to fb_max_[width|height] fields and the 622 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 623 * If the values appear to be invalid, set them to 624 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 625 */ 626 static void vmw_get_initial_size(struct vmw_private *dev_priv) 627 { 628 uint32_t width; 629 uint32_t height; 630 631 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 632 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 633 634 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH); 635 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT); 636 637 if (width > dev_priv->fb_max_width || 638 height > dev_priv->fb_max_height) { 639 640 /* 641 * This is a host error and shouldn't occur. 642 */ 643 644 width = VMWGFX_MIN_INITIAL_WIDTH; 645 height = VMWGFX_MIN_INITIAL_HEIGHT; 646 } 647 648 dev_priv->initial_width = width; 649 dev_priv->initial_height = height; 650 } 651 652 /** 653 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 654 * system. 655 * 656 * @dev_priv: Pointer to a struct vmw_private 657 * 658 * This functions tries to determine what actions need to be taken by the 659 * driver to make system pages visible to the device. 660 * If this function decides that DMA is not possible, it returns -EINVAL. 661 * The driver may then try to disable features of the device that require 662 * DMA. 663 */ 664 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 665 { 666 static const char *names[vmw_dma_map_max] = { 667 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 668 [vmw_dma_map_populate] = "Caching DMA mappings.", 669 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 670 671 /* 672 * When running with SEV we always want dma mappings, because 673 * otherwise ttm tt pool pages will bounce through swiotlb running 674 * out of available space. 675 */ 676 if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 677 dev_priv->map_mode = vmw_dma_alloc_coherent; 678 else if (vmw_restrict_iommu) 679 dev_priv->map_mode = vmw_dma_map_bind; 680 else 681 dev_priv->map_mode = vmw_dma_map_populate; 682 683 drm_info(&dev_priv->drm, 684 "DMA map mode: %s\n", names[dev_priv->map_mode]); 685 return 0; 686 } 687 688 /** 689 * vmw_dma_masks - set required page- and dma masks 690 * 691 * @dev_priv: Pointer to struct drm-device 692 * 693 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 694 * restriction also for 64-bit systems. 695 */ 696 static int vmw_dma_masks(struct vmw_private *dev_priv) 697 { 698 struct drm_device *dev = &dev_priv->drm; 699 int ret = 0; 700 701 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 702 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 703 drm_info(&dev_priv->drm, 704 "Restricting DMA addresses to 44 bits.\n"); 705 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 706 } 707 708 return ret; 709 } 710 711 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 712 { 713 int ret; 714 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 715 dev_priv->vram_size >> PAGE_SHIFT); 716 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 717 return ret; 718 } 719 720 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 721 { 722 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 723 } 724 725 static int vmw_setup_pci_resources(struct vmw_private *dev, 726 u32 pci_id) 727 { 728 resource_size_t rmmio_start; 729 resource_size_t rmmio_size; 730 resource_size_t fifo_start; 731 resource_size_t fifo_size; 732 int ret; 733 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 734 735 pci_set_master(pdev); 736 737 ret = pci_request_regions(pdev, "vmwgfx probe"); 738 if (ret) 739 return ret; 740 741 dev->pci_id = pci_id; 742 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 743 rmmio_start = pci_resource_start(pdev, 0); 744 rmmio_size = pci_resource_len(pdev, 0); 745 dev->vram_start = pci_resource_start(pdev, 2); 746 dev->vram_size = pci_resource_len(pdev, 2); 747 748 drm_info(&dev->drm, 749 "Register MMIO at 0x%pa size is %llu kiB\n", 750 &rmmio_start, (uint64_t)rmmio_size / 1024); 751 dev->rmmio = devm_ioremap(dev->drm.dev, 752 rmmio_start, 753 rmmio_size); 754 if (!dev->rmmio) { 755 drm_err(&dev->drm, 756 "Failed mapping registers mmio memory.\n"); 757 pci_release_regions(pdev); 758 return -ENOMEM; 759 } 760 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 761 dev->io_start = pci_resource_start(pdev, 0); 762 dev->vram_start = pci_resource_start(pdev, 1); 763 dev->vram_size = pci_resource_len(pdev, 1); 764 fifo_start = pci_resource_start(pdev, 2); 765 fifo_size = pci_resource_len(pdev, 2); 766 767 drm_info(&dev->drm, 768 "FIFO at %pa size is %llu kiB\n", 769 &fifo_start, (uint64_t)fifo_size / 1024); 770 dev->fifo_mem = devm_memremap(dev->drm.dev, 771 fifo_start, 772 fifo_size, 773 MEMREMAP_WB); 774 775 if (IS_ERR(dev->fifo_mem)) { 776 drm_err(&dev->drm, 777 "Failed mapping FIFO memory.\n"); 778 pci_release_regions(pdev); 779 return PTR_ERR(dev->fifo_mem); 780 } 781 } else { 782 pci_release_regions(pdev); 783 return -EINVAL; 784 } 785 786 /* 787 * This is approximate size of the vram, the exact size will only 788 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 789 * size will be equal to or bigger than the size reported by 790 * SVGA_REG_VRAM_SIZE. 791 */ 792 drm_info(&dev->drm, 793 "VRAM at %pa size is %llu kiB\n", 794 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 795 796 return 0; 797 } 798 799 static int vmw_detect_version(struct vmw_private *dev) 800 { 801 uint32_t svga_id; 802 803 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 804 SVGA_ID_3 : SVGA_ID_2); 805 svga_id = vmw_read(dev, SVGA_REG_ID); 806 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 807 drm_err(&dev->drm, 808 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 809 svga_id, dev->pci_id); 810 return -ENOSYS; 811 } 812 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 813 drm_info(&dev->drm, 814 "Running on SVGA version %d.\n", (svga_id & 0xff)); 815 return 0; 816 } 817 818 static void vmw_write_driver_id(struct vmw_private *dev) 819 { 820 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) { 821 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 822 SVGA_REG_GUEST_DRIVER_ID_LINUX); 823 824 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1, 825 LINUX_VERSION_MAJOR << 24 | 826 LINUX_VERSION_PATCHLEVEL << 16 | 827 LINUX_VERSION_SUBLEVEL); 828 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2, 829 VMWGFX_DRIVER_MAJOR << 24 | 830 VMWGFX_DRIVER_MINOR << 16 | 831 VMWGFX_DRIVER_PATCHLEVEL); 832 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0); 833 834 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 835 SVGA_REG_GUEST_DRIVER_ID_SUBMIT); 836 } 837 } 838 839 static void vmw_sw_context_init(struct vmw_private *dev_priv) 840 { 841 struct vmw_sw_context *sw_context = &dev_priv->ctx; 842 843 hash_init(sw_context->res_ht); 844 } 845 846 static void vmw_sw_context_fini(struct vmw_private *dev_priv) 847 { 848 struct vmw_sw_context *sw_context = &dev_priv->ctx; 849 850 vfree(sw_context->cmd_bounce); 851 if (sw_context->staged_bindings) 852 vmw_binding_state_free(sw_context->staged_bindings); 853 } 854 855 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 856 { 857 int ret; 858 enum vmw_res_type i; 859 bool refuse_dma = false; 860 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 861 862 dev_priv->drm.dev_private = dev_priv; 863 864 vmw_sw_context_init(dev_priv); 865 866 mutex_init(&dev_priv->cmdbuf_mutex); 867 mutex_init(&dev_priv->binding_mutex); 868 spin_lock_init(&dev_priv->resource_lock); 869 spin_lock_init(&dev_priv->hw_lock); 870 spin_lock_init(&dev_priv->waiter_lock); 871 spin_lock_init(&dev_priv->cursor_lock); 872 873 ret = vmw_setup_pci_resources(dev_priv, pci_id); 874 if (ret) 875 return ret; 876 ret = vmw_detect_version(dev_priv); 877 if (ret) 878 goto out_no_pci_or_version; 879 880 881 for (i = vmw_res_context; i < vmw_res_max; ++i) { 882 idr_init_base(&dev_priv->res_idr[i], 1); 883 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 884 } 885 886 init_waitqueue_head(&dev_priv->fence_queue); 887 init_waitqueue_head(&dev_priv->fifo_queue); 888 dev_priv->fence_queue_waiters = 0; 889 dev_priv->fifo_queue_waiters = 0; 890 891 dev_priv->used_memory_size = 0; 892 893 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 894 895 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 896 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 897 dev_priv->capabilities, 898 cap1_names, ARRAY_SIZE(cap1_names)); 899 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 900 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 901 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 902 dev_priv->capabilities2, 903 cap2_names, ARRAY_SIZE(cap2_names)); 904 } 905 906 if (!vmwgfx_supported(dev_priv)) { 907 vmw_disable_backdoor(); 908 drm_err_once(&dev_priv->drm, 909 "vmwgfx seems to be running on an unsupported hypervisor."); 910 drm_err_once(&dev_priv->drm, 911 "This configuration is likely broken."); 912 drm_err_once(&dev_priv->drm, 913 "Please switch to a supported graphics device to avoid problems."); 914 } 915 916 vmw_vkms_init(dev_priv); 917 918 ret = vmw_dma_select_mode(dev_priv); 919 if (unlikely(ret != 0)) { 920 drm_info(&dev_priv->drm, 921 "Restricting capabilities since DMA not available.\n"); 922 refuse_dma = true; 923 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 924 drm_info(&dev_priv->drm, 925 "Disabling 3D acceleration.\n"); 926 } 927 928 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 929 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 930 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 931 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 932 933 vmw_get_initial_size(dev_priv); 934 935 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 936 dev_priv->max_gmr_ids = 937 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 938 dev_priv->max_gmr_pages = 939 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 940 dev_priv->memory_size = 941 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 942 dev_priv->memory_size -= dev_priv->vram_size; 943 } else { 944 /* 945 * An arbitrary limit of 512MiB on surface 946 * memory. But all HWV8 hardware supports GMR2. 947 */ 948 dev_priv->memory_size = 512*1024*1024; 949 } 950 dev_priv->max_mob_pages = 0; 951 dev_priv->max_mob_size = 0; 952 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 953 uint64_t mem_size; 954 955 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 956 mem_size = vmw_read(dev_priv, 957 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 958 else 959 mem_size = 960 vmw_read(dev_priv, 961 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 962 963 /* 964 * Workaround for low memory 2D VMs to compensate for the 965 * allocation taken by fbdev 966 */ 967 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 968 mem_size *= 3; 969 970 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 971 dev_priv->max_primary_mem = 972 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 973 dev_priv->max_mob_size = 974 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 975 dev_priv->stdu_max_width = 976 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 977 dev_priv->stdu_max_height = 978 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 979 980 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 981 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 982 dev_priv->texture_max_width = vmw_read(dev_priv, 983 SVGA_REG_DEV_CAP); 984 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 985 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 986 dev_priv->texture_max_height = vmw_read(dev_priv, 987 SVGA_REG_DEV_CAP); 988 } else { 989 dev_priv->texture_max_width = 8192; 990 dev_priv->texture_max_height = 8192; 991 dev_priv->max_primary_mem = dev_priv->vram_size; 992 } 993 drm_info(&dev_priv->drm, 994 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n", 995 (u64)dev_priv->vram_size / 1024, 996 (u64)dev_priv->fifo_mem_size / 1024, 997 dev_priv->memory_size / 1024); 998 999 drm_info(&dev_priv->drm, 1000 "MOB limits: max mob size = %u kB, max mob pages = %u\n", 1001 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 1002 1003 ret = vmw_dma_masks(dev_priv); 1004 if (unlikely(ret != 0)) 1005 goto out_err0; 1006 1007 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 1008 1009 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 1010 drm_info(&dev_priv->drm, 1011 "Max GMR ids is %u\n", 1012 (unsigned)dev_priv->max_gmr_ids); 1013 drm_info(&dev_priv->drm, 1014 "Max number of GMR pages is %u\n", 1015 (unsigned)dev_priv->max_gmr_pages); 1016 } 1017 drm_info(&dev_priv->drm, 1018 "Maximum display memory size is %llu kiB\n", 1019 (uint64_t)dev_priv->max_primary_mem / 1024); 1020 1021 /* Need mmio memory to check for fifo pitchlock cap. */ 1022 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 1023 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 1024 !vmw_fifo_have_pitchlock(dev_priv)) { 1025 ret = -ENOSYS; 1026 DRM_ERROR("Hardware has no pitchlock\n"); 1027 goto out_err0; 1028 } 1029 1030 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops); 1031 1032 if (unlikely(dev_priv->tdev == NULL)) { 1033 drm_err(&dev_priv->drm, 1034 "Unable to initialize TTM object management.\n"); 1035 ret = -ENOMEM; 1036 goto out_err0; 1037 } 1038 1039 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 1040 ret = vmw_irq_install(dev_priv); 1041 if (ret != 0) { 1042 drm_err(&dev_priv->drm, 1043 "Failed installing irq: %d\n", ret); 1044 goto out_no_irq; 1045 } 1046 } 1047 1048 dev_priv->fman = vmw_fence_manager_init(dev_priv); 1049 if (unlikely(dev_priv->fman == NULL)) { 1050 ret = -ENOMEM; 1051 goto out_no_fman; 1052 } 1053 1054 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1055 dev_priv->drm.dev, 1056 dev_priv->drm.anon_inode->i_mapping, 1057 dev_priv->drm.vma_offset_manager, 1058 dev_priv->map_mode == vmw_dma_alloc_coherent, 1059 false); 1060 if (unlikely(ret != 0)) { 1061 drm_err(&dev_priv->drm, 1062 "Failed initializing TTM buffer object driver.\n"); 1063 goto out_no_bdev; 1064 } 1065 1066 /* 1067 * Enable VRAM, but initially don't use it until SVGA is enabled and 1068 * unhidden. 1069 */ 1070 1071 ret = vmw_vram_manager_init(dev_priv); 1072 if (unlikely(ret != 0)) { 1073 drm_err(&dev_priv->drm, 1074 "Failed initializing memory manager for VRAM.\n"); 1075 goto out_no_vram; 1076 } 1077 1078 ret = vmw_devcaps_create(dev_priv); 1079 if (unlikely(ret != 0)) { 1080 drm_err(&dev_priv->drm, 1081 "Failed initializing device caps.\n"); 1082 goto out_no_vram; 1083 } 1084 1085 /* 1086 * "Guest Memory Regions" is an aperture like feature with 1087 * one slot per bo. There is an upper limit of the number of 1088 * slots as well as the bo size. 1089 */ 1090 dev_priv->has_gmr = true; 1091 /* TODO: This is most likely not correct */ 1092 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1093 refuse_dma || 1094 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1095 drm_info(&dev_priv->drm, 1096 "No GMR memory available. " 1097 "Graphics memory resources are very limited.\n"); 1098 dev_priv->has_gmr = false; 1099 } 1100 1101 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1102 dev_priv->has_mob = true; 1103 1104 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1105 drm_info(&dev_priv->drm, 1106 "No MOB memory available. " 1107 "3D will be disabled.\n"); 1108 dev_priv->has_mob = false; 1109 } 1110 if (vmw_sys_man_init(dev_priv) != 0) { 1111 drm_info(&dev_priv->drm, 1112 "No MOB page table memory available. " 1113 "3D will be disabled.\n"); 1114 dev_priv->has_mob = false; 1115 } 1116 } 1117 1118 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1119 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1120 dev_priv->sm_type = VMW_SM_4; 1121 } 1122 1123 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1124 if (has_sm4_context(dev_priv) && 1125 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1126 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1127 dev_priv->sm_type = VMW_SM_4_1; 1128 if (has_sm4_1_context(dev_priv) && 1129 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1130 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1131 dev_priv->sm_type = VMW_SM_5; 1132 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1133 dev_priv->sm_type = VMW_SM_5_1X; 1134 } 1135 } 1136 } 1137 1138 ret = vmw_kms_init(dev_priv); 1139 if (unlikely(ret != 0)) 1140 goto out_no_kms; 1141 vmw_overlay_init(dev_priv); 1142 1143 ret = vmw_request_device(dev_priv); 1144 if (ret) 1145 goto out_no_fifo; 1146 1147 vmw_print_sm_type(dev_priv); 1148 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1149 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1150 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1151 vmw_write_driver_id(dev_priv); 1152 1153 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1154 register_pm_notifier(&dev_priv->pm_nb); 1155 1156 return 0; 1157 1158 out_no_fifo: 1159 vmw_overlay_close(dev_priv); 1160 vmw_kms_close(dev_priv); 1161 out_no_kms: 1162 if (dev_priv->has_mob) { 1163 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1164 vmw_sys_man_fini(dev_priv); 1165 } 1166 if (dev_priv->has_gmr) 1167 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1168 vmw_devcaps_destroy(dev_priv); 1169 vmw_vram_manager_fini(dev_priv); 1170 out_no_vram: 1171 ttm_device_fini(&dev_priv->bdev); 1172 out_no_bdev: 1173 vmw_fence_manager_takedown(dev_priv->fman); 1174 out_no_fman: 1175 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1176 vmw_irq_uninstall(&dev_priv->drm); 1177 out_no_irq: 1178 ttm_object_device_release(&dev_priv->tdev); 1179 out_err0: 1180 for (i = vmw_res_context; i < vmw_res_max; ++i) 1181 idr_destroy(&dev_priv->res_idr[i]); 1182 1183 if (dev_priv->ctx.staged_bindings) 1184 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1185 out_no_pci_or_version: 1186 pci_release_regions(pdev); 1187 return ret; 1188 } 1189 1190 static void vmw_driver_unload(struct drm_device *dev) 1191 { 1192 struct vmw_private *dev_priv = vmw_priv(dev); 1193 struct pci_dev *pdev = to_pci_dev(dev->dev); 1194 enum vmw_res_type i; 1195 1196 unregister_pm_notifier(&dev_priv->pm_nb); 1197 1198 vmw_sw_context_fini(dev_priv); 1199 vmw_fifo_resource_dec(dev_priv); 1200 1201 vmw_svga_disable(dev_priv); 1202 1203 vmw_vkms_cleanup(dev_priv); 1204 vmw_kms_close(dev_priv); 1205 vmw_overlay_close(dev_priv); 1206 1207 if (dev_priv->has_gmr) 1208 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1209 1210 vmw_release_device_early(dev_priv); 1211 if (dev_priv->has_mob) { 1212 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1213 vmw_sys_man_fini(dev_priv); 1214 } 1215 vmw_devcaps_destroy(dev_priv); 1216 vmw_vram_manager_fini(dev_priv); 1217 ttm_device_fini(&dev_priv->bdev); 1218 vmw_release_device_late(dev_priv); 1219 vmw_fence_manager_takedown(dev_priv->fman); 1220 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1221 vmw_irq_uninstall(&dev_priv->drm); 1222 1223 ttm_object_device_release(&dev_priv->tdev); 1224 1225 for (i = vmw_res_context; i < vmw_res_max; ++i) 1226 idr_destroy(&dev_priv->res_idr[i]); 1227 1228 vmw_mksstat_remove_all(dev_priv); 1229 1230 pci_release_regions(pdev); 1231 } 1232 1233 static void vmw_postclose(struct drm_device *dev, 1234 struct drm_file *file_priv) 1235 { 1236 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1237 1238 ttm_object_file_release(&vmw_fp->tfile); 1239 kfree(vmw_fp); 1240 } 1241 1242 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1243 { 1244 struct vmw_private *dev_priv = vmw_priv(dev); 1245 struct vmw_fpriv *vmw_fp; 1246 int ret = -ENOMEM; 1247 1248 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1249 if (unlikely(!vmw_fp)) 1250 return ret; 1251 1252 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev); 1253 if (unlikely(vmw_fp->tfile == NULL)) 1254 goto out_no_tfile; 1255 1256 file_priv->driver_priv = vmw_fp; 1257 1258 return 0; 1259 1260 out_no_tfile: 1261 kfree(vmw_fp); 1262 return ret; 1263 } 1264 1265 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1266 unsigned long arg, 1267 long (*ioctl_func)(struct file *, unsigned int, 1268 unsigned long)) 1269 { 1270 struct drm_file *file_priv = filp->private_data; 1271 struct drm_device *dev = file_priv->minor->dev; 1272 unsigned int nr = DRM_IOCTL_NR(cmd); 1273 unsigned int flags; 1274 1275 /* 1276 * Do extra checking on driver private ioctls. 1277 */ 1278 1279 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1280 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1281 const struct drm_ioctl_desc *ioctl = 1282 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1283 1284 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1285 return ioctl_func(filp, cmd, arg); 1286 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1287 if (!drm_is_current_master(file_priv) && 1288 !capable(CAP_SYS_ADMIN)) 1289 return -EACCES; 1290 } 1291 1292 if (unlikely(ioctl->cmd != cmd)) 1293 goto out_io_encoding; 1294 1295 flags = ioctl->flags; 1296 } else if (!drm_ioctl_flags(nr, &flags)) 1297 return -EINVAL; 1298 1299 return ioctl_func(filp, cmd, arg); 1300 1301 out_io_encoding: 1302 DRM_ERROR("Invalid command format, ioctl %d\n", 1303 nr - DRM_COMMAND_BASE); 1304 1305 return -EINVAL; 1306 } 1307 1308 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1309 unsigned long arg) 1310 { 1311 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1312 } 1313 1314 #ifdef CONFIG_COMPAT 1315 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1316 unsigned long arg) 1317 { 1318 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1319 } 1320 #endif 1321 1322 static void vmw_master_set(struct drm_device *dev, 1323 struct drm_file *file_priv, 1324 bool from_open) 1325 { 1326 /* 1327 * Inform a new master that the layout may have changed while 1328 * it was gone. 1329 */ 1330 if (!from_open) 1331 drm_sysfs_hotplug_event(dev); 1332 } 1333 1334 static void vmw_master_drop(struct drm_device *dev, 1335 struct drm_file *file_priv) 1336 { 1337 struct vmw_private *dev_priv = vmw_priv(dev); 1338 1339 vmw_kms_legacy_hotspot_clear(dev_priv); 1340 } 1341 1342 bool vmwgfx_supported(struct vmw_private *vmw) 1343 { 1344 #if defined(CONFIG_X86) 1345 return hypervisor_is_type(X86_HYPER_VMWARE); 1346 #elif defined(CONFIG_ARM64) 1347 /* 1348 * On aarch64 only svga3 is supported 1349 */ 1350 return vmw->pci_id == VMWGFX_PCI_ID_SVGA3; 1351 #else 1352 drm_warn_once(&vmw->drm, 1353 "vmwgfx is running on an unknown architecture."); 1354 return false; 1355 #endif 1356 } 1357 1358 /** 1359 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1360 * 1361 * @dev_priv: Pointer to device private struct. 1362 * Needs the reservation sem to be held in non-exclusive mode. 1363 */ 1364 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1365 { 1366 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1367 1368 if (!ttm_resource_manager_used(man)) { 1369 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1370 ttm_resource_manager_set_used(man, true); 1371 } 1372 } 1373 1374 /** 1375 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1376 * 1377 * @dev_priv: Pointer to device private struct. 1378 */ 1379 void vmw_svga_enable(struct vmw_private *dev_priv) 1380 { 1381 __vmw_svga_enable(dev_priv); 1382 } 1383 1384 /** 1385 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1386 * 1387 * @dev_priv: Pointer to device private struct. 1388 * Needs the reservation sem to be held in exclusive mode. 1389 * Will not empty VRAM. VRAM must be emptied by caller. 1390 */ 1391 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1392 { 1393 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1394 1395 if (ttm_resource_manager_used(man)) { 1396 ttm_resource_manager_set_used(man, false); 1397 vmw_write(dev_priv, SVGA_REG_ENABLE, 1398 SVGA_REG_ENABLE_HIDE | 1399 SVGA_REG_ENABLE_ENABLE); 1400 } 1401 } 1402 1403 /** 1404 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1405 * running. 1406 * 1407 * @dev_priv: Pointer to device private struct. 1408 * Will empty VRAM. 1409 */ 1410 void vmw_svga_disable(struct vmw_private *dev_priv) 1411 { 1412 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1413 /* 1414 * Disabling SVGA will turn off device modesetting capabilities, so 1415 * notify KMS about that so that it doesn't cache atomic state that 1416 * isn't valid anymore, for example crtcs turned on. 1417 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1418 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1419 * end up with lock order reversal. Thus, a master may actually perform 1420 * a new modeset just after we call vmw_kms_lost_device() and race with 1421 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1422 * to be inconsistent with the device, causing modesetting problems. 1423 * 1424 */ 1425 vmw_kms_lost_device(&dev_priv->drm); 1426 if (ttm_resource_manager_used(man)) { 1427 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1428 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1429 ttm_resource_manager_set_used(man, false); 1430 vmw_write(dev_priv, SVGA_REG_ENABLE, 1431 SVGA_REG_ENABLE_HIDE | 1432 SVGA_REG_ENABLE_ENABLE); 1433 } 1434 } 1435 1436 static void vmw_remove(struct pci_dev *pdev) 1437 { 1438 struct drm_device *dev = pci_get_drvdata(pdev); 1439 1440 drm_dev_unregister(dev); 1441 vmw_driver_unload(dev); 1442 } 1443 1444 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) 1445 { 1446 struct drm_minor *minor = vmw->drm.primary; 1447 struct dentry *root = minor->debugfs_root; 1448 1449 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM), 1450 root, "system_ttm"); 1451 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM), 1452 root, "vram_ttm"); 1453 if (vmw->has_gmr) 1454 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1455 root, "gmr_ttm"); 1456 if (vmw->has_mob) { 1457 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1458 root, "mob_ttm"); 1459 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1460 root, "system_mob_ttm"); 1461 } 1462 } 1463 1464 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1465 void *ptr) 1466 { 1467 struct vmw_private *dev_priv = 1468 container_of(nb, struct vmw_private, pm_nb); 1469 1470 switch (val) { 1471 case PM_HIBERNATION_PREPARE: 1472 /* 1473 * Take the reservation sem in write mode, which will make sure 1474 * there are no other processes holding a buffer object 1475 * reservation, meaning we should be able to evict all buffer 1476 * objects if needed. 1477 * Once user-space processes have been frozen, we can release 1478 * the lock again. 1479 */ 1480 dev_priv->suspend_locked = true; 1481 break; 1482 case PM_POST_HIBERNATION: 1483 case PM_POST_RESTORE: 1484 if (READ_ONCE(dev_priv->suspend_locked)) { 1485 dev_priv->suspend_locked = false; 1486 } 1487 break; 1488 default: 1489 break; 1490 } 1491 return 0; 1492 } 1493 1494 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1495 { 1496 struct drm_device *dev = pci_get_drvdata(pdev); 1497 struct vmw_private *dev_priv = vmw_priv(dev); 1498 1499 if (dev_priv->refuse_hibernation) 1500 return -EBUSY; 1501 1502 pci_save_state(pdev); 1503 pci_disable_device(pdev); 1504 pci_set_power_state(pdev, PCI_D3hot); 1505 return 0; 1506 } 1507 1508 static int vmw_pci_resume(struct pci_dev *pdev) 1509 { 1510 pci_set_power_state(pdev, PCI_D0); 1511 pci_restore_state(pdev); 1512 return pci_enable_device(pdev); 1513 } 1514 1515 static int vmw_pm_suspend(struct device *kdev) 1516 { 1517 struct pci_dev *pdev = to_pci_dev(kdev); 1518 struct pm_message dummy; 1519 1520 dummy.event = 0; 1521 1522 return vmw_pci_suspend(pdev, dummy); 1523 } 1524 1525 static int vmw_pm_resume(struct device *kdev) 1526 { 1527 struct pci_dev *pdev = to_pci_dev(kdev); 1528 1529 return vmw_pci_resume(pdev); 1530 } 1531 1532 static int vmw_pm_freeze(struct device *kdev) 1533 { 1534 struct pci_dev *pdev = to_pci_dev(kdev); 1535 struct drm_device *dev = pci_get_drvdata(pdev); 1536 struct vmw_private *dev_priv = vmw_priv(dev); 1537 struct ttm_operation_ctx ctx = { 1538 .interruptible = false, 1539 .no_wait_gpu = false 1540 }; 1541 int ret; 1542 1543 /* 1544 * No user-space processes should be running now. 1545 */ 1546 ret = vmw_kms_suspend(&dev_priv->drm); 1547 if (ret) { 1548 DRM_ERROR("Failed to freeze modesetting.\n"); 1549 return ret; 1550 } 1551 1552 vmw_execbuf_release_pinned_bo(dev_priv); 1553 vmw_resource_evict_all(dev_priv); 1554 vmw_release_device_early(dev_priv); 1555 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1556 vmw_fifo_resource_dec(dev_priv); 1557 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1558 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1559 vmw_fifo_resource_inc(dev_priv); 1560 WARN_ON(vmw_request_device_late(dev_priv)); 1561 dev_priv->suspend_locked = false; 1562 if (dev_priv->suspend_state) 1563 vmw_kms_resume(dev); 1564 return -EBUSY; 1565 } 1566 1567 vmw_fence_fifo_down(dev_priv->fman); 1568 __vmw_svga_disable(dev_priv); 1569 1570 vmw_release_device_late(dev_priv); 1571 return 0; 1572 } 1573 1574 static int vmw_pm_restore(struct device *kdev) 1575 { 1576 struct pci_dev *pdev = to_pci_dev(kdev); 1577 struct drm_device *dev = pci_get_drvdata(pdev); 1578 struct vmw_private *dev_priv = vmw_priv(dev); 1579 int ret; 1580 1581 vmw_detect_version(dev_priv); 1582 1583 vmw_fifo_resource_inc(dev_priv); 1584 1585 ret = vmw_request_device(dev_priv); 1586 if (ret) 1587 return ret; 1588 1589 __vmw_svga_enable(dev_priv); 1590 1591 vmw_fence_fifo_up(dev_priv->fman); 1592 dev_priv->suspend_locked = false; 1593 if (dev_priv->suspend_state) 1594 vmw_kms_resume(&dev_priv->drm); 1595 1596 return 0; 1597 } 1598 1599 static const struct dev_pm_ops vmw_pm_ops = { 1600 .freeze = vmw_pm_freeze, 1601 .thaw = vmw_pm_restore, 1602 .restore = vmw_pm_restore, 1603 .suspend = vmw_pm_suspend, 1604 .resume = vmw_pm_resume, 1605 }; 1606 1607 static const struct file_operations vmwgfx_driver_fops = { 1608 .owner = THIS_MODULE, 1609 .open = drm_open, 1610 .release = drm_release, 1611 .unlocked_ioctl = vmw_unlocked_ioctl, 1612 .mmap = drm_gem_mmap, 1613 .poll = drm_poll, 1614 .read = drm_read, 1615 #if defined(CONFIG_COMPAT) 1616 .compat_ioctl = vmw_compat_ioctl, 1617 #endif 1618 .llseek = noop_llseek, 1619 }; 1620 1621 static const struct drm_driver driver = { 1622 .driver_features = 1623 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT, 1624 .ioctls = vmw_ioctls, 1625 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1626 .master_set = vmw_master_set, 1627 .master_drop = vmw_master_drop, 1628 .open = vmw_driver_open, 1629 .postclose = vmw_postclose, 1630 1631 .dumb_create = vmw_dumb_create, 1632 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1633 1634 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1635 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1636 .gem_prime_import_sg_table = vmw_prime_import_sg_table, 1637 1638 .fops = &vmwgfx_driver_fops, 1639 .name = VMWGFX_DRIVER_NAME, 1640 .desc = VMWGFX_DRIVER_DESC, 1641 .date = VMWGFX_DRIVER_DATE, 1642 .major = VMWGFX_DRIVER_MAJOR, 1643 .minor = VMWGFX_DRIVER_MINOR, 1644 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1645 }; 1646 1647 static struct pci_driver vmw_pci_driver = { 1648 .name = VMWGFX_DRIVER_NAME, 1649 .id_table = vmw_pci_id_list, 1650 .probe = vmw_probe, 1651 .remove = vmw_remove, 1652 .driver = { 1653 .pm = &vmw_pm_ops 1654 } 1655 }; 1656 1657 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1658 { 1659 struct vmw_private *vmw; 1660 int ret; 1661 1662 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver); 1663 if (ret) 1664 goto out_error; 1665 1666 ret = pcim_enable_device(pdev); 1667 if (ret) 1668 goto out_error; 1669 1670 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1671 struct vmw_private, drm); 1672 if (IS_ERR(vmw)) { 1673 ret = PTR_ERR(vmw); 1674 goto out_error; 1675 } 1676 1677 pci_set_drvdata(pdev, &vmw->drm); 1678 1679 ret = vmw_driver_load(vmw, ent->device); 1680 if (ret) 1681 goto out_error; 1682 1683 ret = drm_dev_register(&vmw->drm, 0); 1684 if (ret) 1685 goto out_unload; 1686 1687 vmw_fifo_resource_inc(vmw); 1688 vmw_svga_enable(vmw); 1689 drm_fbdev_generic_setup(&vmw->drm, 0); 1690 1691 vmw_debugfs_gem_init(vmw); 1692 vmw_debugfs_resource_managers_init(vmw); 1693 1694 return 0; 1695 out_unload: 1696 vmw_driver_unload(&vmw->drm); 1697 out_error: 1698 return ret; 1699 } 1700 1701 drm_module_pci_driver(vmw_pci_driver); 1702 1703 MODULE_AUTHOR("VMware Inc. and others"); 1704 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1705 MODULE_LICENSE("GPL and additional rights"); 1706 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1707 __stringify(VMWGFX_DRIVER_MINOR) "." 1708 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1709 "0"); 1710