1 /********************************************************** 2 * Copyright 1998-2015 VMware, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person 5 * obtaining a copy of this software and associated documentation 6 * files (the "Software"), to deal in the Software without 7 * restriction, including without limitation the rights to use, copy, 8 * modify, merge, publish, distribute, sublicense, and/or sell copies 9 * of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 * 24 **********************************************************/ 25 26 /* 27 * svga_reg.h -- 28 * 29 * Virtual hardware definitions for the VMware SVGA II device. 30 */ 31 32 #ifndef _SVGA_REG_H_ 33 #define _SVGA_REG_H_ 34 #include <linux/pci_ids.h> 35 36 #define INCLUDE_ALLOW_MODULE 37 #define INCLUDE_ALLOW_USERLEVEL 38 39 #define INCLUDE_ALLOW_VMCORE 40 #include "includeCheck.h" 41 42 #include "svga_types.h" 43 44 /* 45 * SVGA_REG_ENABLE bit definitions. 46 */ 47 typedef enum { 48 SVGA_REG_ENABLE_DISABLE = 0, 49 SVGA_REG_ENABLE_ENABLE = (1 << 0), 50 SVGA_REG_ENABLE_HIDE = (1 << 1), 51 } SvgaRegEnable; 52 53 typedef uint32 SVGAMobId; 54 55 /* 56 * Arbitrary and meaningless limits. Please ignore these when writing 57 * new drivers. 58 */ 59 #define SVGA_MAX_WIDTH 2560 60 #define SVGA_MAX_HEIGHT 1600 61 62 63 #define SVGA_MAX_BITS_PER_PIXEL 32 64 #define SVGA_MAX_DEPTH 24 65 #define SVGA_MAX_DISPLAYS 10 66 67 /* 68 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned 69 * cursor bypass mode. This is still supported, but no new guest 70 * drivers should use it. 71 */ 72 #define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */ 73 #define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */ 74 #define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */ 75 #define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */ 76 77 /* 78 * The maximum framebuffer size that can traced for guests unless the 79 * SVGA_CAP_GBOBJECTS is set in SVGA_REG_CAPABILITIES. In that case 80 * the full framebuffer can be traced independent of this limit. 81 */ 82 #define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000 83 84 #define SVGA_MAX_PSEUDOCOLOR_DEPTH 8 85 #define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH) 86 #define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS) 87 88 #define SVGA_MAGIC 0x900000UL 89 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 90 91 /* Version 2 let the address of the frame buffer be unsigned on Win32 */ 92 #define SVGA_VERSION_2 2 93 #define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2) 94 95 /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so 96 PALETTE_BASE has moved */ 97 #define SVGA_VERSION_1 1 98 #define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1) 99 100 /* Version 0 is the initial version */ 101 #define SVGA_VERSION_0 0 102 #define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0) 103 104 /* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */ 105 #define SVGA_ID_INVALID 0xFFFFFFFF 106 107 /* Port offsets, relative to BAR0 */ 108 #define SVGA_INDEX_PORT 0x0 109 #define SVGA_VALUE_PORT 0x1 110 #define SVGA_BIOS_PORT 0x2 111 #define SVGA_IRQSTATUS_PORT 0x8 112 113 /* 114 * Interrupt source flags for IRQSTATUS_PORT and IRQMASK. 115 * 116 * Interrupts are only supported when the 117 * SVGA_CAP_IRQMASK capability is present. 118 */ 119 #define SVGA_IRQFLAG_ANY_FENCE 0x1 /* Any fence was passed */ 120 #define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */ 121 #define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */ 122 #define SVGA_IRQFLAG_COMMAND_BUFFER 0x8 /* Command buffer completed */ 123 #define SVGA_IRQFLAG_ERROR 0x10 /* Error while processing commands */ 124 125 /* 126 * Registers 127 */ 128 129 enum { 130 SVGA_REG_ID = 0, 131 SVGA_REG_ENABLE = 1, 132 SVGA_REG_WIDTH = 2, 133 SVGA_REG_HEIGHT = 3, 134 SVGA_REG_MAX_WIDTH = 4, 135 SVGA_REG_MAX_HEIGHT = 5, 136 SVGA_REG_DEPTH = 6, 137 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 138 SVGA_REG_PSEUDOCOLOR = 8, 139 SVGA_REG_RED_MASK = 9, 140 SVGA_REG_GREEN_MASK = 10, 141 SVGA_REG_BLUE_MASK = 11, 142 SVGA_REG_BYTES_PER_LINE = 12, 143 SVGA_REG_FB_START = 13, /* (Deprecated) */ 144 SVGA_REG_FB_OFFSET = 14, 145 SVGA_REG_VRAM_SIZE = 15, 146 SVGA_REG_FB_SIZE = 16, 147 148 /* ID 0 implementation only had the above registers, then the palette */ 149 SVGA_REG_ID_0_TOP = 17, 150 151 SVGA_REG_CAPABILITIES = 17, 152 SVGA_REG_MEM_START = 18, /* (Deprecated) */ 153 SVGA_REG_MEM_SIZE = 19, 154 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 155 SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ 156 SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */ 157 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 158 SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */ 159 SVGA_REG_CURSOR_X = 25, /* (Deprecated) */ 160 SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */ 161 SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */ 162 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */ 163 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 164 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 165 SVGA_REG_NUM_DISPLAYS = 31, /* (Deprecated) */ 166 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 167 SVGA_REG_IRQMASK = 33, /* Interrupt mask */ 168 169 /* Legacy multi-monitor support */ 170 SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */ 171 SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */ 172 SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */ 173 SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */ 174 SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */ 175 SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */ 176 SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */ 177 178 /* See "Guest memory regions" below. */ 179 SVGA_REG_GMR_ID = 41, 180 SVGA_REG_GMR_DESCRIPTOR = 42, 181 SVGA_REG_GMR_MAX_IDS = 43, 182 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44, 183 184 SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ 185 SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */ 186 SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ 187 SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */ 188 SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */ 189 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */ 190 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */ 191 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */ 192 SVGA_REG_CMD_PREPEND_LOW = 53, 193 SVGA_REG_CMD_PREPEND_HIGH = 54, 194 SVGA_REG_SCREENTARGET_MAX_WIDTH = 55, 195 SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56, 196 SVGA_REG_MOB_MAX_SIZE = 57, 197 SVGA_REG_TOP = 58, /* Must be 1 more than the last register */ 198 199 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 200 /* Next 768 (== 256*3) registers exist for colormap */ 201 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS 202 /* Base of scratch registers */ 203 /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage: 204 First 4 are reserved for VESA BIOS Extension; any remaining are for 205 the use of the current SVGA driver. */ 206 }; 207 208 /* 209 * Guest memory regions (GMRs): 210 * 211 * This is a new memory mapping feature available in SVGA devices 212 * which have the SVGA_CAP_GMR bit set. Previously, there were two 213 * fixed memory regions available with which to share data between the 214 * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs 215 * are our name for an extensible way of providing arbitrary DMA 216 * buffers for use between the driver and the SVGA device. They are a 217 * new alternative to framebuffer memory, usable for both 2D and 3D 218 * graphics operations. 219 * 220 * Since GMR mapping must be done synchronously with guest CPU 221 * execution, we use a new pair of SVGA registers: 222 * 223 * SVGA_REG_GMR_ID -- 224 * 225 * Read/write. 226 * This register holds the 32-bit ID (a small positive integer) 227 * of a GMR to create, delete, or redefine. Writing this register 228 * has no side-effects. 229 * 230 * SVGA_REG_GMR_DESCRIPTOR -- 231 * 232 * Write-only. 233 * Writing this register will create, delete, or redefine the GMR 234 * specified by the above ID register. If this register is zero, 235 * the GMR is deleted. Any pointers into this GMR (including those 236 * currently being processed by FIFO commands) will be 237 * synchronously invalidated. 238 * 239 * If this register is nonzero, it must be the physical page 240 * number (PPN) of a data structure which describes the physical 241 * layout of the memory region this GMR should describe. The 242 * descriptor structure will be read synchronously by the SVGA 243 * device when this register is written. The descriptor need not 244 * remain allocated for the lifetime of the GMR. 245 * 246 * The guest driver should write SVGA_REG_GMR_ID first, then 247 * SVGA_REG_GMR_DESCRIPTOR. 248 * 249 * SVGA_REG_GMR_MAX_IDS -- 250 * 251 * Read-only. 252 * The SVGA device may choose to support a maximum number of 253 * user-defined GMR IDs. This register holds the number of supported 254 * IDs. (The maximum supported ID plus 1) 255 * 256 * SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH -- 257 * 258 * Read-only. 259 * The SVGA device may choose to put a limit on the total number 260 * of SVGAGuestMemDescriptor structures it will read when defining 261 * a single GMR. 262 * 263 * The descriptor structure is an array of SVGAGuestMemDescriptor 264 * structures. Each structure may do one of three things: 265 * 266 * - Terminate the GMR descriptor list. 267 * (ppn==0, numPages==0) 268 * 269 * - Add a PPN or range of PPNs to the GMR's virtual address space. 270 * (ppn != 0, numPages != 0) 271 * 272 * - Provide the PPN of the next SVGAGuestMemDescriptor, in order to 273 * support multi-page GMR descriptor tables without forcing the 274 * driver to allocate physically contiguous memory. 275 * (ppn != 0, numPages == 0) 276 * 277 * Note that each physical page of SVGAGuestMemDescriptor structures 278 * can describe at least 2MB of guest memory. If the driver needs to 279 * use more than one page of descriptor structures, it must use one of 280 * its SVGAGuestMemDescriptors to point to an additional page. The 281 * device will never automatically cross a page boundary. 282 * 283 * Once the driver has described a GMR, it is immediately available 284 * for use via any FIFO command that uses an SVGAGuestPtr structure. 285 * These pointers include a GMR identifier plus an offset into that 286 * GMR. 287 * 288 * The driver must check the SVGA_CAP_GMR bit before using the GMR 289 * registers. 290 */ 291 292 /* 293 * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer 294 * memory as well. In the future, these IDs could even be used to 295 * allow legacy memory regions to be redefined by the guest as GMRs. 296 * 297 * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA 298 * is being phased out. Please try to use user-defined GMRs whenever 299 * possible. 300 */ 301 #define SVGA_GMR_NULL ((uint32) -1) 302 #define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */ 303 304 typedef 305 #include "vmware_pack_begin.h" 306 struct SVGAGuestMemDescriptor { 307 uint32 ppn; 308 uint32 numPages; 309 } 310 #include "vmware_pack_end.h" 311 SVGAGuestMemDescriptor; 312 313 typedef 314 #include "vmware_pack_begin.h" 315 struct SVGAGuestPtr { 316 uint32 gmrId; 317 uint32 offset; 318 } 319 #include "vmware_pack_end.h" 320 SVGAGuestPtr; 321 322 /* 323 * Register based command buffers -- 324 * 325 * Provide an SVGA device interface that allows the guest to submit 326 * command buffers to the SVGA device through an SVGA device register. 327 * The metadata for each command buffer is contained in the 328 * SVGACBHeader structure along with the return status codes. 329 * 330 * The SVGA device supports command buffers if 331 * SVGA_CAP_COMMAND_BUFFERS is set in the device caps register. The 332 * fifo must be enabled for command buffers to be submitted. 333 * 334 * Command buffers are submitted when the guest writing the 64 byte 335 * aligned physical address into the SVGA_REG_COMMAND_LOW and 336 * SVGA_REG_COMMAND_HIGH. SVGA_REG_COMMAND_HIGH contains the upper 32 337 * bits of the physical address. SVGA_REG_COMMAND_LOW contains the 338 * lower 32 bits of the physical address, since the command buffer 339 * headers are required to be 64 byte aligned the lower 6 bits are 340 * used for the SVGACBContext value. Writing to SVGA_REG_COMMAND_LOW 341 * submits the command buffer to the device and queues it for 342 * execution. The SVGA device supports at least 343 * SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued 344 * per context and if that limit is reached the device will write the 345 * status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command 346 * buffer header synchronously and not raise any IRQs. 347 * 348 * It is invalid to submit a command buffer without a valid physical 349 * address and results are undefined. 350 * 351 * The device guarantees that command buffers of size SVGA_CB_MAX_SIZE 352 * will be supported. If a larger command buffer is submitted results 353 * are unspecified and the device will either complete the command 354 * buffer or return an error. 355 * 356 * The device guarantees that any individual command in a command 357 * buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is 358 * enough to fit a 64x64 color-cursor definition. If the command is 359 * too large the device is allowed to process the command or return an 360 * error. 361 * 362 * The device context is a special SVGACBContext that allows for 363 * synchronous register like accesses with the flexibility of 364 * commands. There is a different command set defined by 365 * SVGADeviceContextCmdId. The commands in each command buffer is not 366 * allowed to straddle physical pages. 367 * 368 * The offset field which is available starting with the 369 * SVGA_CAP_CMD_BUFFERS_2 cap bit can be set by the guest to bias the 370 * start of command processing into the buffer. If an error is 371 * encountered the errorOffset will still be relative to the specific 372 * PA, not biased by the offset. When the command buffer is finished 373 * the guest should not read the offset field as there is no guarantee 374 * what it will set to. 375 * 376 * When the SVGA_CAP_HP_CMD_QUEUE cap bit is set a new command queue 377 * SVGA_CB_CONTEXT_1 is available. Commands submitted to this queue 378 * will be executed as quickly as possible by the SVGA device 379 * potentially before already queued commands on SVGA_CB_CONTEXT_0. 380 * The SVGA device guarantees that any command buffers submitted to 381 * SVGA_CB_CONTEXT_0 will be executed after any _already_ submitted 382 * command buffers to SVGA_CB_CONTEXT_1. 383 */ 384 385 #define SVGA_CB_MAX_SIZE (512 * 1024) /* 512 KB */ 386 #define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32 387 #define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) /* 32 KB */ 388 389 #define SVGA_CB_CONTEXT_MASK 0x3f 390 typedef enum { 391 SVGA_CB_CONTEXT_DEVICE = 0x3f, 392 SVGA_CB_CONTEXT_0 = 0x0, 393 SVGA_CB_CONTEXT_1 = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */ 394 SVGA_CB_CONTEXT_MAX = 0x2, 395 } SVGACBContext; 396 397 398 typedef enum { 399 /* 400 * The guest is supposed to write SVGA_CB_STATUS_NONE to the status 401 * field before submitting the command buffer header, the host will 402 * change the value when it is done with the command buffer. 403 */ 404 SVGA_CB_STATUS_NONE = 0, 405 406 /* 407 * Written by the host when a command buffer completes successfully. 408 * The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless 409 * the SVGA_CB_FLAG_NO_IRQ flag is set. 410 */ 411 SVGA_CB_STATUS_COMPLETED = 1, 412 413 /* 414 * Written by the host synchronously with the command buffer 415 * submission to indicate the command buffer was not submitted. No 416 * IRQ is raised. 417 */ 418 SVGA_CB_STATUS_QUEUE_FULL = 2, 419 420 /* 421 * Written by the host when an error was detected parsing a command 422 * in the command buffer, errorOffset is written to contain the 423 * offset to the first byte of the failing command. The device 424 * raises the IRQ with both SVGA_IRQFLAG_ERROR and 425 * SVGA_IRQFLAG_COMMAND_BUFFER. Some of the commands may have been 426 * processed. 427 */ 428 SVGA_CB_STATUS_COMMAND_ERROR = 3, 429 430 /* 431 * Written by the host if there is an error parsing the command 432 * buffer header. The device raises the IRQ with both 433 * SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER. The device 434 * did not processes any of the command buffer. 435 */ 436 SVGA_CB_STATUS_CB_HEADER_ERROR = 4, 437 438 /* 439 * Written by the host if the guest requested the host to preempt 440 * the command buffer. The device will not raise any IRQs and the 441 * command buffer was not processed. 442 */ 443 SVGA_CB_STATUS_PREEMPTED = 5, 444 445 /* 446 * Written by the host synchronously with the command buffer 447 * submission to indicate the the command buffer was not submitted 448 * due to an error. No IRQ is raised. 449 */ 450 SVGA_CB_STATUS_SUBMISSION_ERROR = 6, 451 } SVGACBStatus; 452 453 typedef enum { 454 SVGA_CB_FLAG_NONE = 0, 455 SVGA_CB_FLAG_NO_IRQ = 1 << 0, 456 SVGA_CB_FLAG_DX_CONTEXT = 1 << 1, 457 SVGA_CB_FLAG_MOB = 1 << 2, 458 } SVGACBFlags; 459 460 typedef 461 #include "vmware_pack_begin.h" 462 struct { 463 volatile SVGACBStatus status; 464 volatile uint32 errorOffset; 465 uint64 id; 466 SVGACBFlags flags; 467 uint32 length; 468 union { 469 PA pa; 470 struct { 471 SVGAMobId mobid; 472 uint32 mobOffset; 473 } mob; 474 } ptr; 475 uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise */ 476 uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */ 477 uint32 mustBeZero[6]; 478 } 479 #include "vmware_pack_end.h" 480 SVGACBHeader; 481 482 typedef enum { 483 SVGA_DC_CMD_NOP = 0, 484 SVGA_DC_CMD_START_STOP_CONTEXT = 1, 485 SVGA_DC_CMD_PREEMPT = 2, 486 SVGA_DC_CMD_MAX = 3, 487 SVGA_DC_CMD_FORCE_UINT = MAX_UINT32, 488 } SVGADeviceContextCmdId; 489 490 typedef struct { 491 uint32 enable; 492 SVGACBContext context; 493 } SVGADCCmdStartStop; 494 495 /* 496 * SVGADCCmdPreempt -- 497 * 498 * This command allows the guest to request that all command buffers 499 * on the specified context be preempted that can be. After execution 500 * of this command all command buffers that were preempted will 501 * already have SVGA_CB_STATUS_PREEMPTED written into the status 502 * field. The device might still be processing a command buffer, 503 * assuming execution of it started before the preemption request was 504 * received. Specifying the ignoreIDZero flag to TRUE will cause the 505 * device to not preempt command buffers with the id field in the 506 * command buffer header set to zero. 507 */ 508 509 typedef struct { 510 SVGACBContext context; 511 uint32 ignoreIDZero; 512 } SVGADCCmdPreempt; 513 514 /* 515 * SVGAGMRImageFormat -- 516 * 517 * This is a packed representation of the source 2D image format 518 * for a GMR-to-screen blit. Currently it is defined as an encoding 519 * of the screen's color depth and bits-per-pixel, however, 16 bits 520 * are reserved for future use to identify other encodings (such as 521 * RGBA or higher-precision images). 522 * 523 * Currently supported formats: 524 * 525 * bpp depth Format Name 526 * --- ----- ----------- 527 * 32 24 32-bit BGRX 528 * 24 24 24-bit BGR 529 * 16 16 RGB 5-6-5 530 * 16 15 RGB 5-5-5 531 * 532 */ 533 534 typedef struct SVGAGMRImageFormat { 535 union { 536 struct { 537 uint32 bitsPerPixel : 8; 538 uint32 colorDepth : 8; 539 uint32 reserved : 16; /* Must be zero */ 540 }; 541 542 uint32 value; 543 }; 544 } SVGAGMRImageFormat; 545 546 typedef 547 #include "vmware_pack_begin.h" 548 struct SVGAGuestImage { 549 SVGAGuestPtr ptr; 550 551 /* 552 * A note on interpretation of pitch: This value of pitch is the 553 * number of bytes between vertically adjacent image 554 * blocks. Normally this is the number of bytes between the first 555 * pixel of two adjacent scanlines. With compressed textures, 556 * however, this may represent the number of bytes between 557 * compression blocks rather than between rows of pixels. 558 * 559 * XXX: Compressed textures currently must be tightly packed in guest memory. 560 * 561 * If the image is 1-dimensional, pitch is ignored. 562 * 563 * If 'pitch' is zero, the SVGA3D device calculates a pitch value 564 * assuming each row of blocks is tightly packed. 565 */ 566 uint32 pitch; 567 } 568 #include "vmware_pack_end.h" 569 SVGAGuestImage; 570 571 /* 572 * SVGAColorBGRX -- 573 * 574 * A 24-bit color format (BGRX), which does not depend on the 575 * format of the legacy guest framebuffer (GFB) or the current 576 * GMRFB state. 577 */ 578 579 typedef struct SVGAColorBGRX { 580 union { 581 struct { 582 uint32 b : 8; 583 uint32 g : 8; 584 uint32 r : 8; 585 uint32 x : 8; /* Unused */ 586 }; 587 588 uint32 value; 589 }; 590 } SVGAColorBGRX; 591 592 593 /* 594 * SVGASignedRect -- 595 * SVGASignedPoint -- 596 * 597 * Signed rectangle and point primitives. These are used by the new 598 * 2D primitives for drawing to Screen Objects, which can occupy a 599 * signed virtual coordinate space. 600 * 601 * SVGASignedRect specifies a half-open interval: the (left, top) 602 * pixel is part of the rectangle, but the (right, bottom) pixel is 603 * not. 604 */ 605 606 typedef 607 #include "vmware_pack_begin.h" 608 struct { 609 int32 left; 610 int32 top; 611 int32 right; 612 int32 bottom; 613 } 614 #include "vmware_pack_end.h" 615 SVGASignedRect; 616 617 typedef 618 #include "vmware_pack_begin.h" 619 struct { 620 int32 x; 621 int32 y; 622 } 623 #include "vmware_pack_end.h" 624 SVGASignedPoint; 625 626 627 /* 628 * SVGA Device Capabilities 629 * 630 * Note the holes in the bitfield. Missing bits have been deprecated, 631 * and must not be reused. Those capabilities will never be reported 632 * by new versions of the SVGA device. 633 * 634 * XXX: Add longer descriptions for each capability, including a list 635 * of the new features that each capability provides. 636 * 637 * SVGA_CAP_IRQMASK -- 638 * Provides device interrupts. Adds device register SVGA_REG_IRQMASK 639 * to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to 640 * set/clear pending interrupts. 641 * 642 * SVGA_CAP_GMR -- 643 * Provides synchronous mapping of guest memory regions (GMR). 644 * Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR, 645 * SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH. 646 * 647 * SVGA_CAP_TRACES -- 648 * Allows framebuffer trace-based updates even when FIFO is enabled. 649 * Adds device register SVGA_REG_TRACES. 650 * 651 * SVGA_CAP_GMR2 -- 652 * Provides asynchronous commands to define and remap guest memory 653 * regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and 654 * SVGA_REG_MEMORY_SIZE. 655 * 656 * SVGA_CAP_SCREEN_OBJECT_2 -- 657 * Allow screen object support, and require backing stores from the 658 * guest for each screen object. 659 * 660 * SVGA_CAP_COMMAND_BUFFERS -- 661 * Enable register based command buffer submission. 662 * 663 * SVGA_CAP_DEAD1 -- 664 * This cap was incorrectly used by old drivers and should not be 665 * reused. 666 * 667 * SVGA_CAP_CMD_BUFFERS_2 -- 668 * Enable support for the prepend command buffer submision 669 * registers. SVGA_REG_CMD_PREPEND_LOW and 670 * SVGA_REG_CMD_PREPEND_HIGH. 671 * 672 * SVGA_CAP_GBOBJECTS -- 673 * Enable guest-backed objects and surfaces. 674 * 675 * SVGA_CAP_CMD_BUFFERS_3 -- 676 * Enable support for command buffers in a mob. 677 */ 678 679 #define SVGA_CAP_NONE 0x00000000 680 #define SVGA_CAP_RECT_COPY 0x00000002 681 #define SVGA_CAP_CURSOR 0x00000020 682 #define SVGA_CAP_CURSOR_BYPASS 0x00000040 683 #define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 684 #define SVGA_CAP_8BIT_EMULATION 0x00000100 685 #define SVGA_CAP_ALPHA_CURSOR 0x00000200 686 #define SVGA_CAP_3D 0x00004000 687 #define SVGA_CAP_EXTENDED_FIFO 0x00008000 688 #define SVGA_CAP_MULTIMON 0x00010000 689 #define SVGA_CAP_PITCHLOCK 0x00020000 690 #define SVGA_CAP_IRQMASK 0x00040000 691 #define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 692 #define SVGA_CAP_GMR 0x00100000 693 #define SVGA_CAP_TRACES 0x00200000 694 #define SVGA_CAP_GMR2 0x00400000 695 #define SVGA_CAP_SCREEN_OBJECT_2 0x00800000 696 #define SVGA_CAP_COMMAND_BUFFERS 0x01000000 697 #define SVGA_CAP_DEAD1 0x02000000 698 #define SVGA_CAP_CMD_BUFFERS_2 0x04000000 699 #define SVGA_CAP_GBOBJECTS 0x08000000 700 #define SVGA_CAP_DX 0x10000000 701 #define SVGA_CAP_HP_CMD_QUEUE 0x20000000 702 703 #define SVGA_CAP_CMD_RESERVED 0x80000000 704 705 706 /* 707 * The Guest can optionally read some SVGA device capabilities through 708 * the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before 709 * the SVGA device is initialized. The type of capability the guest 710 * is requesting from the SVGABackdoorCapType enum should be placed in 711 * the upper 16 bits of the backdoor command id (ECX). On success the 712 * the value of EBX will be set to BDOOR_MAGIC and EAX will be set to 713 * the requested capability. If the command is not supported then EBX 714 * will be left unchanged and EAX will be set to -1. Because it is 715 * possible that -1 is the value of the requested cap the correct way 716 * to check if the command was successful is to check if EBX was changed 717 * to BDOOR_MAGIC making sure to initialize the register to something 718 * else first. 719 */ 720 721 typedef enum { 722 SVGABackdoorCapDeviceCaps = 0, 723 SVGABackdoorCapFifoCaps = 1, 724 SVGABackdoorCap3dHWVersion = 2, 725 SVGABackdoorCapMax = 3, 726 } SVGABackdoorCapType; 727 728 729 /* 730 * FIFO register indices. 731 * 732 * The FIFO is a chunk of device memory mapped into guest physmem. It 733 * is always treated as 32-bit words. 734 * 735 * The guest driver gets to decide how to partition it between 736 * - FIFO registers (there are always at least 4, specifying where the 737 * following data area is and how much data it contains; there may be 738 * more registers following these, depending on the FIFO protocol 739 * version in use) 740 * - FIFO data, written by the guest and slurped out by the VMX. 741 * These indices are 32-bit word offsets into the FIFO. 742 */ 743 744 enum { 745 /* 746 * Block 1 (basic registers): The originally defined FIFO registers. 747 * These exist and are valid for all versions of the FIFO protocol. 748 */ 749 750 SVGA_FIFO_MIN = 0, 751 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 752 SVGA_FIFO_NEXT_CMD, 753 SVGA_FIFO_STOP, 754 755 /* 756 * Block 2 (extended registers): Mandatory registers for the extended 757 * FIFO. These exist if the SVGA caps register includes 758 * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their 759 * associated capability bit is enabled. 760 * 761 * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied 762 * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE. 763 * This means that the guest has to test individually (in most cases 764 * using FIFO caps) for the presence of registers after this; the VMX 765 * can define "extended FIFO" to mean whatever it wants, and currently 766 * won't enable it unless there's room for that set and much more. 767 */ 768 769 SVGA_FIFO_CAPABILITIES = 4, 770 SVGA_FIFO_FLAGS, 771 /* Valid with SVGA_FIFO_CAP_FENCE: */ 772 SVGA_FIFO_FENCE, 773 774 /* 775 * Block 3a (optional extended registers): Additional registers for the 776 * extended FIFO, whose presence isn't actually implied by 777 * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to 778 * leave room for them. 779 * 780 * These in block 3a, the VMX currently considers mandatory for the 781 * extended FIFO. 782 */ 783 784 /* Valid if exists (i.e. if extended FIFO enabled): */ 785 SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */ 786 /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */ 787 SVGA_FIFO_PITCHLOCK, 788 789 /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */ 790 SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */ 791 SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */ 792 SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */ 793 SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */ 794 SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */ 795 796 /* Valid with SVGA_FIFO_CAP_RESERVE: */ 797 SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */ 798 799 /* 800 * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2: 801 * 802 * By default this is SVGA_ID_INVALID, to indicate that the cursor 803 * coordinates are specified relative to the virtual root. If this 804 * is set to a specific screen ID, cursor position is reinterpreted 805 * as a signed offset relative to that screen's origin. 806 */ 807 SVGA_FIFO_CURSOR_SCREEN_ID, 808 809 /* 810 * Valid with SVGA_FIFO_CAP_DEAD 811 * 812 * An arbitrary value written by the host, drivers should not use it. 813 */ 814 SVGA_FIFO_DEAD, 815 816 /* 817 * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED: 818 * 819 * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h) 820 * on platforms that can enforce graphics resource limits. 821 */ 822 SVGA_FIFO_3D_HWVERSION_REVISED, 823 824 /* 825 * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new 826 * registers, but this must be done carefully and with judicious use of 827 * capability bits, since comparisons based on SVGA_FIFO_MIN aren't 828 * enough to tell you whether the register exists: we've shipped drivers 829 * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of 830 * the earlier ones. The actual order of introduction was: 831 * - PITCHLOCK 832 * - 3D_CAPS 833 * - CURSOR_* (cursor bypass 3) 834 * - RESERVED 835 * So, code that wants to know whether it can use any of the 836 * aforementioned registers, or anything else added after PITCHLOCK and 837 * before 3D_CAPS, needs to reason about something other than 838 * SVGA_FIFO_MIN. 839 */ 840 841 /* 842 * 3D caps block space; valid with 3D hardware version >= 843 * SVGA3D_HWVERSION_WS6_B1. 844 */ 845 SVGA_FIFO_3D_CAPS = 32, 846 SVGA_FIFO_3D_CAPS_LAST = 32 + 255, 847 848 /* 849 * End of VMX's current definition of "extended-FIFO registers". 850 * Registers before here are always enabled/disabled as a block; either 851 * the extended FIFO is enabled and includes all preceding registers, or 852 * it's disabled entirely. 853 * 854 * Block 3b (truly optional extended registers): Additional registers for 855 * the extended FIFO, which the VMX already knows how to enable and 856 * disable with correct granularity. 857 * 858 * Registers after here exist if and only if the guest SVGA driver 859 * sets SVGA_FIFO_MIN high enough to leave room for them. 860 */ 861 862 /* Valid if register exists: */ 863 SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */ 864 SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */ 865 SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */ 866 867 /* 868 * Always keep this last. This defines the maximum number of 869 * registers we know about. At power-on, this value is placed in 870 * the SVGA_REG_MEM_REGS register, and we expect the guest driver 871 * to allocate this much space in FIFO memory for registers. 872 */ 873 SVGA_FIFO_NUM_REGS 874 }; 875 876 877 /* 878 * Definition of registers included in extended FIFO support. 879 * 880 * The guest SVGA driver gets to allocate the FIFO between registers 881 * and data. It must always allocate at least 4 registers, but old 882 * drivers stopped there. 883 * 884 * The VMX will enable extended FIFO support if and only if the guest 885 * left enough room for all registers defined as part of the mandatory 886 * set for the extended FIFO. 887 * 888 * Note that the guest drivers typically allocate the FIFO only at 889 * initialization time, not at mode switches, so it's likely that the 890 * number of FIFO registers won't change without a reboot. 891 * 892 * All registers less than this value are guaranteed to be present if 893 * svgaUser->fifo.extended is set. Any later registers must be tested 894 * individually for compatibility at each use (in the VMX). 895 * 896 * This value is used only by the VMX, so it can change without 897 * affecting driver compatibility; keep it that way? 898 */ 899 #define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1) 900 901 902 /* 903 * FIFO Synchronization Registers 904 * 905 * This explains the relationship between the various FIFO 906 * sync-related registers in IOSpace and in FIFO space. 907 * 908 * SVGA_REG_SYNC -- 909 * 910 * The SYNC register can be used in two different ways by the guest: 911 * 912 * 1. If the guest wishes to fully sync (drain) the FIFO, 913 * it will write once to SYNC then poll on the BUSY 914 * register. The FIFO is sync'ed once BUSY is zero. 915 * 916 * 2. If the guest wants to asynchronously wake up the host, 917 * it will write once to SYNC without polling on BUSY. 918 * Ideally it will do this after some new commands have 919 * been placed in the FIFO, and after reading a zero 920 * from SVGA_FIFO_BUSY. 921 * 922 * (1) is the original behaviour that SYNC was designed to 923 * support. Originally, a write to SYNC would implicitly 924 * trigger a read from BUSY. This causes us to synchronously 925 * process the FIFO. 926 * 927 * This behaviour has since been changed so that writing SYNC 928 * will *not* implicitly cause a read from BUSY. Instead, it 929 * makes a channel call which asynchronously wakes up the MKS 930 * thread. 931 * 932 * New guests can use this new behaviour to implement (2) 933 * efficiently. This lets guests get the host's attention 934 * without waiting for the MKS to poll, which gives us much 935 * better CPU utilization on SMP hosts and on UP hosts while 936 * we're blocked on the host GPU. 937 * 938 * Old guests shouldn't notice the behaviour change. SYNC was 939 * never guaranteed to process the entire FIFO, since it was 940 * bounded to a particular number of CPU cycles. Old guests will 941 * still loop on the BUSY register until the FIFO is empty. 942 * 943 * Writing to SYNC currently has the following side-effects: 944 * 945 * - Sets SVGA_REG_BUSY to TRUE (in the monitor) 946 * - Asynchronously wakes up the MKS thread for FIFO processing 947 * - The value written to SYNC is recorded as a "reason", for 948 * stats purposes. 949 * 950 * If SVGA_FIFO_BUSY is available, drivers are advised to only 951 * write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set 952 * SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will 953 * eventually set SVGA_FIFO_BUSY on its own, but this approach 954 * lets the driver avoid sending multiple asynchronous wakeup 955 * messages to the MKS thread. 956 * 957 * SVGA_REG_BUSY -- 958 * 959 * This register is set to TRUE when SVGA_REG_SYNC is written, 960 * and it reads as FALSE when the FIFO has been completely 961 * drained. 962 * 963 * Every read from this register causes us to synchronously 964 * process FIFO commands. There is no guarantee as to how many 965 * commands each read will process. 966 * 967 * CPU time spent processing FIFO commands will be billed to 968 * the guest. 969 * 970 * New drivers should avoid using this register unless they 971 * need to guarantee that the FIFO is completely drained. It 972 * is overkill for performing a sync-to-fence. Older drivers 973 * will use this register for any type of synchronization. 974 * 975 * SVGA_FIFO_BUSY -- 976 * 977 * This register is a fast way for the guest driver to check 978 * whether the FIFO is already being processed. It reads and 979 * writes at normal RAM speeds, with no monitor intervention. 980 * 981 * If this register reads as TRUE, the host is guaranteeing that 982 * any new commands written into the FIFO will be noticed before 983 * the MKS goes back to sleep. 984 * 985 * If this register reads as FALSE, no such guarantee can be 986 * made. 987 * 988 * The guest should use this register to quickly determine 989 * whether or not it needs to wake up the host. If the guest 990 * just wrote a command or group of commands that it would like 991 * the host to begin processing, it should: 992 * 993 * 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further 994 * action is necessary. 995 * 996 * 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest 997 * code that we've already sent a SYNC to the host and we 998 * don't need to send a duplicate. 999 * 1000 * 3. Write a reason to SVGA_REG_SYNC. This will send an 1001 * asynchronous wakeup to the MKS thread. 1002 */ 1003 1004 1005 /* 1006 * FIFO Capabilities 1007 * 1008 * Fence -- Fence register and command are supported 1009 * Accel Front -- Front buffer only commands are supported 1010 * Pitch Lock -- Pitch lock register is supported 1011 * Video -- SVGA Video overlay units are supported 1012 * Escape -- Escape command is supported 1013 * 1014 * XXX: Add longer descriptions for each capability, including a list 1015 * of the new features that each capability provides. 1016 * 1017 * SVGA_FIFO_CAP_SCREEN_OBJECT -- 1018 * 1019 * Provides dynamic multi-screen rendering, for improved Unity and 1020 * multi-monitor modes. With Screen Object, the guest can 1021 * dynamically create and destroy 'screens', which can represent 1022 * Unity windows or virtual monitors. Screen Object also provides 1023 * strong guarantees that DMA operations happen only when 1024 * guest-initiated. Screen Object deprecates the BAR1 guest 1025 * framebuffer (GFB) and all commands that work only with the GFB. 1026 * 1027 * New registers: 1028 * FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID 1029 * 1030 * New 2D commands: 1031 * DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN, 1032 * BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY 1033 * 1034 * New 3D commands: 1035 * BLIT_SURFACE_TO_SCREEN 1036 * 1037 * New guarantees: 1038 * 1039 * - The host will not read or write guest memory, including the GFB, 1040 * except when explicitly initiated by a DMA command. 1041 * 1042 * - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK, 1043 * is guaranteed to complete before any subsequent FENCEs. 1044 * 1045 * - All legacy commands which affect a Screen (UPDATE, PRESENT, 1046 * PRESENT_READBACK) as well as new Screen blit commands will 1047 * all behave consistently as blits, and memory will be read 1048 * or written in FIFO order. 1049 * 1050 * For example, if you PRESENT from one SVGA3D surface to multiple 1051 * places on the screen, the data copied will always be from the 1052 * SVGA3D surface at the time the PRESENT was issued in the FIFO. 1053 * This was not necessarily true on devices without Screen Object. 1054 * 1055 * This means that on devices that support Screen Object, the 1056 * PRESENT_READBACK command should not be necessary unless you 1057 * actually want to read back the results of 3D rendering into 1058 * system memory. (And for that, the BLIT_SCREEN_TO_GMRFB 1059 * command provides a strict superset of functionality.) 1060 * 1061 * - When a screen is resized, either using Screen Object commands or 1062 * legacy multimon registers, its contents are preserved. 1063 * 1064 * SVGA_FIFO_CAP_GMR2 -- 1065 * 1066 * Provides new commands to define and remap guest memory regions (GMR). 1067 * 1068 * New 2D commands: 1069 * DEFINE_GMR2, REMAP_GMR2. 1070 * 1071 * SVGA_FIFO_CAP_3D_HWVERSION_REVISED -- 1072 * 1073 * Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists. 1074 * This register may replace SVGA_FIFO_3D_HWVERSION on platforms 1075 * that enforce graphics resource limits. This allows the platform 1076 * to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest 1077 * drivers that do not limit their resources. 1078 * 1079 * Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators 1080 * are codependent (and thus we use a single capability bit). 1081 * 1082 * SVGA_FIFO_CAP_SCREEN_OBJECT_2 -- 1083 * 1084 * Modifies the DEFINE_SCREEN command to include a guest provided 1085 * backing store in GMR memory and the bytesPerLine for the backing 1086 * store. This capability requires the use of a backing store when 1087 * creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT 1088 * is present then backing stores are optional. 1089 * 1090 * SVGA_FIFO_CAP_DEAD -- 1091 * 1092 * Drivers should not use this cap bit. This cap bit can not be 1093 * reused since some hosts already expose it. 1094 */ 1095 1096 #define SVGA_FIFO_CAP_NONE 0 1097 #define SVGA_FIFO_CAP_FENCE (1<<0) 1098 #define SVGA_FIFO_CAP_ACCELFRONT (1<<1) 1099 #define SVGA_FIFO_CAP_PITCHLOCK (1<<2) 1100 #define SVGA_FIFO_CAP_VIDEO (1<<3) 1101 #define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4) 1102 #define SVGA_FIFO_CAP_ESCAPE (1<<5) 1103 #define SVGA_FIFO_CAP_RESERVE (1<<6) 1104 #define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7) 1105 #define SVGA_FIFO_CAP_GMR2 (1<<8) 1106 #define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2 1107 #define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1<<9) 1108 #define SVGA_FIFO_CAP_DEAD (1<<10) 1109 1110 1111 /* 1112 * FIFO Flags 1113 * 1114 * Accel Front -- Driver should use front buffer only commands 1115 */ 1116 1117 #define SVGA_FIFO_FLAG_NONE 0 1118 #define SVGA_FIFO_FLAG_ACCELFRONT (1<<0) 1119 #define SVGA_FIFO_FLAG_RESERVED (1<<31) /* Internal use only */ 1120 1121 /* 1122 * FIFO reservation sentinel value 1123 */ 1124 1125 #define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff 1126 1127 1128 /* 1129 * Video overlay support 1130 */ 1131 1132 #define SVGA_NUM_OVERLAY_UNITS 32 1133 1134 1135 /* 1136 * Video capabilities that the guest is currently using 1137 */ 1138 1139 #define SVGA_VIDEO_FLAG_COLORKEY 0x0001 1140 1141 1142 /* 1143 * Offsets for the video overlay registers 1144 */ 1145 1146 enum { 1147 SVGA_VIDEO_ENABLED = 0, 1148 SVGA_VIDEO_FLAGS, 1149 SVGA_VIDEO_DATA_OFFSET, 1150 SVGA_VIDEO_FORMAT, 1151 SVGA_VIDEO_COLORKEY, 1152 SVGA_VIDEO_SIZE, /* Deprecated */ 1153 SVGA_VIDEO_WIDTH, 1154 SVGA_VIDEO_HEIGHT, 1155 SVGA_VIDEO_SRC_X, 1156 SVGA_VIDEO_SRC_Y, 1157 SVGA_VIDEO_SRC_WIDTH, 1158 SVGA_VIDEO_SRC_HEIGHT, 1159 SVGA_VIDEO_DST_X, /* Signed int32 */ 1160 SVGA_VIDEO_DST_Y, /* Signed int32 */ 1161 SVGA_VIDEO_DST_WIDTH, 1162 SVGA_VIDEO_DST_HEIGHT, 1163 SVGA_VIDEO_PITCH_1, 1164 SVGA_VIDEO_PITCH_2, 1165 SVGA_VIDEO_PITCH_3, 1166 SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */ 1167 SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */ 1168 /* (SVGA_ID_INVALID) */ 1169 SVGA_VIDEO_NUM_REGS 1170 }; 1171 1172 1173 /* 1174 * SVGA Overlay Units 1175 * 1176 * width and height relate to the entire source video frame. 1177 * srcX, srcY, srcWidth and srcHeight represent subset of the source 1178 * video frame to be displayed. 1179 */ 1180 1181 typedef 1182 #include "vmware_pack_begin.h" 1183 struct SVGAOverlayUnit { 1184 uint32 enabled; 1185 uint32 flags; 1186 uint32 dataOffset; 1187 uint32 format; 1188 uint32 colorKey; 1189 uint32 size; 1190 uint32 width; 1191 uint32 height; 1192 uint32 srcX; 1193 uint32 srcY; 1194 uint32 srcWidth; 1195 uint32 srcHeight; 1196 int32 dstX; 1197 int32 dstY; 1198 uint32 dstWidth; 1199 uint32 dstHeight; 1200 uint32 pitches[3]; 1201 uint32 dataGMRId; 1202 uint32 dstScreenId; 1203 } 1204 #include "vmware_pack_end.h" 1205 SVGAOverlayUnit; 1206 1207 1208 /* 1209 * Guest display topology 1210 * 1211 * XXX: This structure is not part of the SVGA device's interface, and 1212 * doesn't really belong here. 1213 */ 1214 #define SVGA_INVALID_DISPLAY_ID ((uint32)-1) 1215 1216 typedef struct SVGADisplayTopology { 1217 uint16 displayId; 1218 uint16 isPrimary; 1219 uint32 width; 1220 uint32 height; 1221 uint32 positionX; 1222 uint32 positionY; 1223 } SVGADisplayTopology; 1224 1225 1226 /* 1227 * SVGAScreenObject -- 1228 * 1229 * This is a new way to represent a guest's multi-monitor screen or 1230 * Unity window. Screen objects are only supported if the 1231 * SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set. 1232 * 1233 * If Screen Objects are supported, they can be used to fully 1234 * replace the functionality provided by the framebuffer registers 1235 * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY. 1236 * 1237 * The screen object is a struct with guaranteed binary 1238 * compatibility. New flags can be added, and the struct may grow, 1239 * but existing fields must retain their meaning. 1240 * 1241 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of 1242 * a SVGAGuestPtr that is used to back the screen contents. This 1243 * memory must come from the GFB. The guest is not allowed to 1244 * access the memory and doing so will have undefined results. The 1245 * backing store is required to be page aligned and the size is 1246 * padded to the next page boundry. The number of pages is: 1247 * (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE 1248 * 1249 * The pitch in the backingStore is required to be at least large 1250 * enough to hold a 32bbp scanline. It is recommended that the 1251 * driver pad bytesPerLine for a potential performance win. 1252 * 1253 * The cloneCount field is treated as a hint from the guest that 1254 * the user wants this display to be cloned, countCount times. A 1255 * value of zero means no cloning should happen. 1256 */ 1257 1258 #define SVGA_SCREEN_MUST_BE_SET (1 << 0) 1259 #define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */ 1260 #define SVGA_SCREEN_IS_PRIMARY (1 << 1) 1261 #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) 1262 1263 /* 1264 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is 1265 * deactivated the base layer is defined to lose all contents and 1266 * become black. When a screen is deactivated the backing store is 1267 * optional. When set backingPtr and bytesPerLine will be ignored. 1268 */ 1269 #define SVGA_SCREEN_DEACTIVATE (1 << 3) 1270 1271 /* 1272 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set 1273 * the screen contents will be outputted as all black to the user 1274 * though the base layer contents is preserved. The screen base layer 1275 * can still be read and written to like normal though the no visible 1276 * effect will be seen by the user. When the flag is changed the 1277 * screen will be blanked or redrawn to the current contents as needed 1278 * without any extra commands from the driver. This flag only has an 1279 * effect when the screen is not deactivated. 1280 */ 1281 #define SVGA_SCREEN_BLANKING (1 << 4) 1282 1283 typedef 1284 #include "vmware_pack_begin.h" 1285 struct { 1286 uint32 structSize; /* sizeof(SVGAScreenObject) */ 1287 uint32 id; 1288 uint32 flags; 1289 struct { 1290 uint32 width; 1291 uint32 height; 1292 } size; 1293 struct { 1294 int32 x; 1295 int32 y; 1296 } root; 1297 1298 /* 1299 * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional 1300 * with SVGA_FIFO_CAP_SCREEN_OBJECT. 1301 */ 1302 SVGAGuestImage backingStore; 1303 1304 /* 1305 * The cloneCount field is treated as a hint from the guest that 1306 * the user wants this display to be cloned, cloneCount times. 1307 * 1308 * A value of zero means no cloning should happen. 1309 */ 1310 uint32 cloneCount; 1311 } 1312 #include "vmware_pack_end.h" 1313 SVGAScreenObject; 1314 1315 1316 /* 1317 * Commands in the command FIFO: 1318 * 1319 * Command IDs defined below are used for the traditional 2D FIFO 1320 * communication (not all commands are available for all versions of the 1321 * SVGA FIFO protocol). 1322 * 1323 * Note the holes in the command ID numbers: These commands have been 1324 * deprecated, and the old IDs must not be reused. 1325 * 1326 * Command IDs from 1000 to 2999 are reserved for use by the SVGA3D 1327 * protocol. 1328 * 1329 * Each command's parameters are described by the comments and 1330 * structs below. 1331 */ 1332 1333 typedef enum { 1334 SVGA_CMD_INVALID_CMD = 0, 1335 SVGA_CMD_UPDATE = 1, 1336 SVGA_CMD_RECT_COPY = 3, 1337 SVGA_CMD_RECT_ROP_COPY = 14, 1338 SVGA_CMD_DEFINE_CURSOR = 19, 1339 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 1340 SVGA_CMD_UPDATE_VERBOSE = 25, 1341 SVGA_CMD_FRONT_ROP_FILL = 29, 1342 SVGA_CMD_FENCE = 30, 1343 SVGA_CMD_ESCAPE = 33, 1344 SVGA_CMD_DEFINE_SCREEN = 34, 1345 SVGA_CMD_DESTROY_SCREEN = 35, 1346 SVGA_CMD_DEFINE_GMRFB = 36, 1347 SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37, 1348 SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38, 1349 SVGA_CMD_ANNOTATION_FILL = 39, 1350 SVGA_CMD_ANNOTATION_COPY = 40, 1351 SVGA_CMD_DEFINE_GMR2 = 41, 1352 SVGA_CMD_REMAP_GMR2 = 42, 1353 SVGA_CMD_DEAD = 43, 1354 SVGA_CMD_DEAD_2 = 44, 1355 SVGA_CMD_NOP = 45, 1356 SVGA_CMD_NOP_ERROR = 46, 1357 SVGA_CMD_MAX 1358 } SVGAFifoCmdId; 1359 1360 #define SVGA_CMD_MAX_DATASIZE (256 * 1024) 1361 #define SVGA_CMD_MAX_ARGS 64 1362 1363 1364 /* 1365 * SVGA_CMD_UPDATE -- 1366 * 1367 * This is a DMA transfer which copies from the Guest Framebuffer 1368 * (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which 1369 * intersect with the provided virtual rectangle. 1370 * 1371 * This command does not support using arbitrary guest memory as a 1372 * data source- it only works with the pre-defined GFB memory. 1373 * This command also does not support signed virtual coordinates. 1374 * If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with 1375 * negative root x/y coordinates, the negative portion of those 1376 * screens will not be reachable by this command. 1377 * 1378 * This command is not necessary when using framebuffer 1379 * traces. Traces are automatically enabled if the SVGA FIFO is 1380 * disabled, and you may explicitly enable/disable traces using 1381 * SVGA_REG_TRACES. With traces enabled, any write to the GFB will 1382 * automatically act as if a subsequent SVGA_CMD_UPDATE was issued. 1383 * 1384 * Traces and SVGA_CMD_UPDATE are the only supported ways to render 1385 * pseudocolor screen updates. The newer Screen Object commands 1386 * only support true color formats. 1387 * 1388 * Availability: 1389 * Always available. 1390 */ 1391 1392 typedef 1393 #include "vmware_pack_begin.h" 1394 struct { 1395 uint32 x; 1396 uint32 y; 1397 uint32 width; 1398 uint32 height; 1399 } 1400 #include "vmware_pack_end.h" 1401 SVGAFifoCmdUpdate; 1402 1403 1404 /* 1405 * SVGA_CMD_RECT_COPY -- 1406 * 1407 * Perform a rectangular DMA transfer from one area of the GFB to 1408 * another, and copy the result to any screens which intersect it. 1409 * 1410 * Availability: 1411 * SVGA_CAP_RECT_COPY 1412 */ 1413 1414 typedef 1415 #include "vmware_pack_begin.h" 1416 struct { 1417 uint32 srcX; 1418 uint32 srcY; 1419 uint32 destX; 1420 uint32 destY; 1421 uint32 width; 1422 uint32 height; 1423 } 1424 #include "vmware_pack_end.h" 1425 SVGAFifoCmdRectCopy; 1426 1427 1428 /* 1429 * SVGA_CMD_RECT_ROP_COPY -- 1430 * 1431 * Perform a rectangular DMA transfer from one area of the GFB to 1432 * another, and copy the result to any screens which intersect it. 1433 * The value of ROP may only be SVGA_ROP_COPY, and this command is 1434 * only supported for backwards compatibility reasons. 1435 * 1436 * Availability: 1437 * SVGA_CAP_RECT_COPY 1438 */ 1439 1440 typedef 1441 #include "vmware_pack_begin.h" 1442 struct { 1443 uint32 srcX; 1444 uint32 srcY; 1445 uint32 destX; 1446 uint32 destY; 1447 uint32 width; 1448 uint32 height; 1449 uint32 rop; 1450 } 1451 #include "vmware_pack_end.h" 1452 SVGAFifoCmdRectRopCopy; 1453 1454 1455 /* 1456 * SVGA_CMD_DEFINE_CURSOR -- 1457 * 1458 * Provide a new cursor image, as an AND/XOR mask. 1459 * 1460 * The recommended way to position the cursor overlay is by using 1461 * the SVGA_FIFO_CURSOR_* registers, supported by the 1462 * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. 1463 * 1464 * Availability: 1465 * SVGA_CAP_CURSOR 1466 */ 1467 1468 typedef 1469 #include "vmware_pack_begin.h" 1470 struct { 1471 uint32 id; /* Reserved, must be zero. */ 1472 uint32 hotspotX; 1473 uint32 hotspotY; 1474 uint32 width; 1475 uint32 height; 1476 uint32 andMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */ 1477 uint32 xorMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */ 1478 /* 1479 * Followed by scanline data for AND mask, then XOR mask. 1480 * Each scanline is padded to a 32-bit boundary. 1481 */ 1482 } 1483 #include "vmware_pack_end.h" 1484 SVGAFifoCmdDefineCursor; 1485 1486 1487 /* 1488 * SVGA_CMD_DEFINE_ALPHA_CURSOR -- 1489 * 1490 * Provide a new cursor image, in 32-bit BGRA format. 1491 * 1492 * The recommended way to position the cursor overlay is by using 1493 * the SVGA_FIFO_CURSOR_* registers, supported by the 1494 * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. 1495 * 1496 * Availability: 1497 * SVGA_CAP_ALPHA_CURSOR 1498 */ 1499 1500 typedef 1501 #include "vmware_pack_begin.h" 1502 struct { 1503 uint32 id; /* Reserved, must be zero. */ 1504 uint32 hotspotX; 1505 uint32 hotspotY; 1506 uint32 width; 1507 uint32 height; 1508 /* Followed by scanline data */ 1509 } 1510 #include "vmware_pack_end.h" 1511 SVGAFifoCmdDefineAlphaCursor; 1512 1513 1514 /* 1515 * SVGA_CMD_UPDATE_VERBOSE -- 1516 * 1517 * Just like SVGA_CMD_UPDATE, but also provide a per-rectangle 1518 * 'reason' value, an opaque cookie which is used by internal 1519 * debugging tools. Third party drivers should not use this 1520 * command. 1521 * 1522 * Availability: 1523 * SVGA_CAP_EXTENDED_FIFO 1524 */ 1525 1526 typedef 1527 #include "vmware_pack_begin.h" 1528 struct { 1529 uint32 x; 1530 uint32 y; 1531 uint32 width; 1532 uint32 height; 1533 uint32 reason; 1534 } 1535 #include "vmware_pack_end.h" 1536 SVGAFifoCmdUpdateVerbose; 1537 1538 1539 /* 1540 * SVGA_CMD_FRONT_ROP_FILL -- 1541 * 1542 * This is a hint which tells the SVGA device that the driver has 1543 * just filled a rectangular region of the GFB with a solid 1544 * color. Instead of reading these pixels from the GFB, the device 1545 * can assume that they all equal 'color'. This is primarily used 1546 * for remote desktop protocols. 1547 * 1548 * Availability: 1549 * SVGA_FIFO_CAP_ACCELFRONT 1550 */ 1551 1552 #define SVGA_ROP_COPY 0x03 1553 1554 typedef 1555 #include "vmware_pack_begin.h" 1556 struct { 1557 uint32 color; /* In the same format as the GFB */ 1558 uint32 x; 1559 uint32 y; 1560 uint32 width; 1561 uint32 height; 1562 uint32 rop; /* Must be SVGA_ROP_COPY */ 1563 } 1564 #include "vmware_pack_end.h" 1565 SVGAFifoCmdFrontRopFill; 1566 1567 1568 /* 1569 * SVGA_CMD_FENCE -- 1570 * 1571 * Insert a synchronization fence. When the SVGA device reaches 1572 * this command, it will copy the 'fence' value into the 1573 * SVGA_FIFO_FENCE register. It will also compare the fence against 1574 * SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the 1575 * SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will 1576 * raise this interrupt. 1577 * 1578 * Availability: 1579 * SVGA_FIFO_FENCE for this command, 1580 * SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL. 1581 */ 1582 1583 typedef 1584 #include "vmware_pack_begin.h" 1585 struct { 1586 uint32 fence; 1587 } 1588 #include "vmware_pack_end.h" 1589 SVGAFifoCmdFence; 1590 1591 1592 /* 1593 * SVGA_CMD_ESCAPE -- 1594 * 1595 * Send an extended or vendor-specific variable length command. 1596 * This is used for video overlay, third party plugins, and 1597 * internal debugging tools. See svga_escape.h 1598 * 1599 * Availability: 1600 * SVGA_FIFO_CAP_ESCAPE 1601 */ 1602 1603 typedef 1604 #include "vmware_pack_begin.h" 1605 struct { 1606 uint32 nsid; 1607 uint32 size; 1608 /* followed by 'size' bytes of data */ 1609 } 1610 #include "vmware_pack_end.h" 1611 SVGAFifoCmdEscape; 1612 1613 1614 /* 1615 * SVGA_CMD_DEFINE_SCREEN -- 1616 * 1617 * Define or redefine an SVGAScreenObject. See the description of 1618 * SVGAScreenObject above. The video driver is responsible for 1619 * generating new screen IDs. They should be small positive 1620 * integers. The virtual device will have an implementation 1621 * specific upper limit on the number of screen IDs 1622 * supported. Drivers are responsible for recycling IDs. The first 1623 * valid ID is zero. 1624 * 1625 * - Interaction with other registers: 1626 * 1627 * For backwards compatibility, when the GFB mode registers (WIDTH, 1628 * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device 1629 * deletes all screens other than screen #0, and redefines screen 1630 * #0 according to the specified mode. Drivers that use 1631 * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0. 1632 * 1633 * If you use screen objects, do not use the legacy multi-mon 1634 * registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*). 1635 * 1636 * Availability: 1637 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1638 */ 1639 1640 typedef 1641 #include "vmware_pack_begin.h" 1642 struct { 1643 SVGAScreenObject screen; /* Variable-length according to version */ 1644 } 1645 #include "vmware_pack_end.h" 1646 SVGAFifoCmdDefineScreen; 1647 1648 1649 /* 1650 * SVGA_CMD_DESTROY_SCREEN -- 1651 * 1652 * Destroy an SVGAScreenObject. Its ID is immediately available for 1653 * re-use. 1654 * 1655 * Availability: 1656 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1657 */ 1658 1659 typedef 1660 #include "vmware_pack_begin.h" 1661 struct { 1662 uint32 screenId; 1663 } 1664 #include "vmware_pack_end.h" 1665 SVGAFifoCmdDestroyScreen; 1666 1667 1668 /* 1669 * SVGA_CMD_DEFINE_GMRFB -- 1670 * 1671 * This command sets a piece of SVGA device state called the 1672 * Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a 1673 * piece of light-weight state which identifies the location and 1674 * format of an image in guest memory or in BAR1. The GMRFB has 1675 * an arbitrary size, and it doesn't need to match the geometry 1676 * of the GFB or any screen object. 1677 * 1678 * The GMRFB can be redefined as often as you like. You could 1679 * always use the same GMRFB, you could redefine it before 1680 * rendering from a different guest screen, or you could even 1681 * redefine it before every blit. 1682 * 1683 * There are multiple ways to use this command. The simplest way is 1684 * to use it to move the framebuffer either to elsewhere in the GFB 1685 * (BAR1) memory region, or to a user-defined GMR. This lets a 1686 * driver use a framebuffer allocated entirely out of normal system 1687 * memory, which we encourage. 1688 * 1689 * Another way to use this command is to set up a ring buffer of 1690 * updates in GFB memory. If a driver wants to ensure that no 1691 * frames are skipped by the SVGA device, it is important that the 1692 * driver not modify the source data for a blit until the device is 1693 * done processing the command. One efficient way to accomplish 1694 * this is to use a ring of small DMA buffers. Each buffer is used 1695 * for one blit, then we move on to the next buffer in the 1696 * ring. The FENCE mechanism is used to protect each buffer from 1697 * re-use until the device is finished with that buffer's 1698 * corresponding blit. 1699 * 1700 * This command does not affect the meaning of SVGA_CMD_UPDATE. 1701 * UPDATEs always occur from the legacy GFB memory area. This 1702 * command has no support for pseudocolor GMRFBs. Currently only 1703 * true-color 15, 16, and 24-bit depths are supported. Future 1704 * devices may expose capabilities for additional framebuffer 1705 * formats. 1706 * 1707 * The default GMRFB value is undefined. Drivers must always send 1708 * this command at least once before performing any blit from the 1709 * GMRFB. 1710 * 1711 * Availability: 1712 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1713 */ 1714 1715 typedef 1716 #include "vmware_pack_begin.h" 1717 struct { 1718 SVGAGuestPtr ptr; 1719 uint32 bytesPerLine; 1720 SVGAGMRImageFormat format; 1721 } 1722 #include "vmware_pack_end.h" 1723 SVGAFifoCmdDefineGMRFB; 1724 1725 1726 /* 1727 * SVGA_CMD_BLIT_GMRFB_TO_SCREEN -- 1728 * 1729 * This is a guest-to-host blit. It performs a DMA operation to 1730 * copy a rectangular region of pixels from the current GMRFB to 1731 * a ScreenObject. 1732 * 1733 * The destination coordinate may be specified relative to a 1734 * screen's origin. The provided screen ID must be valid. 1735 * 1736 * The SVGA device is guaranteed to finish reading from the GMRFB 1737 * by the time any subsequent FENCE commands are reached. 1738 * 1739 * This command consumes an annotation. See the 1740 * SVGA_CMD_ANNOTATION_* commands for details. 1741 * 1742 * Availability: 1743 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1744 */ 1745 1746 typedef 1747 #include "vmware_pack_begin.h" 1748 struct { 1749 SVGASignedPoint srcOrigin; 1750 SVGASignedRect destRect; 1751 uint32 destScreenId; 1752 } 1753 #include "vmware_pack_end.h" 1754 SVGAFifoCmdBlitGMRFBToScreen; 1755 1756 1757 /* 1758 * SVGA_CMD_BLIT_SCREEN_TO_GMRFB -- 1759 * 1760 * This is a host-to-guest blit. It performs a DMA operation to 1761 * copy a rectangular region of pixels from a single ScreenObject 1762 * back to the current GMRFB. 1763 * 1764 * The source coordinate is specified relative to a screen's 1765 * origin. The provided screen ID must be valid. If any parameters 1766 * are invalid, the resulting pixel values are undefined. 1767 * 1768 * The SVGA device is guaranteed to finish writing to the GMRFB by 1769 * the time any subsequent FENCE commands are reached. 1770 * 1771 * Availability: 1772 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1773 */ 1774 1775 typedef 1776 #include "vmware_pack_begin.h" 1777 struct { 1778 SVGASignedPoint destOrigin; 1779 SVGASignedRect srcRect; 1780 uint32 srcScreenId; 1781 } 1782 #include "vmware_pack_end.h" 1783 SVGAFifoCmdBlitScreenToGMRFB; 1784 1785 1786 /* 1787 * SVGA_CMD_ANNOTATION_FILL -- 1788 * 1789 * The annotation commands have been deprecated, should not be used 1790 * by new drivers. They used to provide performance hints to the SVGA 1791 * device about the content of screen updates, but newer SVGA devices 1792 * ignore these. 1793 * 1794 * Availability: 1795 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1796 */ 1797 1798 typedef 1799 #include "vmware_pack_begin.h" 1800 struct { 1801 SVGAColorBGRX color; 1802 } 1803 #include "vmware_pack_end.h" 1804 SVGAFifoCmdAnnotationFill; 1805 1806 1807 /* 1808 * SVGA_CMD_ANNOTATION_COPY -- 1809 * 1810 * The annotation commands have been deprecated, should not be used 1811 * by new drivers. They used to provide performance hints to the SVGA 1812 * device about the content of screen updates, but newer SVGA devices 1813 * ignore these. 1814 * 1815 * Availability: 1816 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1817 */ 1818 1819 typedef 1820 #include "vmware_pack_begin.h" 1821 struct { 1822 SVGASignedPoint srcOrigin; 1823 uint32 srcScreenId; 1824 } 1825 #include "vmware_pack_end.h" 1826 SVGAFifoCmdAnnotationCopy; 1827 1828 1829 /* 1830 * SVGA_CMD_DEFINE_GMR2 -- 1831 * 1832 * Define guest memory region v2. See the description of GMRs above. 1833 * 1834 * Availability: 1835 * SVGA_CAP_GMR2 1836 */ 1837 1838 typedef 1839 #include "vmware_pack_begin.h" 1840 struct { 1841 uint32 gmrId; 1842 uint32 numPages; 1843 } 1844 #include "vmware_pack_end.h" 1845 SVGAFifoCmdDefineGMR2; 1846 1847 1848 /* 1849 * SVGA_CMD_REMAP_GMR2 -- 1850 * 1851 * Remap guest memory region v2. See the description of GMRs above. 1852 * 1853 * This command allows guest to modify a portion of an existing GMR by 1854 * invalidating it or reassigning it to different guest physical pages. 1855 * The pages are identified by physical page number (PPN). The pages 1856 * are assumed to be pinned and valid for DMA operations. 1857 * 1858 * Description of command flags: 1859 * 1860 * SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR. 1861 * The PPN list must not overlap with the remap region (this can be 1862 * handled trivially by referencing a separate GMR). If flag is 1863 * disabled, PPN list is appended to SVGARemapGMR command. 1864 * 1865 * SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise 1866 * it is in PPN32 format. 1867 * 1868 * SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry. 1869 * A single PPN can be used to invalidate a portion of a GMR or 1870 * map it to to a single guest scratch page. 1871 * 1872 * Availability: 1873 * SVGA_CAP_GMR2 1874 */ 1875 1876 typedef enum { 1877 SVGA_REMAP_GMR2_PPN32 = 0, 1878 SVGA_REMAP_GMR2_VIA_GMR = (1 << 0), 1879 SVGA_REMAP_GMR2_PPN64 = (1 << 1), 1880 SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2), 1881 } SVGARemapGMR2Flags; 1882 1883 typedef 1884 #include "vmware_pack_begin.h" 1885 struct { 1886 uint32 gmrId; 1887 SVGARemapGMR2Flags flags; 1888 uint32 offsetPages; /* offset in pages to begin remap */ 1889 uint32 numPages; /* number of pages to remap */ 1890 /* 1891 * Followed by additional data depending on SVGARemapGMR2Flags. 1892 * 1893 * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows. 1894 * Otherwise an array of page descriptors in PPN32 or PPN64 format 1895 * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag 1896 * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry. 1897 */ 1898 } 1899 #include "vmware_pack_end.h" 1900 SVGAFifoCmdRemapGMR2; 1901 1902 1903 /* 1904 * Size of SVGA device memory such as frame buffer and FIFO. 1905 */ 1906 #define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) /* bytes */ 1907 #define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024) 1908 #define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024) 1909 #define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024) 1910 #define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024) 1911 #define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024) 1912 #define SVGA_GRAPHICS_MEMORY_KB_MAX (2 * 1024 * 1024) 1913 #define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024) 1914 1915 #define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */ 1916 1917 /* 1918 * To simplify autoDetect display configuration, support a minimum of 1919 * two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated: 1920 * numDisplays = 2 1921 * maxWidth = numDisplay * 1920 = 3840 1922 * maxHeight = rotated width of single monitor = 1920 1923 * vramSize = maxWidth * maxHeight * 4 = 29491200 1924 */ 1925 #define SVGA_VRAM_SIZE_AUTODETECT (32 * 1024 * 1024) 1926 1927 #if defined(VMX86_SERVER) 1928 #define SVGA_VRAM_SIZE (4 * 1024 * 1024) 1929 #define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024) 1930 #define SVGA_FIFO_SIZE (256 * 1024) 1931 #define SVGA_FIFO_SIZE_3D (516 * 1024) 1932 #define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024) 1933 #define SVGA_AUTODETECT_DEFAULT FALSE 1934 #else 1935 #define SVGA_VRAM_SIZE (16 * 1024 * 1024) 1936 #define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE 1937 #define SVGA_FIFO_SIZE (2 * 1024 * 1024) 1938 #define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE 1939 #define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024) 1940 #define SVGA_AUTODETECT_DEFAULT TRUE 1941 #endif 1942 1943 #define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024) 1944 #define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024) 1945 1946 #endif 1947