1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /************************************************************************** 3 * 4 * Copyright 2008-2015 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 /* 29 * svga3d_surfacedefs.h -- 30 * 31 * Surface definitions and inlineable utilities for SVGA3d. 32 */ 33 34 #ifndef _SVGA3D_SURFACEDEFS_H_ 35 #define _SVGA3D_SURFACEDEFS_H_ 36 37 #define INCLUDE_ALLOW_USERLEVEL 38 #define INCLUDE_ALLOW_MODULE 39 #include "includeCheck.h" 40 41 #include <linux/kernel.h> 42 #include <drm/vmwgfx_drm.h> 43 44 #include "svga3d_reg.h" 45 46 #define surf_size_struct struct drm_vmw_size 47 48 /* 49 * enum svga3d_block_desc - describes generic properties about formats. 50 */ 51 enum svga3d_block_desc { 52 /* Nothing special can be said about this format. */ 53 SVGA3DBLOCKDESC_NONE = 0, 54 55 /* Format contains Blue/U data */ 56 SVGA3DBLOCKDESC_BLUE = 1 << 0, 57 SVGA3DBLOCKDESC_W = 1 << 0, 58 SVGA3DBLOCKDESC_BUMP_L = 1 << 0, 59 60 /* Format contains Green/V data */ 61 SVGA3DBLOCKDESC_GREEN = 1 << 1, 62 SVGA3DBLOCKDESC_V = 1 << 1, 63 64 /* Format contains Red/W/Luminance data */ 65 SVGA3DBLOCKDESC_RED = 1 << 2, 66 SVGA3DBLOCKDESC_U = 1 << 2, 67 SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, 68 69 /* Format contains Alpha/Q data */ 70 SVGA3DBLOCKDESC_ALPHA = 1 << 3, 71 SVGA3DBLOCKDESC_Q = 1 << 3, 72 73 /* Format is a buffer */ 74 SVGA3DBLOCKDESC_BUFFER = 1 << 4, 75 76 /* Format is compressed */ 77 SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, 78 79 /* Format uses IEEE floating point */ 80 SVGA3DBLOCKDESC_FP = 1 << 6, 81 82 /* Three separate blocks store data. */ 83 SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7, 84 85 /* 2 planes of Y, UV, e.g., NV12. */ 86 SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 8, 87 88 /* 3 planes of separate Y, U, V, e.g., YV12. */ 89 SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 9, 90 91 /* Block with a stencil channel */ 92 SVGA3DBLOCKDESC_STENCIL = 1 << 11, 93 94 /* Typeless format */ 95 SVGA3DBLOCKDESC_TYPELESS = 1 << 12, 96 97 /* Channels are signed integers */ 98 SVGA3DBLOCKDESC_SINT = 1 << 13, 99 100 /* Channels are unsigned integers */ 101 SVGA3DBLOCKDESC_UINT = 1 << 14, 102 103 /* Channels are normalized (when sampling) */ 104 SVGA3DBLOCKDESC_NORM = 1 << 15, 105 106 /* Channels are in SRGB */ 107 SVGA3DBLOCKDESC_SRGB = 1 << 16, 108 109 /* Shared exponent */ 110 SVGA3DBLOCKDESC_EXP = 1 << 17, 111 112 /* Format contains color data. */ 113 SVGA3DBLOCKDESC_COLOR = 1 << 18, 114 /* Format contains depth data. */ 115 SVGA3DBLOCKDESC_DEPTH = 1 << 19, 116 /* Format contains bump data. */ 117 SVGA3DBLOCKDESC_BUMP = 1 << 20, 118 119 /* Format contains YUV video data. */ 120 SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21, 121 122 /* For mixed unsigned/signed formats. */ 123 SVGA3DBLOCKDESC_MIXED = 1 << 22, 124 125 /* For distingushing CxV8U8. */ 126 SVGA3DBLOCKDESC_CX = 1 << 23, 127 128 /* Different compressed format groups. */ 129 SVGA3DBLOCKDESC_BC1 = 1 << 24, 130 SVGA3DBLOCKDESC_BC2 = 1 << 25, 131 SVGA3DBLOCKDESC_BC3 = 1 << 26, 132 SVGA3DBLOCKDESC_BC4 = 1 << 27, 133 SVGA3DBLOCKDESC_BC5 = 1 << 28, 134 SVGA3DBLOCKDESC_BC6H = 1 << 29, 135 SVGA3DBLOCKDESC_BC7 = 1 << 30, 136 137 SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA | 138 SVGA3DBLOCKDESC_UINT | 139 SVGA3DBLOCKDESC_COLOR, 140 SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT | 141 SVGA3DBLOCKDESC_NORM, 142 SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED | 143 SVGA3DBLOCKDESC_UINT | 144 SVGA3DBLOCKDESC_COLOR, 145 SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT | 146 SVGA3DBLOCKDESC_NORM, 147 SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED | 148 SVGA3DBLOCKDESC_SINT | 149 SVGA3DBLOCKDESC_COLOR, 150 SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT | 151 SVGA3DBLOCKDESC_NORM, 152 SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN | 153 SVGA3DBLOCKDESC_UINT | 154 SVGA3DBLOCKDESC_COLOR, 155 SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED | 156 SVGA3DBLOCKDESC_GREEN | 157 SVGA3DBLOCKDESC_UINT | 158 SVGA3DBLOCKDESC_COLOR, 159 SVGA3DBLOCKDESC_RG_UNORM = SVGA3DBLOCKDESC_RG_UINT | 160 SVGA3DBLOCKDESC_NORM, 161 SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED | 162 SVGA3DBLOCKDESC_GREEN | 163 SVGA3DBLOCKDESC_SINT | 164 SVGA3DBLOCKDESC_COLOR, 165 SVGA3DBLOCKDESC_RG_SNORM = SVGA3DBLOCKDESC_RG_SINT | 166 SVGA3DBLOCKDESC_NORM, 167 SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED | 168 SVGA3DBLOCKDESC_GREEN | 169 SVGA3DBLOCKDESC_BLUE | 170 SVGA3DBLOCKDESC_UINT | 171 SVGA3DBLOCKDESC_COLOR, 172 SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED | 173 SVGA3DBLOCKDESC_GREEN | 174 SVGA3DBLOCKDESC_BLUE | 175 SVGA3DBLOCKDESC_SINT | 176 SVGA3DBLOCKDESC_COLOR, 177 SVGA3DBLOCKDESC_RGB_UNORM = SVGA3DBLOCKDESC_RGB_UINT | 178 SVGA3DBLOCKDESC_NORM, 179 SVGA3DBLOCKDESC_RGB_UNORM_SRGB = SVGA3DBLOCKDESC_RGB_UNORM | 180 SVGA3DBLOCKDESC_SRGB, 181 SVGA3DBLOCKDESC_RGBA_UINT = SVGA3DBLOCKDESC_RED | 182 SVGA3DBLOCKDESC_GREEN | 183 SVGA3DBLOCKDESC_BLUE | 184 SVGA3DBLOCKDESC_ALPHA | 185 SVGA3DBLOCKDESC_UINT | 186 SVGA3DBLOCKDESC_COLOR, 187 SVGA3DBLOCKDESC_RGBA_UNORM = SVGA3DBLOCKDESC_RGBA_UINT | 188 SVGA3DBLOCKDESC_NORM, 189 SVGA3DBLOCKDESC_RGBA_UNORM_SRGB = SVGA3DBLOCKDESC_RGBA_UNORM | 190 SVGA3DBLOCKDESC_SRGB, 191 SVGA3DBLOCKDESC_RGBA_SINT = SVGA3DBLOCKDESC_RED | 192 SVGA3DBLOCKDESC_GREEN | 193 SVGA3DBLOCKDESC_BLUE | 194 SVGA3DBLOCKDESC_ALPHA | 195 SVGA3DBLOCKDESC_SINT | 196 SVGA3DBLOCKDESC_COLOR, 197 SVGA3DBLOCKDESC_RGBA_SNORM = SVGA3DBLOCKDESC_RGBA_SINT | 198 SVGA3DBLOCKDESC_NORM, 199 SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED | 200 SVGA3DBLOCKDESC_GREEN | 201 SVGA3DBLOCKDESC_BLUE | 202 SVGA3DBLOCKDESC_ALPHA | 203 SVGA3DBLOCKDESC_FP | 204 SVGA3DBLOCKDESC_COLOR, 205 SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U | 206 SVGA3DBLOCKDESC_V | 207 SVGA3DBLOCKDESC_BUMP, 208 SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV | 209 SVGA3DBLOCKDESC_BUMP_L | 210 SVGA3DBLOCKDESC_MIXED | 211 SVGA3DBLOCKDESC_BUMP, 212 SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV | 213 SVGA3DBLOCKDESC_W | 214 SVGA3DBLOCKDESC_BUMP, 215 SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW | 216 SVGA3DBLOCKDESC_ALPHA | 217 SVGA3DBLOCKDESC_MIXED | 218 SVGA3DBLOCKDESC_BUMP, 219 SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U | 220 SVGA3DBLOCKDESC_V | 221 SVGA3DBLOCKDESC_W | 222 SVGA3DBLOCKDESC_Q | 223 SVGA3DBLOCKDESC_BUMP, 224 SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE | 225 SVGA3DBLOCKDESC_UINT | 226 SVGA3DBLOCKDESC_NORM | 227 SVGA3DBLOCKDESC_COLOR, 228 SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE | 229 SVGA3DBLOCKDESC_ALPHA | 230 SVGA3DBLOCKDESC_UINT | 231 SVGA3DBLOCKDESC_NORM | 232 SVGA3DBLOCKDESC_COLOR, 233 SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED | 234 SVGA3DBLOCKDESC_FP | 235 SVGA3DBLOCKDESC_COLOR, 236 SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP | 237 SVGA3DBLOCKDESC_GREEN | 238 SVGA3DBLOCKDESC_COLOR, 239 SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP | 240 SVGA3DBLOCKDESC_BLUE | 241 SVGA3DBLOCKDESC_COLOR, 242 SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO | 243 SVGA3DBLOCKDESC_COLOR, 244 SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA | 245 SVGA3DBLOCKDESC_YUV_VIDEO | 246 SVGA3DBLOCKDESC_COLOR, 247 SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED | 248 SVGA3DBLOCKDESC_GREEN | 249 SVGA3DBLOCKDESC_BLUE | 250 SVGA3DBLOCKDESC_EXP | 251 SVGA3DBLOCKDESC_COLOR, 252 253 SVGA3DBLOCKDESC_COMP_TYPELESS = SVGA3DBLOCKDESC_COMPRESSED | 254 SVGA3DBLOCKDESC_TYPELESS, 255 SVGA3DBLOCKDESC_COMP_UNORM = SVGA3DBLOCKDESC_COMPRESSED | 256 SVGA3DBLOCKDESC_UINT | 257 SVGA3DBLOCKDESC_NORM | 258 SVGA3DBLOCKDESC_COLOR, 259 SVGA3DBLOCKDESC_COMP_SNORM = SVGA3DBLOCKDESC_COMPRESSED | 260 SVGA3DBLOCKDESC_SINT | 261 SVGA3DBLOCKDESC_NORM | 262 SVGA3DBLOCKDESC_COLOR, 263 SVGA3DBLOCKDESC_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_COMP_UNORM | 264 SVGA3DBLOCKDESC_SRGB, 265 SVGA3DBLOCKDESC_BC1_COMP_TYPELESS = SVGA3DBLOCKDESC_BC1 | 266 SVGA3DBLOCKDESC_COMP_TYPELESS, 267 SVGA3DBLOCKDESC_BC1_COMP_UNORM = SVGA3DBLOCKDESC_BC1 | 268 SVGA3DBLOCKDESC_COMP_UNORM, 269 SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC1_COMP_UNORM | 270 SVGA3DBLOCKDESC_SRGB, 271 SVGA3DBLOCKDESC_BC2_COMP_TYPELESS = SVGA3DBLOCKDESC_BC2 | 272 SVGA3DBLOCKDESC_COMP_TYPELESS, 273 SVGA3DBLOCKDESC_BC2_COMP_UNORM = SVGA3DBLOCKDESC_BC2 | 274 SVGA3DBLOCKDESC_COMP_UNORM, 275 SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC2_COMP_UNORM | 276 SVGA3DBLOCKDESC_SRGB, 277 SVGA3DBLOCKDESC_BC3_COMP_TYPELESS = SVGA3DBLOCKDESC_BC3 | 278 SVGA3DBLOCKDESC_COMP_TYPELESS, 279 SVGA3DBLOCKDESC_BC3_COMP_UNORM = SVGA3DBLOCKDESC_BC3 | 280 SVGA3DBLOCKDESC_COMP_UNORM, 281 SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC3_COMP_UNORM | 282 SVGA3DBLOCKDESC_SRGB, 283 SVGA3DBLOCKDESC_BC4_COMP_TYPELESS = SVGA3DBLOCKDESC_BC4 | 284 SVGA3DBLOCKDESC_COMP_TYPELESS, 285 SVGA3DBLOCKDESC_BC4_COMP_UNORM = SVGA3DBLOCKDESC_BC4 | 286 SVGA3DBLOCKDESC_COMP_UNORM, 287 SVGA3DBLOCKDESC_BC4_COMP_SNORM = SVGA3DBLOCKDESC_BC4 | 288 SVGA3DBLOCKDESC_COMP_SNORM, 289 SVGA3DBLOCKDESC_BC5_COMP_TYPELESS = SVGA3DBLOCKDESC_BC5 | 290 SVGA3DBLOCKDESC_COMP_TYPELESS, 291 SVGA3DBLOCKDESC_BC5_COMP_UNORM = SVGA3DBLOCKDESC_BC5 | 292 SVGA3DBLOCKDESC_COMP_UNORM, 293 SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 | 294 SVGA3DBLOCKDESC_COMP_SNORM, 295 SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS = SVGA3DBLOCKDESC_BC6H | 296 SVGA3DBLOCKDESC_COMP_TYPELESS, 297 SVGA3DBLOCKDESC_BC6H_COMP_UF16 = SVGA3DBLOCKDESC_BC6H | 298 SVGA3DBLOCKDESC_COMPRESSED, 299 SVGA3DBLOCKDESC_BC6H_COMP_SF16 = SVGA3DBLOCKDESC_BC6H | 300 SVGA3DBLOCKDESC_COMPRESSED, 301 SVGA3DBLOCKDESC_BC7_COMP_TYPELESS = SVGA3DBLOCKDESC_BC7 | 302 SVGA3DBLOCKDESC_COMP_TYPELESS, 303 SVGA3DBLOCKDESC_BC7_COMP_UNORM = SVGA3DBLOCKDESC_BC7 | 304 SVGA3DBLOCKDESC_COMP_UNORM, 305 SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC7_COMP_UNORM | 306 SVGA3DBLOCKDESC_SRGB, 307 308 SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO | 309 SVGA3DBLOCKDESC_PLANAR_YUV | 310 SVGA3DBLOCKDESC_2PLANAR_YUV | 311 SVGA3DBLOCKDESC_COLOR, 312 SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_YUV_VIDEO | 313 SVGA3DBLOCKDESC_PLANAR_YUV | 314 SVGA3DBLOCKDESC_3PLANAR_YUV | 315 SVGA3DBLOCKDESC_COLOR, 316 317 SVGA3DBLOCKDESC_DEPTH_UINT = SVGA3DBLOCKDESC_DEPTH | 318 SVGA3DBLOCKDESC_UINT, 319 SVGA3DBLOCKDESC_DEPTH_UNORM = SVGA3DBLOCKDESC_DEPTH_UINT | 320 SVGA3DBLOCKDESC_NORM, 321 SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH | 322 SVGA3DBLOCKDESC_STENCIL, 323 SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH | 324 SVGA3DBLOCKDESC_STENCIL | 325 SVGA3DBLOCKDESC_UINT, 326 SVGA3DBLOCKDESC_DS_UNORM = SVGA3DBLOCKDESC_DS_UINT | 327 SVGA3DBLOCKDESC_NORM, 328 SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH | 329 SVGA3DBLOCKDESC_FP, 330 331 SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV | 332 SVGA3DBLOCKDESC_UINT, 333 SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV | 334 SVGA3DBLOCKDESC_SINT | 335 SVGA3DBLOCKDESC_NORM, 336 SVGA3DBLOCKDESC_UVCX_SNORM = SVGA3DBLOCKDESC_UV_SNORM | 337 SVGA3DBLOCKDESC_CX, 338 SVGA3DBLOCKDESC_UVWQ_SNORM = SVGA3DBLOCKDESC_UVWQ | 339 SVGA3DBLOCKDESC_SINT | 340 SVGA3DBLOCKDESC_NORM, 341 }; 342 343 struct svga3d_channel_def { 344 union { 345 u8 blue; 346 u8 w_bump; 347 u8 l_bump; 348 u8 uv_video; 349 u8 u_video; 350 }; 351 union { 352 u8 green; 353 u8 stencil; 354 u8 v_bump; 355 u8 v_video; 356 }; 357 union { 358 u8 red; 359 u8 u_bump; 360 u8 luminance; 361 u8 y_video; 362 u8 depth; 363 u8 data; 364 }; 365 union { 366 u8 alpha; 367 u8 q_bump; 368 u8 exp; 369 }; 370 }; 371 372 /* 373 * struct svga3d_surface_desc - describes the actual pixel data. 374 * 375 * @format: Format 376 * @block_desc: Block description 377 * @block_size: Dimensions in pixels of a block 378 * @bytes_per_block: Size of block in bytes 379 * @pitch_bytes_per_block: Size of a block in bytes for purposes of pitch 380 * @bit_depth: Channel bit depths 381 * @bit_offset: Channel bit masks (in bits offset from the start of the pointer) 382 */ 383 struct svga3d_surface_desc { 384 SVGA3dSurfaceFormat format; 385 enum svga3d_block_desc block_desc; 386 387 surf_size_struct block_size; 388 u32 bytes_per_block; 389 u32 pitch_bytes_per_block; 390 391 struct svga3d_channel_def bit_depth; 392 struct svga3d_channel_def bit_offset; 393 }; 394 395 static const struct svga3d_surface_desc svga3d_surface_descs[] = { 396 {SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE, 397 {1, 1, 1}, 0, 0, 398 {{0}, {0}, {0}, {0}}, 399 {{0}, {0}, {0}, {0}}}, 400 401 {SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB_UNORM, 402 {1, 1, 1}, 4, 4, 403 {{8}, {8}, {8}, {0}}, 404 {{0}, {8}, {16}, {24}}}, 405 406 {SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA_UNORM, 407 {1, 1, 1}, 4, 4, 408 {{8}, {8}, {8}, {8}}, 409 {{0}, {8}, {16}, {24}}}, 410 411 {SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB_UNORM, 412 {1, 1, 1}, 2, 2, 413 {{5}, {6}, {5}, {0}}, 414 {{0}, {5}, {11}, {0}}}, 415 416 {SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB_UNORM, 417 {1, 1, 1}, 2, 2, 418 {{5}, {5}, {5}, {0}}, 419 {{0}, {5}, {10}, {0}}}, 420 421 {SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA_UNORM, 422 {1, 1, 1}, 2, 2, 423 {{5}, {5}, {5}, {1}}, 424 {{0}, {5}, {10}, {15}}}, 425 426 {SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA_UNORM, 427 {1, 1, 1}, 2, 2, 428 {{4}, {4}, {4}, {4}}, 429 {{0}, {4}, {8}, {12}}}, 430 431 {SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH_UNORM, 432 {1, 1, 1}, 4, 4, 433 {{0}, {0}, {32}, {0}}, 434 {{0}, {0}, {0}, {0}}}, 435 436 {SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH_UNORM, 437 {1, 1, 1}, 2, 2, 438 {{0}, {0}, {16}, {0}}, 439 {{0}, {0}, {0}, {0}}}, 440 441 {SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS_UNORM, 442 {1, 1, 1}, 4, 4, 443 {{0}, {8}, {24}, {0}}, 444 {{0}, {0}, {8}, {0}}}, 445 446 {SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS_UNORM, 447 {1, 1, 1}, 2, 2, 448 {{0}, {1}, {15}, {0}}, 449 {{0}, {0}, {1}, {0}}}, 450 451 {SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_L_UNORM, 452 {1, 1, 1}, 1, 1, 453 {{0}, {0}, {8}, {0}}, 454 {{0}, {0}, {0}, {0}}}, 455 456 {SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA_UNORM, 457 {1, 1, 1}, 1, 1, 458 {{0}, {0}, {4}, {4}}, 459 {{0}, {0}, {0}, {4}}}, 460 461 {SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_L_UNORM, 462 {1, 1, 1}, 2, 2, 463 {{0}, {0}, {16}, {0}}, 464 {{0}, {0}, {0}, {0}}}, 465 466 {SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA_UNORM, 467 {1, 1, 1}, 2, 2, 468 {{0}, {0}, {8}, {8}}, 469 {{0}, {0}, {0}, {8}}}, 470 471 {SVGA3D_DXT1, SVGA3DBLOCKDESC_BC1_COMP_UNORM, 472 {4, 4, 1}, 8, 8, 473 {{0}, {0}, {64}, {0}}, 474 {{0}, {0}, {0}, {0}}}, 475 476 {SVGA3D_DXT2, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 477 {4, 4, 1}, 16, 16, 478 {{0}, {0}, {128}, {0}}, 479 {{0}, {0}, {0}, {0}}}, 480 481 {SVGA3D_DXT3, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 482 {4, 4, 1}, 16, 16, 483 {{0}, {0}, {128}, {0}}, 484 {{0}, {0}, {0}, {0}}}, 485 486 {SVGA3D_DXT4, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 487 {4, 4, 1}, 16, 16, 488 {{0}, {0}, {128}, {0}}, 489 {{0}, {0}, {0}, {0}}}, 490 491 {SVGA3D_DXT5, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 492 {4, 4, 1}, 16, 16, 493 {{0}, {0}, {128}, {0}}, 494 {{0}, {0}, {0}, {0}}}, 495 496 {SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV_SNORM, 497 {1, 1, 1}, 2, 2, 498 {{0}, {8}, {8}, {0}}, 499 {{0}, {8}, {0}, {0}}}, 500 501 {SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL, 502 {1, 1, 1}, 2, 2, 503 {{6}, {5}, {5}, {0}}, 504 {{10}, {5}, {0}, {0}}}, 505 506 {SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL, 507 {1, 1, 1}, 4, 4, 508 {{8}, {8}, {8}, {0}}, 509 {{16}, {8}, {0}, {0}}}, 510 511 {SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_NONE, 512 {1, 1, 1}, 3, 3, 513 {{8}, {8}, {8}, {0}}, 514 {{16}, {8}, {0}, {0}}}, 515 516 {SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP, 517 {1, 1, 1}, 8, 8, 518 {{16}, {16}, {16}, {16}}, 519 {{32}, {16}, {0}, {48}}}, 520 521 {SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP, 522 {1, 1, 1}, 16, 16, 523 {{32}, {32}, {32}, {32}}, 524 {{64}, {32}, {0}, {96}}}, 525 526 {SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA_UNORM, 527 {1, 1, 1}, 4, 4, 528 {{10}, {10}, {10}, {2}}, 529 {{0}, {10}, {20}, {30}}}, 530 531 {SVGA3D_V8U8, SVGA3DBLOCKDESC_UV_SNORM, 532 {1, 1, 1}, 2, 2, 533 {{0}, {8}, {8}, {0}}, 534 {{0}, {8}, {0}, {0}}}, 535 536 {SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ_SNORM, 537 {1, 1, 1}, 4, 4, 538 {{8}, {8}, {8}, {8}}, 539 {{16}, {8}, {0}, {24}}}, 540 541 {SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UVCX_SNORM, 542 {1, 1, 1}, 2, 2, 543 {{0}, {8}, {8}, {0}}, 544 {{0}, {8}, {0}, {0}}}, 545 546 {SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL, 547 {1, 1, 1}, 4, 4, 548 {{8}, {8}, {8}, {0}}, 549 {{16}, {8}, {0}, {0}}}, 550 551 {SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA, 552 {1, 1, 1}, 4, 4, 553 {{10}, {10}, {10}, {2}}, 554 {{20}, {10}, {0}, {30}}}, 555 556 {SVGA3D_ALPHA8, SVGA3DBLOCKDESC_A_UNORM, 557 {1, 1, 1}, 1, 1, 558 {{0}, {0}, {0}, {8}}, 559 {{0}, {0}, {0}, {0}}}, 560 561 {SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP, 562 {1, 1, 1}, 2, 2, 563 {{0}, {0}, {16}, {0}}, 564 {{0}, {0}, {0}, {0}}}, 565 566 {SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP, 567 {1, 1, 1}, 4, 4, 568 {{0}, {0}, {32}, {0}}, 569 {{0}, {0}, {0}, {0}}}, 570 571 {SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP, 572 {1, 1, 1}, 4, 4, 573 {{0}, {16}, {16}, {0}}, 574 {{0}, {16}, {0}, {0}}}, 575 576 {SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP, 577 {1, 1, 1}, 8, 8, 578 {{0}, {32}, {32}, {0}}, 579 {{0}, {32}, {0}, {0}}}, 580 581 {SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER, 582 {1, 1, 1}, 1, 1, 583 {{0}, {0}, {8}, {0}}, 584 {{0}, {0}, {0}, {0}}}, 585 586 {SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH_UNORM, 587 {1, 1, 1}, 4, 4, 588 {{0}, {0}, {24}, {0}}, 589 {{0}, {0}, {8}, {0}}}, 590 591 {SVGA3D_V16U16, SVGA3DBLOCKDESC_UV_SNORM, 592 {1, 1, 1}, 4, 4, 593 {{0}, {16}, {16}, {0}}, 594 {{0}, {16}, {0}, {0}}}, 595 596 {SVGA3D_G16R16, SVGA3DBLOCKDESC_RG_UNORM, 597 {1, 1, 1}, 4, 4, 598 {{0}, {16}, {16}, {0}}, 599 {{0}, {16}, {0}, {0}}}, 600 601 {SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA_UNORM, 602 {1, 1, 1}, 8, 8, 603 {{16}, {16}, {16}, {16}}, 604 {{32}, {16}, {0}, {48}}}, 605 606 {SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV, 607 {2, 1, 1}, 4, 4, 608 {{8}, {0}, {8}, {0}}, 609 {{0}, {0}, {8}, {0}}}, 610 611 {SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV, 612 {2, 1, 1}, 4, 4, 613 {{8}, {0}, {8}, {0}}, 614 {{8}, {0}, {0}, {0}}}, 615 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{SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP, 1022 {1, 1, 1}, 8, 8, 1023 {{0}, {32}, {32}, {0}}, 1024 {{0}, {32}, {0}, {0}}}, 1025 1026 {SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1027 {1, 1, 1}, 4, 4, 1028 {{10}, {10}, {10}, {2}}, 1029 {{20}, {10}, {0}, {30}}}, 1030 1031 {SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM, 1032 {1, 1, 1}, 4, 4, 1033 {{8}, {8}, {8}, {8}}, 1034 {{16}, {8}, {0}, {24}}}, 1035 1036 {SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP, 1037 {1, 1, 1}, 4, 4, 1038 {{0}, {16}, {16}, {0}}, 1039 {{0}, {16}, {0}, {0}}}, 1040 1041 {SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG_UNORM, 1042 {1, 1, 1}, 4, 4, 1043 {{0}, {16}, {16}, {0}}, 1044 {{0}, {16}, {0}, {0}}}, 1045 1046 {SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG_SNORM, 1047 {1, 1, 1}, 4, 4, 1048 {{0}, {16}, {16}, {0}}, 1049 {{0}, {16}, {0}, {0}}}, 1050 1051 {SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP, 1052 {1, 1, 1}, 4, 4, 1053 {{0}, {0}, {32}, {0}}, 1054 {{0}, {0}, {0}, {0}}}, 1055 1056 {SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG_SNORM, 1057 {1, 1, 1}, 2, 2, 1058 {{0}, {8}, {8}, {0}}, 1059 {{0}, {8}, {0}, {0}}}, 1060 1061 {SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP, 1062 {1, 1, 1}, 2, 2, 1063 {{0}, {0}, {16}, {0}}, 1064 {{0}, {0}, {0}, {0}}}, 1065 1066 {SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH_UNORM, 1067 {1, 1, 1}, 2, 2, 1068 {{0}, {0}, {16}, {0}}, 1069 {{0}, {0}, {0}, {0}}}, 1070 1071 {SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_A_UNORM, 1072 {1, 1, 1}, 1, 1, 1073 {{0}, {0}, {0}, {8}}, 1074 {{0}, {0}, {0}, {0}}}, 1075 1076 {SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_BC1_COMP_UNORM, 1077 {4, 4, 1}, 8, 8, 1078 {{0}, {0}, {64}, {0}}, 1079 {{0}, {0}, {0}, {0}}}, 1080 1081 {SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 1082 {4, 4, 1}, 16, 16, 1083 {{0}, {0}, {128}, {0}}, 1084 {{0}, {0}, {0}, {0}}}, 1085 1086 {SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 1087 {4, 4, 1}, 16, 16, 1088 {{0}, {0}, {128}, {0}}, 1089 {{0}, {0}, {0}, {0}}}, 1090 1091 {SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB_UNORM, 1092 {1, 1, 1}, 2, 2, 1093 {{5}, {6}, {5}, {0}}, 1094 {{0}, {5}, {11}, {0}}}, 1095 1096 {SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1097 {1, 1, 1}, 2, 2, 1098 {{5}, {5}, {5}, {1}}, 1099 {{0}, {5}, {10}, {15}}}, 1100 1101 {SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1102 {1, 1, 1}, 4, 4, 1103 {{8}, {8}, {8}, {8}}, 1104 {{0}, {8}, {16}, {24}}}, 1105 1106 {SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB_UNORM, 1107 {1, 1, 1}, 4, 4, 1108 {{8}, {8}, {8}, {0}}, 1109 {{0}, {8}, {16}, {24}}}, 1110 1111 {SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_BC4_COMP_UNORM, 1112 {4, 4, 1}, 8, 8, 1113 {{0}, {0}, {64}, {0}}, 1114 {{0}, {0}, {0}, {0}}}, 1115 1116 {SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_BC5_COMP_UNORM, 1117 {4, 4, 1}, 16, 16, 1118 {{0}, {0}, {128}, {0}}, 1119 {{0}, {0}, {0}, {0}}}, 1120 1121 {SVGA3D_B4G4R4A4_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1122 {1, 1, 1}, 2, 2, 1123 {{4}, {4}, {4}, {4}}, 1124 {{0}, {4}, {8}, {12}}}, 1125 1126 {SVGA3D_BC6H_TYPELESS, SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS, 1127 {4, 4, 1}, 16, 16, 1128 {{0}, {0}, {128}, {0}}, 1129 {{0}, {0}, {0}, {0}}}, 1130 1131 {SVGA3D_BC6H_UF16, SVGA3DBLOCKDESC_BC6H_COMP_UF16, 1132 {4, 4, 1}, 16, 16, 1133 {{0}, {0}, {128}, {0}}, 1134 {{0}, {0}, {0}, {0}}}, 1135 1136 {SVGA3D_BC6H_SF16, SVGA3DBLOCKDESC_BC6H_COMP_SF16, 1137 {4, 4, 1}, 16, 16, 1138 {{0}, {0}, {128}, {0}}, 1139 {{0}, {0}, {0}, {0}}}, 1140 1141 {SVGA3D_BC7_TYPELESS, SVGA3DBLOCKDESC_BC7_COMP_TYPELESS, 1142 {4, 4, 1}, 16, 16, 1143 {{0}, {0}, {128}, {0}}, 1144 {{0}, {0}, {0}, {0}}}, 1145 1146 {SVGA3D_BC7_UNORM, SVGA3DBLOCKDESC_BC7_COMP_UNORM, 1147 {4, 4, 1}, 16, 16, 1148 {{0}, {0}, {128}, {0}}, 1149 {{0}, {0}, {0}, {0}}}, 1150 1151 {SVGA3D_BC7_UNORM_SRGB, SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB, 1152 {4, 4, 1}, 16, 16, 1153 {{0}, {0}, {128}, {0}}, 1154 {{0}, {0}, {0}, {0}}}, 1155 1156 {SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV, 1157 {1, 1, 1}, 4, 4, 1158 {{8}, {8}, {8}, {8}}, 1159 {{0}, {8}, {16}, {24}}}, 1160 }; 1161 1162 static inline u32 clamped_umul32(u32 a, u32 b) 1163 { 1164 uint64_t tmp = (uint64_t) a*b; 1165 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; 1166 } 1167 1168 /** 1169 * svga3dsurface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the 1170 * given format. 1171 */ 1172 static inline const struct svga3d_surface_desc * 1173 svga3dsurface_get_desc(SVGA3dSurfaceFormat format) 1174 { 1175 if (format < ARRAY_SIZE(svga3d_surface_descs)) 1176 return &svga3d_surface_descs[format]; 1177 1178 return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID]; 1179 } 1180 1181 /** 1182 * svga3dsurface_get_mip_size - Given a base level size and the mip level, 1183 * compute the size of the mip level. 1184 */ 1185 static inline surf_size_struct 1186 svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level) 1187 { 1188 surf_size_struct size; 1189 1190 size.width = max_t(u32, base_level.width >> mip_level, 1); 1191 size.height = max_t(u32, base_level.height >> mip_level, 1); 1192 size.depth = max_t(u32, base_level.depth >> mip_level, 1); 1193 size.pad64 = 0; 1194 1195 return size; 1196 } 1197 1198 static inline void 1199 svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc, 1200 const surf_size_struct *pixel_size, 1201 surf_size_struct *block_size) 1202 { 1203 block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width, 1204 desc->block_size.width); 1205 block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height, 1206 desc->block_size.height); 1207 block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth, 1208 desc->block_size.depth); 1209 } 1210 1211 static inline bool 1212 svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc) 1213 { 1214 return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0; 1215 } 1216 1217 static inline u32 1218 svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc, 1219 const surf_size_struct *size) 1220 { 1221 u32 pitch; 1222 surf_size_struct blocks; 1223 1224 svga3dsurface_get_size_in_blocks(desc, size, &blocks); 1225 1226 pitch = blocks.width * desc->pitch_bytes_per_block; 1227 1228 return pitch; 1229 } 1230 1231 /** 1232 * svga3dsurface_get_image_buffer_size - Calculates image buffer size. 1233 * 1234 * Return the number of bytes of buffer space required to store one image of a 1235 * surface, optionally using the specified pitch. 1236 * 1237 * If pitch is zero, it is assumed that rows are tightly packed. 1238 * 1239 * This function is overflow-safe. If the result would have overflowed, instead 1240 * we return MAX_UINT32. 1241 */ 1242 static inline u32 1243 svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc, 1244 const surf_size_struct *size, 1245 u32 pitch) 1246 { 1247 surf_size_struct image_blocks; 1248 u32 slice_size, total_size; 1249 1250 svga3dsurface_get_size_in_blocks(desc, size, &image_blocks); 1251 1252 if (svga3dsurface_is_planar_surface(desc)) { 1253 total_size = clamped_umul32(image_blocks.width, 1254 image_blocks.height); 1255 total_size = clamped_umul32(total_size, image_blocks.depth); 1256 total_size = clamped_umul32(total_size, desc->bytes_per_block); 1257 return total_size; 1258 } 1259 1260 if (pitch == 0) 1261 pitch = svga3dsurface_calculate_pitch(desc, size); 1262 1263 slice_size = clamped_umul32(image_blocks.height, pitch); 1264 total_size = clamped_umul32(slice_size, image_blocks.depth); 1265 1266 return total_size; 1267 } 1268 1269 /** 1270 * svga3dsurface_get_serialized_size - Get the serialized size for the image. 1271 */ 1272 static inline u32 1273 svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format, 1274 surf_size_struct base_level_size, 1275 u32 num_mip_levels, 1276 u32 num_layers) 1277 { 1278 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); 1279 u32 total_size = 0; 1280 u32 mip; 1281 1282 for (mip = 0; mip < num_mip_levels; mip++) { 1283 surf_size_struct size = 1284 svga3dsurface_get_mip_size(base_level_size, mip); 1285 total_size += svga3dsurface_get_image_buffer_size(desc, 1286 &size, 0); 1287 } 1288 1289 return total_size * num_layers; 1290 } 1291 1292 /** 1293 * svga3dsurface_get_serialized_size_extended - Returns the number of bytes 1294 * required for a surface with given parameters. Support for sample count. 1295 */ 1296 static inline u32 1297 svga3dsurface_get_serialized_size_extended(SVGA3dSurfaceFormat format, 1298 surf_size_struct base_level_size, 1299 u32 num_mip_levels, 1300 u32 num_layers, 1301 u32 num_samples) 1302 { 1303 uint64_t total_size = 1304 svga3dsurface_get_serialized_size(format, 1305 base_level_size, 1306 num_mip_levels, 1307 num_layers); 1308 total_size *= max_t(u32, 1, num_samples); 1309 1310 return min_t(uint64_t, total_size, (uint64_t)U32_MAX); 1311 } 1312 1313 /** 1314 * svga3dsurface_get_pixel_offset - Compute the offset (in bytes) to a pixel 1315 * in an image (or volume). 1316 * 1317 * @width: The image width in pixels. 1318 * @height: The image height in pixels 1319 */ 1320 static inline u32 1321 svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format, 1322 u32 width, u32 height, 1323 u32 x, u32 y, u32 z) 1324 { 1325 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); 1326 const u32 bw = desc->block_size.width, bh = desc->block_size.height; 1327 const u32 bd = desc->block_size.depth; 1328 const u32 rowstride = __KERNEL_DIV_ROUND_UP(width, bw) * 1329 desc->bytes_per_block; 1330 const u32 imgstride = __KERNEL_DIV_ROUND_UP(height, bh) * rowstride; 1331 const u32 offset = (z / bd * imgstride + 1332 y / bh * rowstride + 1333 x / bw * desc->bytes_per_block); 1334 return offset; 1335 } 1336 1337 static inline u32 1338 svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format, 1339 surf_size_struct baseLevelSize, 1340 u32 numMipLevels, 1341 u32 face, 1342 u32 mip) 1343 1344 { 1345 u32 offset; 1346 u32 mipChainBytes; 1347 u32 mipChainBytesToLevel; 1348 u32 i; 1349 const struct svga3d_surface_desc *desc; 1350 surf_size_struct mipSize; 1351 u32 bytes; 1352 1353 desc = svga3dsurface_get_desc(format); 1354 1355 mipChainBytes = 0; 1356 mipChainBytesToLevel = 0; 1357 for (i = 0; i < numMipLevels; i++) { 1358 mipSize = svga3dsurface_get_mip_size(baseLevelSize, i); 1359 bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0); 1360 mipChainBytes += bytes; 1361 if (i < mip) 1362 mipChainBytesToLevel += bytes; 1363 } 1364 1365 offset = mipChainBytes * face + mipChainBytesToLevel; 1366 1367 return offset; 1368 } 1369 1370 1371 /** 1372 * svga3dsurface_is_gb_screen_target_format - Is the specified format usable as 1373 * a ScreenTarget? 1374 * (with just the GBObjects cap-bit 1375 * set) 1376 * @format: format to queried 1377 * 1378 * RETURNS: 1379 * true if queried format is valid for screen targets 1380 */ 1381 static inline bool 1382 svga3dsurface_is_gb_screen_target_format(SVGA3dSurfaceFormat format) 1383 { 1384 return (format == SVGA3D_X8R8G8B8 || 1385 format == SVGA3D_A8R8G8B8 || 1386 format == SVGA3D_R5G6B5 || 1387 format == SVGA3D_X1R5G5B5 || 1388 format == SVGA3D_A1R5G5B5 || 1389 format == SVGA3D_P8); 1390 } 1391 1392 1393 /** 1394 * svga3dsurface_is_dx_screen_target_format - Is the specified format usable as 1395 * a ScreenTarget? 1396 * (with DX10 enabled) 1397 * 1398 * @format: format to queried 1399 * 1400 * Results: 1401 * true if queried format is valid for screen targets 1402 */ 1403 static inline bool 1404 svga3dsurface_is_dx_screen_target_format(SVGA3dSurfaceFormat format) 1405 { 1406 return (format == SVGA3D_R8G8B8A8_UNORM || 1407 format == SVGA3D_B8G8R8A8_UNORM || 1408 format == SVGA3D_B8G8R8X8_UNORM); 1409 } 1410 1411 1412 /** 1413 * svga3dsurface_is_screen_target_format - Is the specified format usable as a 1414 * ScreenTarget? 1415 * (for some combination of caps) 1416 * 1417 * @format: format to queried 1418 * 1419 * Results: 1420 * true if queried format is valid for screen targets 1421 */ 1422 static inline bool 1423 svga3dsurface_is_screen_target_format(SVGA3dSurfaceFormat format) 1424 { 1425 if (svga3dsurface_is_gb_screen_target_format(format)) { 1426 return true; 1427 } 1428 return svga3dsurface_is_dx_screen_target_format(format); 1429 } 1430 1431 /** 1432 * struct svga3dsurface_mip - Mimpmap level information 1433 * @bytes: Bytes required in the backing store of this mipmap level. 1434 * @img_stride: Byte stride per image. 1435 * @row_stride: Byte stride per block row. 1436 * @size: The size of the mipmap. 1437 */ 1438 struct svga3dsurface_mip { 1439 size_t bytes; 1440 size_t img_stride; 1441 size_t row_stride; 1442 struct drm_vmw_size size; 1443 1444 }; 1445 1446 /** 1447 * struct svga3dsurface_cache - Cached surface information 1448 * @desc: Pointer to the surface descriptor 1449 * @mip: Array of mipmap level information. Valid size is @num_mip_levels. 1450 * @mip_chain_bytes: Bytes required in the backing store for the whole chain 1451 * of mip levels. 1452 * @sheet_bytes: Bytes required in the backing store for a sheet 1453 * representing a single sample. 1454 * @num_mip_levels: Valid size of the @mip array. Number of mipmap levels in 1455 * a chain. 1456 * @num_layers: Number of slices in an array texture or number of faces in 1457 * a cubemap texture. 1458 */ 1459 struct svga3dsurface_cache { 1460 const struct svga3d_surface_desc *desc; 1461 struct svga3dsurface_mip mip[DRM_VMW_MAX_MIP_LEVELS]; 1462 size_t mip_chain_bytes; 1463 size_t sheet_bytes; 1464 u32 num_mip_levels; 1465 u32 num_layers; 1466 }; 1467 1468 /** 1469 * struct svga3dsurface_loc - Surface location 1470 * @sub_resource: Surface subresource. Defined as layer * num_mip_levels + 1471 * mip_level. 1472 * @x: X coordinate. 1473 * @y: Y coordinate. 1474 * @z: Z coordinate. 1475 */ 1476 struct svga3dsurface_loc { 1477 u32 sub_resource; 1478 u32 x, y, z; 1479 }; 1480 1481 /** 1482 * svga3dsurface_subres - Compute the subresource from layer and mipmap. 1483 * @cache: Surface layout data. 1484 * @mip_level: The mipmap level. 1485 * @layer: The surface layer (face or array slice). 1486 * 1487 * Return: The subresource. 1488 */ 1489 static inline u32 svga3dsurface_subres(const struct svga3dsurface_cache *cache, 1490 u32 mip_level, u32 layer) 1491 { 1492 return cache->num_mip_levels * layer + mip_level; 1493 } 1494 1495 /** 1496 * svga3dsurface_setup_cache - Build a surface cache entry 1497 * @size: The surface base level dimensions. 1498 * @format: The surface format. 1499 * @num_mip_levels: Number of mipmap levels. 1500 * @num_layers: Number of layers. 1501 * @cache: Pointer to a struct svga3dsurface_cach object to be filled in. 1502 * 1503 * Return: Zero on success, -EINVAL on invalid surface layout. 1504 */ 1505 static inline int svga3dsurface_setup_cache(const struct drm_vmw_size *size, 1506 SVGA3dSurfaceFormat format, 1507 u32 num_mip_levels, 1508 u32 num_layers, 1509 u32 num_samples, 1510 struct svga3dsurface_cache *cache) 1511 { 1512 const struct svga3d_surface_desc *desc; 1513 u32 i; 1514 1515 memset(cache, 0, sizeof(*cache)); 1516 cache->desc = desc = svga3dsurface_get_desc(format); 1517 cache->num_mip_levels = num_mip_levels; 1518 cache->num_layers = num_layers; 1519 for (i = 0; i < cache->num_mip_levels; i++) { 1520 struct svga3dsurface_mip *mip = &cache->mip[i]; 1521 1522 mip->size = svga3dsurface_get_mip_size(*size, i); 1523 mip->bytes = svga3dsurface_get_image_buffer_size 1524 (desc, &mip->size, 0); 1525 mip->row_stride = 1526 __KERNEL_DIV_ROUND_UP(mip->size.width, 1527 desc->block_size.width) * 1528 desc->bytes_per_block * num_samples; 1529 if (!mip->row_stride) 1530 goto invalid_dim; 1531 1532 mip->img_stride = 1533 __KERNEL_DIV_ROUND_UP(mip->size.height, 1534 desc->block_size.height) * 1535 mip->row_stride; 1536 if (!mip->img_stride) 1537 goto invalid_dim; 1538 1539 cache->mip_chain_bytes += mip->bytes; 1540 } 1541 cache->sheet_bytes = cache->mip_chain_bytes * num_layers; 1542 if (!cache->sheet_bytes) 1543 goto invalid_dim; 1544 1545 return 0; 1546 1547 invalid_dim: 1548 VMW_DEBUG_USER("Invalid surface layout for dirty tracking.\n"); 1549 return -EINVAL; 1550 } 1551 1552 /** 1553 * svga3dsurface_get_loc - Get a surface location from an offset into the 1554 * backing store 1555 * @cache: Surface layout data. 1556 * @loc: Pointer to a struct svga3dsurface_loc to be filled in. 1557 * @offset: Offset into the surface backing store. 1558 */ 1559 static inline void 1560 svga3dsurface_get_loc(const struct svga3dsurface_cache *cache, 1561 struct svga3dsurface_loc *loc, 1562 size_t offset) 1563 { 1564 const struct svga3dsurface_mip *mip = &cache->mip[0]; 1565 const struct svga3d_surface_desc *desc = cache->desc; 1566 u32 layer; 1567 int i; 1568 1569 if (offset >= cache->sheet_bytes) 1570 offset %= cache->sheet_bytes; 1571 1572 layer = offset / cache->mip_chain_bytes; 1573 offset -= layer * cache->mip_chain_bytes; 1574 for (i = 0; i < cache->num_mip_levels; ++i, ++mip) { 1575 if (mip->bytes > offset) 1576 break; 1577 offset -= mip->bytes; 1578 } 1579 1580 loc->sub_resource = svga3dsurface_subres(cache, i, layer); 1581 loc->z = offset / mip->img_stride; 1582 offset -= loc->z * mip->img_stride; 1583 loc->z *= desc->block_size.depth; 1584 loc->y = offset / mip->row_stride; 1585 offset -= loc->y * mip->row_stride; 1586 loc->y *= desc->block_size.height; 1587 loc->x = offset / desc->bytes_per_block; 1588 loc->x *= desc->block_size.width; 1589 } 1590 1591 /** 1592 * svga3dsurface_inc_loc - Clamp increment a surface location with one block 1593 * size 1594 * in each dimension. 1595 * @loc: Pointer to a struct svga3dsurface_loc to be incremented. 1596 * 1597 * When computing the size of a range as size = end - start, the range does not 1598 * include the end element. However a location representing the last byte 1599 * of a touched region in the backing store *is* included in the range. 1600 * This function modifies such a location to match the end definition 1601 * given as start + size which is the one used in a SVGA3dBox. 1602 */ 1603 static inline void 1604 svga3dsurface_inc_loc(const struct svga3dsurface_cache *cache, 1605 struct svga3dsurface_loc *loc) 1606 { 1607 const struct svga3d_surface_desc *desc = cache->desc; 1608 u32 mip = loc->sub_resource % cache->num_mip_levels; 1609 const struct drm_vmw_size *size = &cache->mip[mip].size; 1610 1611 loc->sub_resource++; 1612 loc->x += desc->block_size.width; 1613 if (loc->x > size->width) 1614 loc->x = size->width; 1615 loc->y += desc->block_size.height; 1616 if (loc->y > size->height) 1617 loc->y = size->height; 1618 loc->z += desc->block_size.depth; 1619 if (loc->z > size->depth) 1620 loc->z = size->depth; 1621 } 1622 1623 /** 1624 * svga3dsurface_min_loc - The start location in a subresource 1625 * @cache: Surface layout data. 1626 * @sub_resource: The subresource. 1627 * @loc: Pointer to a struct svga3dsurface_loc to be filled in. 1628 */ 1629 static inline void 1630 svga3dsurface_min_loc(const struct svga3dsurface_cache *cache, 1631 u32 sub_resource, 1632 struct svga3dsurface_loc *loc) 1633 { 1634 loc->sub_resource = sub_resource; 1635 loc->x = loc->y = loc->z = 0; 1636 } 1637 1638 /** 1639 * svga3dsurface_min_loc - The end location in a subresource 1640 * @cache: Surface layout data. 1641 * @sub_resource: The subresource. 1642 * @loc: Pointer to a struct svga3dsurface_loc to be filled in. 1643 * 1644 * Following the end definition given in svga3dsurface_inc_loc(), 1645 * Compute the end location of a surface subresource. 1646 */ 1647 static inline void 1648 svga3dsurface_max_loc(const struct svga3dsurface_cache *cache, 1649 u32 sub_resource, 1650 struct svga3dsurface_loc *loc) 1651 { 1652 const struct drm_vmw_size *size; 1653 u32 mip; 1654 1655 loc->sub_resource = sub_resource + 1; 1656 mip = sub_resource % cache->num_mip_levels; 1657 size = &cache->mip[mip].size; 1658 loc->x = size->width; 1659 loc->y = size->height; 1660 loc->z = size->depth; 1661 } 1662 1663 #endif /* _SVGA3D_SURFACEDEFS_H_ */ 1664