1 /* 2 * Copyright (C) 2015 Red Hat, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #include <linux/virtio.h> 27 #include <linux/virtio_config.h> 28 #include <linux/virtio_ring.h> 29 30 #include <drm/drm_file.h> 31 #include <drm/drm_managed.h> 32 #include <drm/drm_print.h> 33 34 #include "virtgpu_drv.h" 35 36 static void virtio_gpu_config_changed_work_func(struct work_struct *work) 37 { 38 struct virtio_gpu_device *vgdev = 39 container_of(work, struct virtio_gpu_device, 40 config_changed_work); 41 u32 events_read, events_clear = 0; 42 43 /* read the config space */ 44 virtio_cread_le(vgdev->vdev, struct virtio_gpu_config, 45 events_read, &events_read); 46 if (events_read & VIRTIO_GPU_EVENT_DISPLAY) { 47 if (vgdev->num_scanouts) { 48 if (vgdev->has_edid) 49 virtio_gpu_cmd_get_edids(vgdev); 50 virtio_gpu_cmd_get_display_info(vgdev); 51 virtio_gpu_notify(vgdev); 52 wait_event_timeout(vgdev->resp_wq, 53 !vgdev->display_info_pending, 54 5 * HZ); 55 drm_kms_helper_hotplug_event(vgdev->ddev); 56 } 57 events_clear |= VIRTIO_GPU_EVENT_DISPLAY; 58 } 59 virtio_cwrite_le(vgdev->vdev, struct virtio_gpu_config, 60 events_clear, &events_clear); 61 } 62 63 static void virtio_gpu_init_vq(struct virtio_gpu_queue *vgvq, 64 void (*work_func)(struct work_struct *work)) 65 { 66 spin_lock_init(&vgvq->qlock); 67 init_waitqueue_head(&vgvq->ack_queue); 68 INIT_WORK(&vgvq->dequeue_work, work_func); 69 } 70 71 static void virtio_gpu_get_capsets(struct virtio_gpu_device *vgdev, 72 int num_capsets) 73 { 74 int i, ret; 75 bool invalid_capset_id = false; 76 struct drm_device *drm = vgdev->ddev; 77 78 vgdev->capsets = drmm_kcalloc(drm, num_capsets, 79 sizeof(struct virtio_gpu_drv_capset), 80 GFP_KERNEL); 81 if (!vgdev->capsets) { 82 DRM_ERROR("failed to allocate cap sets\n"); 83 return; 84 } 85 for (i = 0; i < num_capsets; i++) { 86 virtio_gpu_cmd_get_capset_info(vgdev, i); 87 virtio_gpu_notify(vgdev); 88 ret = wait_event_timeout(vgdev->resp_wq, 89 vgdev->capsets[i].id > 0, 5 * HZ); 90 /* 91 * Capability ids are defined in the virtio-gpu spec and are 92 * between 1 to 63, inclusive. 93 */ 94 if (!vgdev->capsets[i].id || 95 vgdev->capsets[i].id > MAX_CAPSET_ID) 96 invalid_capset_id = true; 97 98 if (ret == 0) 99 DRM_ERROR("timed out waiting for cap set %d\n", i); 100 else if (invalid_capset_id) 101 DRM_ERROR("invalid capset id %u", vgdev->capsets[i].id); 102 103 if (ret == 0 || invalid_capset_id) { 104 spin_lock(&vgdev->display_info_lock); 105 drmm_kfree(drm, vgdev->capsets); 106 vgdev->capsets = NULL; 107 spin_unlock(&vgdev->display_info_lock); 108 return; 109 } 110 111 vgdev->capset_id_mask |= 1 << vgdev->capsets[i].id; 112 DRM_INFO("cap set %d: id %d, max-version %d, max-size %d\n", 113 i, vgdev->capsets[i].id, 114 vgdev->capsets[i].max_version, 115 vgdev->capsets[i].max_size); 116 } 117 118 vgdev->num_capsets = num_capsets; 119 } 120 121 int virtio_gpu_init(struct virtio_device *vdev, struct drm_device *dev) 122 { 123 struct virtqueue_info vqs_info[] = { 124 { "control", virtio_gpu_ctrl_ack }, 125 { "cursor", virtio_gpu_cursor_ack }, 126 }; 127 struct virtio_gpu_device *vgdev; 128 /* this will expand later */ 129 struct virtqueue *vqs[2]; 130 u32 num_scanouts, num_capsets, blob_alignment; 131 int ret = 0; 132 133 if (!virtio_has_feature(vdev, VIRTIO_F_VERSION_1)) 134 return -ENODEV; 135 136 vgdev = drmm_kzalloc(dev, sizeof(struct virtio_gpu_device), GFP_KERNEL); 137 if (!vgdev) 138 return -ENOMEM; 139 140 vgdev->ddev = dev; 141 dev->dev_private = vgdev; 142 vgdev->vdev = vdev; 143 144 spin_lock_init(&vgdev->display_info_lock); 145 spin_lock_init(&vgdev->resource_export_lock); 146 spin_lock_init(&vgdev->host_visible_lock); 147 ida_init(&vgdev->ctx_id_ida); 148 ida_init(&vgdev->resource_ida); 149 init_waitqueue_head(&vgdev->resp_wq); 150 virtio_gpu_init_vq(&vgdev->ctrlq, virtio_gpu_dequeue_ctrl_func); 151 virtio_gpu_init_vq(&vgdev->cursorq, virtio_gpu_dequeue_cursor_func); 152 153 vgdev->fence_drv.context = dma_fence_context_alloc(1); 154 spin_lock_init(&vgdev->fence_drv.lock); 155 INIT_LIST_HEAD(&vgdev->fence_drv.fences); 156 INIT_LIST_HEAD(&vgdev->cap_cache); 157 INIT_WORK(&vgdev->config_changed_work, 158 virtio_gpu_config_changed_work_func); 159 160 INIT_WORK(&vgdev->obj_free_work, 161 virtio_gpu_array_put_free_work); 162 INIT_LIST_HEAD(&vgdev->obj_free_list); 163 spin_lock_init(&vgdev->obj_free_lock); 164 165 #ifdef __LITTLE_ENDIAN 166 if (virtio_has_feature(vgdev->vdev, VIRTIO_GPU_F_VIRGL)) 167 vgdev->has_virgl_3d = true; 168 #endif 169 if (virtio_has_feature(vgdev->vdev, VIRTIO_GPU_F_EDID)) 170 vgdev->has_edid = true; 171 172 if (virtio_has_feature(vgdev->vdev, VIRTIO_RING_F_INDIRECT_DESC)) 173 vgdev->has_indirect = true; 174 175 if (virtio_has_feature(vgdev->vdev, VIRTIO_GPU_F_RESOURCE_UUID)) 176 vgdev->has_resource_assign_uuid = true; 177 178 if (virtio_has_feature(vgdev->vdev, VIRTIO_GPU_F_RESOURCE_BLOB)) 179 vgdev->has_resource_blob = true; 180 181 if (virtio_get_shm_region(vgdev->vdev, &vgdev->host_visible_region, 182 VIRTIO_GPU_SHM_ID_HOST_VISIBLE)) { 183 if (!devm_request_mem_region(&vgdev->vdev->dev, 184 vgdev->host_visible_region.addr, 185 vgdev->host_visible_region.len, 186 dev_name(&vgdev->vdev->dev))) { 187 DRM_ERROR("Could not reserve host visible region\n"); 188 ret = -EBUSY; 189 goto err_vqs; 190 } 191 192 DRM_INFO("Host memory window: 0x%lx +0x%lx\n", 193 (unsigned long)vgdev->host_visible_region.addr, 194 (unsigned long)vgdev->host_visible_region.len); 195 vgdev->has_host_visible = true; 196 drm_mm_init(&vgdev->host_visible_mm, 197 (unsigned long)vgdev->host_visible_region.addr, 198 (unsigned long)vgdev->host_visible_region.len); 199 } 200 201 if (virtio_has_feature(vgdev->vdev, VIRTIO_GPU_F_CONTEXT_INIT)) 202 vgdev->has_context_init = true; 203 204 if (virtio_has_feature(vgdev->vdev, VIRTIO_GPU_F_BLOB_ALIGNMENT)) { 205 vgdev->has_blob_alignment = true; 206 virtio_cread_le(vgdev->vdev, struct virtio_gpu_config, 207 blob_alignment, &blob_alignment); 208 vgdev->blob_alignment = blob_alignment; 209 } 210 211 DRM_INFO("features: %cvirgl %cedid %cresource_blob %chost_visible", 212 vgdev->has_virgl_3d ? '+' : '-', 213 vgdev->has_edid ? '+' : '-', 214 vgdev->has_resource_blob ? '+' : '-', 215 vgdev->has_host_visible ? '+' : '-'); 216 217 DRM_INFO("features: %ccontext_init %cblob_alignment\n", 218 vgdev->has_context_init ? '+' : '-', 219 vgdev->has_blob_alignment ? '+' : '-'); 220 221 ret = virtio_find_vqs(vgdev->vdev, 2, vqs, vqs_info, NULL); 222 if (ret) { 223 DRM_ERROR("failed to find virt queues\n"); 224 goto err_vqs; 225 } 226 vgdev->ctrlq.vq = vqs[0]; 227 vgdev->cursorq.vq = vqs[1]; 228 ret = virtio_gpu_alloc_vbufs(vgdev); 229 if (ret) { 230 DRM_ERROR("failed to alloc vbufs\n"); 231 goto err_vbufs; 232 } 233 234 /* get display info */ 235 virtio_cread_le(vgdev->vdev, struct virtio_gpu_config, 236 num_scanouts, &num_scanouts); 237 vgdev->num_scanouts = min_t(uint32_t, num_scanouts, 238 VIRTIO_GPU_MAX_SCANOUTS); 239 240 if (!IS_ENABLED(CONFIG_DRM_VIRTIO_GPU_KMS) || !vgdev->num_scanouts) { 241 DRM_INFO("KMS disabled\n"); 242 vgdev->num_scanouts = 0; 243 vgdev->has_edid = false; 244 dev->driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); 245 } else { 246 DRM_INFO("number of scanouts: %d\n", num_scanouts); 247 } 248 249 virtio_cread_le(vgdev->vdev, struct virtio_gpu_config, 250 num_capsets, &num_capsets); 251 DRM_INFO("number of cap sets: %d\n", num_capsets); 252 253 ret = virtio_gpu_modeset_init(vgdev); 254 if (ret) { 255 DRM_ERROR("modeset init failed\n"); 256 goto err_scanouts; 257 } 258 259 virtio_device_ready(vgdev->vdev); 260 261 if (num_capsets) 262 virtio_gpu_get_capsets(vgdev, num_capsets); 263 if (vgdev->num_scanouts) { 264 if (vgdev->has_edid) 265 virtio_gpu_cmd_get_edids(vgdev); 266 virtio_gpu_cmd_get_display_info(vgdev); 267 virtio_gpu_notify(vgdev); 268 wait_event_timeout(vgdev->resp_wq, !vgdev->display_info_pending, 269 5 * HZ); 270 } 271 return 0; 272 273 err_scanouts: 274 virtio_gpu_free_vbufs(vgdev); 275 err_vbufs: 276 vgdev->vdev->config->del_vqs(vgdev->vdev); 277 err_vqs: 278 dev->dev_private = NULL; 279 return ret; 280 } 281 282 static void virtio_gpu_cleanup_cap_cache(struct virtio_gpu_device *vgdev) 283 { 284 struct virtio_gpu_drv_cap_cache *cache_ent, *tmp; 285 286 list_for_each_entry_safe(cache_ent, tmp, &vgdev->cap_cache, head) { 287 kfree(cache_ent->caps_cache); 288 kfree(cache_ent); 289 } 290 } 291 292 void virtio_gpu_deinit(struct drm_device *dev) 293 { 294 struct virtio_gpu_device *vgdev = dev->dev_private; 295 296 flush_work(&vgdev->obj_free_work); 297 flush_work(&vgdev->ctrlq.dequeue_work); 298 flush_work(&vgdev->cursorq.dequeue_work); 299 flush_work(&vgdev->config_changed_work); 300 virtio_reset_device(vgdev->vdev); 301 vgdev->vdev->config->del_vqs(vgdev->vdev); 302 } 303 304 void virtio_gpu_release(struct drm_device *dev) 305 { 306 struct virtio_gpu_device *vgdev = dev->dev_private; 307 308 if (!vgdev) 309 return; 310 311 virtio_gpu_modeset_fini(vgdev); 312 virtio_gpu_free_vbufs(vgdev); 313 virtio_gpu_cleanup_cap_cache(vgdev); 314 315 if (vgdev->has_host_visible) 316 drm_mm_takedown(&vgdev->host_visible_mm); 317 } 318 319 int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file) 320 { 321 struct virtio_gpu_device *vgdev = dev->dev_private; 322 struct virtio_gpu_fpriv *vfpriv; 323 int handle; 324 325 /* can't create contexts without 3d renderer */ 326 if (!vgdev->has_virgl_3d) 327 return 0; 328 329 /* allocate a virt GPU context for this opener */ 330 vfpriv = kzalloc_obj(*vfpriv); 331 if (!vfpriv) 332 return -ENOMEM; 333 334 mutex_init(&vfpriv->context_lock); 335 336 handle = ida_alloc(&vgdev->ctx_id_ida, GFP_KERNEL); 337 if (handle < 0) { 338 kfree(vfpriv); 339 return handle; 340 } 341 342 vfpriv->ctx_id = handle + 1; 343 file->driver_priv = vfpriv; 344 return 0; 345 } 346 347 void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file) 348 { 349 struct virtio_gpu_device *vgdev = dev->dev_private; 350 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 351 352 if (!vgdev->has_virgl_3d) 353 return; 354 355 if (vfpriv->context_created) { 356 virtio_gpu_cmd_context_destroy(vgdev, vfpriv->ctx_id); 357 virtio_gpu_notify(vgdev); 358 } 359 360 ida_free(&vgdev->ctx_id_ida, vfpriv->ctx_id - 1); 361 mutex_destroy(&vfpriv->context_lock); 362 kfree(vfpriv); 363 file->driver_priv = NULL; 364 } 365