1 /* 2 * Copyright (C) 2015 Red Hat, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef VIRTIO_DRV_H 27 #define VIRTIO_DRV_H 28 29 #include <linux/dma-direction.h> 30 #include <linux/virtio.h> 31 #include <linux/virtio_ids.h> 32 #include <linux/virtio_config.h> 33 #include <linux/virtio_gpu.h> 34 35 #include <drm/drm_atomic.h> 36 #include <drm/drm_drv.h> 37 #include <drm/drm_encoder.h> 38 #include <drm/drm_fourcc.h> 39 #include <drm/drm_framebuffer.h> 40 #include <drm/drm_gem.h> 41 #include <drm/drm_gem_shmem_helper.h> 42 #include <drm/drm_ioctl.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/virtgpu_drm.h> 45 46 #define DRIVER_NAME "virtio_gpu" 47 #define DRIVER_DESC "virtio GPU" 48 #define DRIVER_DATE "0" 49 50 #define DRIVER_MAJOR 0 51 #define DRIVER_MINOR 1 52 #define DRIVER_PATCHLEVEL 0 53 54 #define STATE_INITIALIZING 0 55 #define STATE_OK 1 56 #define STATE_ERR 2 57 58 #define MAX_CAPSET_ID 63 59 #define MAX_RINGS 64 60 61 struct virtio_gpu_object_params { 62 unsigned long size; 63 bool dumb; 64 /* 3d */ 65 bool virgl; 66 bool blob; 67 68 /* classic resources only */ 69 uint32_t format; 70 uint32_t width; 71 uint32_t height; 72 uint32_t target; 73 uint32_t bind; 74 uint32_t depth; 75 uint32_t array_size; 76 uint32_t last_level; 77 uint32_t nr_samples; 78 uint32_t flags; 79 80 /* blob resources only */ 81 uint32_t ctx_id; 82 uint32_t blob_mem; 83 uint32_t blob_flags; 84 uint64_t blob_id; 85 }; 86 87 struct virtio_gpu_object { 88 struct drm_gem_shmem_object base; 89 uint32_t hw_res_handle; 90 bool dumb; 91 bool created; 92 bool host3d_blob, guest_blob; 93 uint32_t blob_mem, blob_flags; 94 95 int uuid_state; 96 uuid_t uuid; 97 }; 98 #define gem_to_virtio_gpu_obj(gobj) \ 99 container_of((gobj), struct virtio_gpu_object, base.base) 100 101 struct virtio_gpu_object_shmem { 102 struct virtio_gpu_object base; 103 }; 104 105 struct virtio_gpu_object_vram { 106 struct virtio_gpu_object base; 107 uint32_t map_state; 108 uint32_t map_info; 109 struct drm_mm_node vram_node; 110 }; 111 112 #define to_virtio_gpu_shmem(virtio_gpu_object) \ 113 container_of((virtio_gpu_object), struct virtio_gpu_object_shmem, base) 114 115 #define to_virtio_gpu_vram(virtio_gpu_object) \ 116 container_of((virtio_gpu_object), struct virtio_gpu_object_vram, base) 117 118 struct virtio_gpu_object_array { 119 struct ww_acquire_ctx ticket; 120 struct list_head next; 121 u32 nents, total; 122 struct drm_gem_object *objs[]; 123 }; 124 125 struct virtio_gpu_vbuffer; 126 struct virtio_gpu_device; 127 128 typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev, 129 struct virtio_gpu_vbuffer *vbuf); 130 131 struct virtio_gpu_fence_driver { 132 atomic64_t last_fence_id; 133 uint64_t current_fence_id; 134 uint64_t context; 135 struct list_head fences; 136 spinlock_t lock; 137 }; 138 139 struct virtio_gpu_fence_event { 140 struct drm_pending_event base; 141 struct drm_event event; 142 }; 143 144 struct virtio_gpu_fence { 145 struct dma_fence f; 146 uint32_t ring_idx; 147 uint64_t fence_id; 148 bool emit_fence_info; 149 struct virtio_gpu_fence_event *e; 150 struct virtio_gpu_fence_driver *drv; 151 struct list_head node; 152 }; 153 154 struct virtio_gpu_vbuffer { 155 char *buf; 156 int size; 157 158 void *data_buf; 159 uint32_t data_size; 160 161 char *resp_buf; 162 int resp_size; 163 virtio_gpu_resp_cb resp_cb; 164 void *resp_cb_data; 165 166 struct virtio_gpu_object_array *objs; 167 struct list_head list; 168 }; 169 170 struct virtio_gpu_output { 171 int index; 172 struct drm_crtc crtc; 173 struct drm_connector conn; 174 struct drm_encoder enc; 175 struct virtio_gpu_display_one info; 176 struct virtio_gpu_update_cursor cursor; 177 struct edid *edid; 178 int cur_x; 179 int cur_y; 180 bool needs_modeset; 181 }; 182 #define drm_crtc_to_virtio_gpu_output(x) \ 183 container_of(x, struct virtio_gpu_output, crtc) 184 185 struct virtio_gpu_framebuffer { 186 struct drm_framebuffer base; 187 struct virtio_gpu_fence *fence; 188 }; 189 #define to_virtio_gpu_framebuffer(x) \ 190 container_of(x, struct virtio_gpu_framebuffer, base) 191 192 struct virtio_gpu_queue { 193 struct virtqueue *vq; 194 spinlock_t qlock; 195 wait_queue_head_t ack_queue; 196 struct work_struct dequeue_work; 197 }; 198 199 struct virtio_gpu_drv_capset { 200 uint32_t id; 201 uint32_t max_version; 202 uint32_t max_size; 203 }; 204 205 struct virtio_gpu_drv_cap_cache { 206 struct list_head head; 207 void *caps_cache; 208 uint32_t id; 209 uint32_t version; 210 uint32_t size; 211 atomic_t is_valid; 212 }; 213 214 struct virtio_gpu_device { 215 struct drm_device *ddev; 216 217 struct virtio_device *vdev; 218 219 struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS]; 220 uint32_t num_scanouts; 221 222 struct virtio_gpu_queue ctrlq; 223 struct virtio_gpu_queue cursorq; 224 struct kmem_cache *vbufs; 225 226 atomic_t pending_commands; 227 228 struct ida resource_ida; 229 230 wait_queue_head_t resp_wq; 231 /* current display info */ 232 spinlock_t display_info_lock; 233 bool display_info_pending; 234 235 struct virtio_gpu_fence_driver fence_drv; 236 237 struct ida ctx_id_ida; 238 239 bool has_virgl_3d; 240 bool has_edid; 241 bool has_indirect; 242 bool has_resource_assign_uuid; 243 bool has_resource_blob; 244 bool has_host_visible; 245 bool has_context_init; 246 struct virtio_shm_region host_visible_region; 247 struct drm_mm host_visible_mm; 248 249 struct work_struct config_changed_work; 250 251 struct work_struct obj_free_work; 252 spinlock_t obj_free_lock; 253 struct list_head obj_free_list; 254 255 struct virtio_gpu_drv_capset *capsets; 256 uint32_t num_capsets; 257 uint64_t capset_id_mask; 258 struct list_head cap_cache; 259 260 /* protects uuid state when exporting */ 261 spinlock_t resource_export_lock; 262 /* protects map state and host_visible_mm */ 263 spinlock_t host_visible_lock; 264 }; 265 266 struct virtio_gpu_fpriv { 267 uint32_t ctx_id; 268 uint32_t context_init; 269 bool context_created; 270 uint32_t num_rings; 271 uint64_t base_fence_ctx; 272 uint64_t ring_idx_mask; 273 struct mutex context_lock; 274 }; 275 276 /* virtgpu_ioctl.c */ 277 #define DRM_VIRTIO_NUM_IOCTLS 12 278 extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS]; 279 void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file); 280 281 /* virtgpu_kms.c */ 282 int virtio_gpu_init(struct virtio_device *vdev, struct drm_device *dev); 283 void virtio_gpu_deinit(struct drm_device *dev); 284 void virtio_gpu_release(struct drm_device *dev); 285 int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file); 286 void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file); 287 288 /* virtgpu_gem.c */ 289 int virtio_gpu_gem_object_open(struct drm_gem_object *obj, 290 struct drm_file *file); 291 void virtio_gpu_gem_object_close(struct drm_gem_object *obj, 292 struct drm_file *file); 293 int virtio_gpu_mode_dumb_create(struct drm_file *file_priv, 294 struct drm_device *dev, 295 struct drm_mode_create_dumb *args); 296 int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv, 297 struct drm_device *dev, 298 uint32_t handle, uint64_t *offset_p); 299 300 struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents); 301 struct virtio_gpu_object_array* 302 virtio_gpu_array_from_handles(struct drm_file *drm_file, u32 *handles, u32 nents); 303 void virtio_gpu_array_add_obj(struct virtio_gpu_object_array *objs, 304 struct drm_gem_object *obj); 305 int virtio_gpu_array_lock_resv(struct virtio_gpu_object_array *objs); 306 void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs); 307 void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs, 308 struct dma_fence *fence); 309 void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs); 310 void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev, 311 struct virtio_gpu_object_array *objs); 312 void virtio_gpu_array_put_free_work(struct work_struct *work); 313 314 /* virtgpu_vq.c */ 315 int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev); 316 void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev); 317 void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev, 318 struct virtio_gpu_object *bo, 319 struct virtio_gpu_object_params *params, 320 struct virtio_gpu_object_array *objs, 321 struct virtio_gpu_fence *fence); 322 void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev, 323 struct virtio_gpu_object *bo); 324 void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev, 325 uint64_t offset, 326 uint32_t width, uint32_t height, 327 uint32_t x, uint32_t y, 328 struct virtio_gpu_object_array *objs, 329 struct virtio_gpu_fence *fence); 330 void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev, 331 uint32_t resource_id, 332 uint32_t x, uint32_t y, 333 uint32_t width, uint32_t height, 334 struct virtio_gpu_object_array *objs, 335 struct virtio_gpu_fence *fence); 336 void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev, 337 uint32_t scanout_id, uint32_t resource_id, 338 uint32_t width, uint32_t height, 339 uint32_t x, uint32_t y); 340 void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev, 341 struct virtio_gpu_object *obj, 342 struct virtio_gpu_mem_entry *ents, 343 unsigned int nents); 344 int virtio_gpu_attach_status_page(struct virtio_gpu_device *vgdev); 345 int virtio_gpu_detach_status_page(struct virtio_gpu_device *vgdev); 346 void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev, 347 struct virtio_gpu_output *output); 348 int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev); 349 int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx); 350 int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev, 351 int idx, int version, 352 struct virtio_gpu_drv_cap_cache **cache_p); 353 int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev); 354 void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id, 355 uint32_t context_init, uint32_t nlen, 356 const char *name); 357 void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev, 358 uint32_t id); 359 void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev, 360 uint32_t ctx_id, 361 struct virtio_gpu_object_array *objs); 362 void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev, 363 uint32_t ctx_id, 364 struct virtio_gpu_object_array *objs); 365 void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev, 366 void *data, uint32_t data_size, 367 uint32_t ctx_id, 368 struct virtio_gpu_object_array *objs, 369 struct virtio_gpu_fence *fence); 370 void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev, 371 uint32_t ctx_id, 372 uint64_t offset, uint32_t level, 373 uint32_t stride, 374 uint32_t layer_stride, 375 struct drm_virtgpu_3d_box *box, 376 struct virtio_gpu_object_array *objs, 377 struct virtio_gpu_fence *fence); 378 void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev, 379 uint32_t ctx_id, 380 uint64_t offset, uint32_t level, 381 uint32_t stride, 382 uint32_t layer_stride, 383 struct drm_virtgpu_3d_box *box, 384 struct virtio_gpu_object_array *objs, 385 struct virtio_gpu_fence *fence); 386 void 387 virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev, 388 struct virtio_gpu_object *bo, 389 struct virtio_gpu_object_params *params, 390 struct virtio_gpu_object_array *objs, 391 struct virtio_gpu_fence *fence); 392 void virtio_gpu_ctrl_ack(struct virtqueue *vq); 393 void virtio_gpu_cursor_ack(struct virtqueue *vq); 394 void virtio_gpu_fence_ack(struct virtqueue *vq); 395 void virtio_gpu_dequeue_ctrl_func(struct work_struct *work); 396 void virtio_gpu_dequeue_cursor_func(struct work_struct *work); 397 void virtio_gpu_dequeue_fence_func(struct work_struct *work); 398 399 void virtio_gpu_notify(struct virtio_gpu_device *vgdev); 400 401 int 402 virtio_gpu_cmd_resource_assign_uuid(struct virtio_gpu_device *vgdev, 403 struct virtio_gpu_object_array *objs); 404 405 int virtio_gpu_cmd_map(struct virtio_gpu_device *vgdev, 406 struct virtio_gpu_object_array *objs, uint64_t offset); 407 408 void virtio_gpu_cmd_unmap(struct virtio_gpu_device *vgdev, 409 struct virtio_gpu_object *bo); 410 411 void 412 virtio_gpu_cmd_resource_create_blob(struct virtio_gpu_device *vgdev, 413 struct virtio_gpu_object *bo, 414 struct virtio_gpu_object_params *params, 415 struct virtio_gpu_mem_entry *ents, 416 uint32_t nents); 417 void 418 virtio_gpu_cmd_set_scanout_blob(struct virtio_gpu_device *vgdev, 419 uint32_t scanout_id, 420 struct virtio_gpu_object *bo, 421 struct drm_framebuffer *fb, 422 uint32_t width, uint32_t height, 423 uint32_t x, uint32_t y); 424 425 /* virtgpu_display.c */ 426 int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev); 427 void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev); 428 429 /* virtgpu_plane.c */ 430 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc); 431 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev, 432 enum drm_plane_type type, 433 int index); 434 435 /* virtgpu_fence.c */ 436 struct virtio_gpu_fence *virtio_gpu_fence_alloc(struct virtio_gpu_device *vgdev, 437 uint64_t base_fence_ctx, 438 uint32_t ring_idx); 439 void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev, 440 struct virtio_gpu_ctrl_hdr *cmd_hdr, 441 struct virtio_gpu_fence *fence); 442 void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev, 443 u64 fence_id); 444 445 /* virtgpu_object.c */ 446 void virtio_gpu_cleanup_object(struct virtio_gpu_object *bo); 447 struct drm_gem_object *virtio_gpu_create_object(struct drm_device *dev, 448 size_t size); 449 int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, 450 struct virtio_gpu_object_params *params, 451 struct virtio_gpu_object **bo_ptr, 452 struct virtio_gpu_fence *fence); 453 454 bool virtio_gpu_is_shmem(struct virtio_gpu_object *bo); 455 456 int virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev, 457 uint32_t *resid); 458 /* virtgpu_prime.c */ 459 int virtio_gpu_resource_assign_uuid(struct virtio_gpu_device *vgdev, 460 struct virtio_gpu_object *bo); 461 struct dma_buf *virtgpu_gem_prime_export(struct drm_gem_object *obj, 462 int flags); 463 struct drm_gem_object *virtgpu_gem_prime_import(struct drm_device *dev, 464 struct dma_buf *buf); 465 int virtgpu_gem_prime_get_uuid(struct drm_gem_object *obj, 466 uuid_t *uuid); 467 struct drm_gem_object *virtgpu_gem_prime_import_sg_table( 468 struct drm_device *dev, struct dma_buf_attachment *attach, 469 struct sg_table *sgt); 470 471 /* virtgpu_debugfs.c */ 472 void virtio_gpu_debugfs_init(struct drm_minor *minor); 473 474 /* virtgpu_vram.c */ 475 bool virtio_gpu_is_vram(struct virtio_gpu_object *bo); 476 int virtio_gpu_vram_create(struct virtio_gpu_device *vgdev, 477 struct virtio_gpu_object_params *params, 478 struct virtio_gpu_object **bo_ptr); 479 struct sg_table *virtio_gpu_vram_map_dma_buf(struct virtio_gpu_object *bo, 480 struct device *dev, 481 enum dma_data_direction dir); 482 void virtio_gpu_vram_unmap_dma_buf(struct device *dev, 483 struct sg_table *sgt, 484 enum dma_data_direction dir); 485 486 #endif 487