1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2025 Icenowy Zheng <uwu@icenowy.me> 4 * 5 * Based on vs_dc_hw.h, which is: 6 * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. 7 */ 8 9 #ifndef _VS_PRIMARY_PLANE_REGS_H_ 10 #define _VS_PRIMARY_PLANE_REGS_H_ 11 12 #include <linux/bits.h> 13 14 #define VSDC_FB_ADDRESS(n) (0x1400 + 0x4 * (n)) 15 16 #define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n)) 17 18 #define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n)) 19 #define VSDC_FB_CONFIG_CLEAR_EN BIT(8) 20 #define VSDC_FB_CONFIG_ROT_MASK GENMASK(13, 11) 21 #define VSDC_FB_CONFIG_ROT(v) ((v) << 11) 22 #define VSDC_FB_CONFIG_YUV_SPACE_MASK GENMASK(16, 14) 23 #define VSDC_FB_CONFIG_YUV_SPACE(v) ((v) << 14) 24 #define VSDC_FB_CONFIG_TILE_MODE_MASK GENMASK(21, 17) 25 #define VSDC_FB_CONFIG_TILE_MODE(v) ((v) << 14) 26 #define VSDC_FB_CONFIG_SCALE_EN BIT(22) 27 #define VSDC_FB_CONFIG_SWIZZLE_MASK GENMASK(24, 23) 28 #define VSDC_FB_CONFIG_SWIZZLE(v) ((v) << 23) 29 #define VSDC_FB_CONFIG_UV_SWIZZLE_EN BIT(25) 30 #define VSDC_FB_CONFIG_FMT_MASK GENMASK(31, 26) 31 #define VSDC_FB_CONFIG_FMT(v) ((v) << 26) 32 33 #define VSDC_FB_SIZE(n) (0x1810 + 0x4 * (n)) 34 /* Fill with value generated with VSDC_MAKE_PLANE_SIZE(w, h) */ 35 36 #define VSDC_FB_CONFIG_EX(n) (0x1CC0 + 0x4 * (n)) 37 #define VSDC_FB_CONFIG_EX_COMMIT BIT(12) 38 #define VSDC_FB_CONFIG_EX_FB_EN BIT(13) 39 #define VSDC_FB_CONFIG_EX_ZPOS_MASK GENMASK(18, 16) 40 #define VSDC_FB_CONFIG_EX_ZPOS(v) ((v) << 16) 41 #define VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK GENMASK(19, 19) 42 #define VSDC_FB_CONFIG_EX_DISPLAY_ID(v) ((v) << 19) 43 44 #define VSDC_FB_TOP_LEFT(n) (0x24D8 + 0x4 * (n)) 45 /* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ 46 47 #define VSDC_FB_BOTTOM_RIGHT(n) (0x24E0 + 0x4 * (n)) 48 /* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ 49 50 #define VSDC_FB_BLEND_CONFIG(n) (0x2510 + 0x4 * (n)) 51 #define VSDC_FB_BLEND_CONFIG_BLEND_DISABLE BIT(1) 52 53 #endif /* _VS_PRIMARY_PLANE_REGS_H_ */ 54