1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2016 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 SDTV module 8 * 9 * The VEC encoder generates PAL or NTSC composite video output. 10 * 11 * TV mode selection is done by an atomic property on the encoder, 12 * because a drm_mode_modeinfo is insufficient to distinguish between 13 * PAL and PAL-M or NTSC and NTSC-J. 14 */ 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_panel.h> 20 #include <drm/drm_probe_helper.h> 21 #include <drm/drm_simple_kms_helper.h> 22 #include <linux/clk.h> 23 #include <linux/component.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 28 #include "vc4_drv.h" 29 #include "vc4_regs.h" 30 31 /* WSE Registers */ 32 #define VEC_WSE_RESET 0xc0 33 34 #define VEC_WSE_CONTROL 0xc4 35 #define VEC_WSE_WSS_ENABLE BIT(7) 36 37 #define VEC_WSE_WSS_DATA 0xc8 38 #define VEC_WSE_VPS_DATA1 0xcc 39 #define VEC_WSE_VPS_CONTROL 0xd0 40 41 /* VEC Registers */ 42 #define VEC_REVID 0x100 43 44 #define VEC_CONFIG0 0x104 45 #define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26) 46 #define VEC_CONFIG0_YDEL(x) ((x) << 26) 47 #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) 48 #define VEC_CONFIG0_CDEL(x) ((x) << 24) 49 #define VEC_CONFIG0_SECAM_STD BIT(21) 50 #define VEC_CONFIG0_PBPR_FIL BIT(18) 51 #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) 52 #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) 53 #define VEC_CONFIG0_CHROMA_GAIN_1_32 (1 << 16) 54 #define VEC_CONFIG0_CHROMA_GAIN_1_16 (2 << 16) 55 #define VEC_CONFIG0_CHROMA_GAIN_1_8 (3 << 16) 56 #define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13) 57 #define VEC_CONFIG0_CBURST_GAIN_UNITY (0 << 13) 58 #define VEC_CONFIG0_CBURST_GAIN_1_128 (1 << 13) 59 #define VEC_CONFIG0_CBURST_GAIN_1_64 (2 << 13) 60 #define VEC_CONFIG0_CBURST_GAIN_1_32 (3 << 13) 61 #define VEC_CONFIG0_CHRBW1 BIT(11) 62 #define VEC_CONFIG0_CHRBW0 BIT(10) 63 #define VEC_CONFIG0_SYNCDIS BIT(9) 64 #define VEC_CONFIG0_BURDIS BIT(8) 65 #define VEC_CONFIG0_CHRDIS BIT(7) 66 #define VEC_CONFIG0_PDEN BIT(6) 67 #define VEC_CONFIG0_YCDELAY BIT(4) 68 #define VEC_CONFIG0_RAMPEN BIT(2) 69 #define VEC_CONFIG0_YCDIS BIT(2) 70 #define VEC_CONFIG0_STD_MASK GENMASK(1, 0) 71 #define VEC_CONFIG0_NTSC_STD 0 72 #define VEC_CONFIG0_PAL_BDGHI_STD 1 73 #define VEC_CONFIG0_PAL_M_STD 2 74 #define VEC_CONFIG0_PAL_N_STD 3 75 76 #define VEC_SCHPH 0x108 77 #define VEC_SOFT_RESET 0x10c 78 #define VEC_CLMP0_START 0x144 79 #define VEC_CLMP0_END 0x148 80 81 /* 82 * These set the color subcarrier frequency 83 * if VEC_CONFIG1_CUSTOM_FREQ is enabled. 84 * 85 * VEC_FREQ1_0 contains the most significant 16-bit half-word, 86 * VEC_FREQ3_2 contains the least significant 16-bit half-word. 87 * 0x80000000 seems to be equivalent to the pixel clock 88 * (which itself is the VEC clock divided by 8). 89 * 90 * Reference values (with the default pixel clock of 13.5 MHz): 91 * 92 * NTSC (3579545.[45] Hz) - 0x21F07C1F 93 * PAL (4433618.75 Hz) - 0x2A098ACB 94 * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3 95 * PAL-N (3582056.25 Hz) - 0x21F69446 96 * 97 * NOTE: For SECAM, it is used as the Dr center frequency, 98 * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not; 99 * that is specified as 4406250 Hz, which corresponds to 0x29C71C72. 100 */ 101 #define VEC_FREQ3_2 0x180 102 #define VEC_FREQ1_0 0x184 103 104 #define VEC_CONFIG1 0x188 105 #define VEC_CONFIG_VEC_RESYNC_OFF BIT(18) 106 #define VEC_CONFIG_RGB219 BIT(17) 107 #define VEC_CONFIG_CBAR_EN BIT(16) 108 #define VEC_CONFIG_TC_OBB BIT(15) 109 #define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10) 110 #define VEC_CONFIG1_C_Y_CVBS (0 << 10) 111 #define VEC_CONFIG1_CVBS_Y_C (1 << 10) 112 #define VEC_CONFIG1_PR_Y_PB (2 << 10) 113 #define VEC_CONFIG1_RGB (4 << 10) 114 #define VEC_CONFIG1_Y_C_CVBS (5 << 10) 115 #define VEC_CONFIG1_C_CVBS_Y (6 << 10) 116 #define VEC_CONFIG1_C_CVBS_CVBS (7 << 10) 117 #define VEC_CONFIG1_DIS_CHR BIT(9) 118 #define VEC_CONFIG1_DIS_LUMA BIT(8) 119 #define VEC_CONFIG1_YCBCR_IN BIT(6) 120 #define VEC_CONFIG1_DITHER_TYPE_LFSR 0 121 #define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5) 122 #define VEC_CONFIG1_DITHER_EN BIT(4) 123 #define VEC_CONFIG1_CYDELAY BIT(3) 124 #define VEC_CONFIG1_LUMADIS BIT(2) 125 #define VEC_CONFIG1_COMPDIS BIT(1) 126 #define VEC_CONFIG1_CUSTOM_FREQ BIT(0) 127 128 #define VEC_CONFIG2 0x18c 129 #define VEC_CONFIG2_PROG_SCAN BIT(15) 130 #define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12) 131 #define VEC_CONFIG2_SYNC_ADJ(x) (((x) / 2) << 12) 132 #define VEC_CONFIG2_PBPR_EN BIT(10) 133 #define VEC_CONFIG2_UV_DIG_DIS BIT(6) 134 #define VEC_CONFIG2_RGB_DIG_DIS BIT(5) 135 #define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2) 136 #define VEC_CONFIG2_TMUX_DRIVE0 (0 << 2) 137 #define VEC_CONFIG2_TMUX_RG_COMP (1 << 2) 138 #define VEC_CONFIG2_TMUX_UV_YC (2 << 2) 139 #define VEC_CONFIG2_TMUX_SYNC_YC (3 << 2) 140 141 #define VEC_INTERRUPT_CONTROL 0x190 142 #define VEC_INTERRUPT_STATUS 0x194 143 144 /* 145 * Db center frequency for SECAM; the clock for this is the same as for 146 * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency. 147 * 148 * This is specified as 4250000 Hz, which corresponds to 0x284BDA13. 149 * That is also the default value, so no need to set it explicitly. 150 */ 151 #define VEC_FCW_SECAM_B 0x198 152 #define VEC_SECAM_GAIN_VAL 0x19c 153 154 #define VEC_CONFIG3 0x1a0 155 #define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0) 156 #define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0) 157 #define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1) 158 159 #define VEC_STATUS0 0x200 160 #define VEC_MASK0 0x204 161 162 #define VEC_CFG 0x208 163 #define VEC_CFG_SG_MODE_MASK GENMASK(6, 5) 164 #define VEC_CFG_SG_MODE(x) ((x) << 5) 165 #define VEC_CFG_SG_EN BIT(4) 166 #define VEC_CFG_VEC_EN BIT(3) 167 #define VEC_CFG_MB_EN BIT(2) 168 #define VEC_CFG_ENABLE BIT(1) 169 #define VEC_CFG_TB_EN BIT(0) 170 171 #define VEC_DAC_TEST 0x20c 172 173 #define VEC_DAC_CONFIG 0x210 174 #define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24) 175 #define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16) 176 #define VEC_DAC_CONFIG_DAC_CTRL(x) (x) 177 178 #define VEC_DAC_MISC 0x214 179 #define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16) 180 #define VEC_DAC_MISC_VCD_CTRL(x) ((x) << 16) 181 #define VEC_DAC_MISC_VID_ACT BIT(8) 182 #define VEC_DAC_MISC_VCD_PWRDN BIT(6) 183 #define VEC_DAC_MISC_BIAS_PWRDN BIT(5) 184 #define VEC_DAC_MISC_DAC_PWRDN BIT(2) 185 #define VEC_DAC_MISC_LDO_PWRDN BIT(1) 186 #define VEC_DAC_MISC_DAC_RST_N BIT(0) 187 188 189 struct vc4_vec_variant { 190 u32 dac_config; 191 }; 192 193 /* General VEC hardware state. */ 194 struct vc4_vec { 195 struct vc4_encoder encoder; 196 struct drm_connector connector; 197 198 struct platform_device *pdev; 199 const struct vc4_vec_variant *variant; 200 201 void __iomem *regs; 202 203 struct clk *clock; 204 205 struct drm_property *legacy_tv_mode_property; 206 207 struct debugfs_regset32 regset; 208 }; 209 210 #define VEC_READ(offset) \ 211 ({ \ 212 kunit_fail_current_test("Accessing a register in a unit test!\n"); \ 213 readl(vec->regs + (offset)); \ 214 }) 215 216 #define VEC_WRITE(offset, val) \ 217 do { \ 218 kunit_fail_current_test("Accessing a register in a unit test!\n"); \ 219 writel(val, vec->regs + (offset)); \ 220 } while (0) 221 222 #define encoder_to_vc4_vec(_encoder) \ 223 container_of_const(_encoder, struct vc4_vec, encoder.base) 224 225 #define connector_to_vc4_vec(_connector) \ 226 container_of_const(_connector, struct vc4_vec, connector) 227 228 enum vc4_vec_tv_mode_id { 229 VC4_VEC_TV_MODE_NTSC, 230 VC4_VEC_TV_MODE_NTSC_J, 231 VC4_VEC_TV_MODE_PAL, 232 VC4_VEC_TV_MODE_PAL_M, 233 VC4_VEC_TV_MODE_NTSC_443, 234 VC4_VEC_TV_MODE_PAL_60, 235 VC4_VEC_TV_MODE_PAL_N, 236 VC4_VEC_TV_MODE_SECAM, 237 }; 238 239 struct vc4_vec_tv_mode { 240 unsigned int mode; 241 u16 expected_htotal; 242 u32 config0; 243 u32 config1; 244 u32 custom_freq; 245 }; 246 247 static const struct debugfs_reg32 vec_regs[] = { 248 VC4_REG32(VEC_WSE_CONTROL), 249 VC4_REG32(VEC_WSE_WSS_DATA), 250 VC4_REG32(VEC_WSE_VPS_DATA1), 251 VC4_REG32(VEC_WSE_VPS_CONTROL), 252 VC4_REG32(VEC_REVID), 253 VC4_REG32(VEC_CONFIG0), 254 VC4_REG32(VEC_SCHPH), 255 VC4_REG32(VEC_CLMP0_START), 256 VC4_REG32(VEC_CLMP0_END), 257 VC4_REG32(VEC_FREQ3_2), 258 VC4_REG32(VEC_FREQ1_0), 259 VC4_REG32(VEC_CONFIG1), 260 VC4_REG32(VEC_CONFIG2), 261 VC4_REG32(VEC_INTERRUPT_CONTROL), 262 VC4_REG32(VEC_INTERRUPT_STATUS), 263 VC4_REG32(VEC_FCW_SECAM_B), 264 VC4_REG32(VEC_SECAM_GAIN_VAL), 265 VC4_REG32(VEC_CONFIG3), 266 VC4_REG32(VEC_STATUS0), 267 VC4_REG32(VEC_MASK0), 268 VC4_REG32(VEC_CFG), 269 VC4_REG32(VEC_DAC_TEST), 270 VC4_REG32(VEC_DAC_CONFIG), 271 VC4_REG32(VEC_DAC_MISC), 272 }; 273 274 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { 275 { 276 .mode = DRM_MODE_TV_MODE_NTSC, 277 .expected_htotal = 858, 278 .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN, 279 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 280 }, 281 { 282 .mode = DRM_MODE_TV_MODE_NTSC_443, 283 .expected_htotal = 858, 284 .config0 = VEC_CONFIG0_NTSC_STD, 285 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, 286 .custom_freq = 0x2a098acb, 287 }, 288 { 289 .mode = DRM_MODE_TV_MODE_NTSC_J, 290 .expected_htotal = 858, 291 .config0 = VEC_CONFIG0_NTSC_STD, 292 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 293 }, 294 { 295 .mode = DRM_MODE_TV_MODE_PAL, 296 .expected_htotal = 864, 297 .config0 = VEC_CONFIG0_PAL_BDGHI_STD, 298 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 299 }, 300 { 301 /* PAL-60 */ 302 .mode = DRM_MODE_TV_MODE_PAL, 303 .expected_htotal = 858, 304 .config0 = VEC_CONFIG0_PAL_M_STD, 305 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, 306 .custom_freq = 0x2a098acb, 307 }, 308 { 309 .mode = DRM_MODE_TV_MODE_PAL_M, 310 .expected_htotal = 858, 311 .config0 = VEC_CONFIG0_PAL_M_STD, 312 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 313 }, 314 { 315 .mode = DRM_MODE_TV_MODE_PAL_N, 316 .expected_htotal = 864, 317 .config0 = VEC_CONFIG0_PAL_N_STD, 318 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 319 }, 320 { 321 .mode = DRM_MODE_TV_MODE_SECAM, 322 .expected_htotal = 864, 323 .config0 = VEC_CONFIG0_SECAM_STD, 324 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 325 .custom_freq = 0x29c71c72, 326 }, 327 }; 328 329 static inline const struct vc4_vec_tv_mode * 330 vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal) 331 { 332 unsigned int i; 333 334 for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) { 335 const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i]; 336 337 if (tv_mode->mode == mode && 338 tv_mode->expected_htotal == htotal) 339 return tv_mode; 340 } 341 342 return NULL; 343 } 344 345 static const struct drm_prop_enum_list legacy_tv_mode_names[] = { 346 { VC4_VEC_TV_MODE_NTSC, "NTSC", }, 347 { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", }, 348 { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", }, 349 { VC4_VEC_TV_MODE_PAL, "PAL", }, 350 { VC4_VEC_TV_MODE_PAL_60, "PAL-60", }, 351 { VC4_VEC_TV_MODE_PAL_M, "PAL-M", }, 352 { VC4_VEC_TV_MODE_PAL_N, "PAL-N", }, 353 { VC4_VEC_TV_MODE_SECAM, "SECAM", }, 354 }; 355 356 static enum drm_connector_status 357 vc4_vec_connector_detect(struct drm_connector *connector, bool force) 358 { 359 return connector_status_unknown; 360 } 361 362 static void vc4_vec_connector_reset(struct drm_connector *connector) 363 { 364 drm_atomic_helper_connector_reset(connector); 365 drm_atomic_helper_connector_tv_reset(connector); 366 } 367 368 static int 369 vc4_vec_connector_set_property(struct drm_connector *connector, 370 struct drm_connector_state *state, 371 struct drm_property *property, 372 uint64_t val) 373 { 374 struct vc4_vec *vec = connector_to_vc4_vec(connector); 375 376 if (property != vec->legacy_tv_mode_property) 377 return -EINVAL; 378 379 switch (val) { 380 case VC4_VEC_TV_MODE_NTSC: 381 state->tv.mode = DRM_MODE_TV_MODE_NTSC; 382 break; 383 384 case VC4_VEC_TV_MODE_NTSC_443: 385 state->tv.mode = DRM_MODE_TV_MODE_NTSC_443; 386 break; 387 388 case VC4_VEC_TV_MODE_NTSC_J: 389 state->tv.mode = DRM_MODE_TV_MODE_NTSC_J; 390 break; 391 392 case VC4_VEC_TV_MODE_PAL: 393 case VC4_VEC_TV_MODE_PAL_60: 394 state->tv.mode = DRM_MODE_TV_MODE_PAL; 395 break; 396 397 case VC4_VEC_TV_MODE_PAL_M: 398 state->tv.mode = DRM_MODE_TV_MODE_PAL_M; 399 break; 400 401 case VC4_VEC_TV_MODE_PAL_N: 402 state->tv.mode = DRM_MODE_TV_MODE_PAL_N; 403 break; 404 405 case VC4_VEC_TV_MODE_SECAM: 406 state->tv.mode = DRM_MODE_TV_MODE_SECAM; 407 break; 408 409 default: 410 return -EINVAL; 411 } 412 413 return 0; 414 } 415 416 static int 417 vc4_vec_connector_get_property(struct drm_connector *connector, 418 const struct drm_connector_state *state, 419 struct drm_property *property, 420 uint64_t *val) 421 { 422 struct vc4_vec *vec = connector_to_vc4_vec(connector); 423 424 if (property != vec->legacy_tv_mode_property) 425 return -EINVAL; 426 427 switch (state->tv.mode) { 428 case DRM_MODE_TV_MODE_NTSC: 429 *val = VC4_VEC_TV_MODE_NTSC; 430 break; 431 432 case DRM_MODE_TV_MODE_NTSC_443: 433 *val = VC4_VEC_TV_MODE_NTSC_443; 434 break; 435 436 case DRM_MODE_TV_MODE_NTSC_J: 437 *val = VC4_VEC_TV_MODE_NTSC_J; 438 break; 439 440 case DRM_MODE_TV_MODE_PAL: 441 *val = VC4_VEC_TV_MODE_PAL; 442 break; 443 444 case DRM_MODE_TV_MODE_PAL_M: 445 *val = VC4_VEC_TV_MODE_PAL_M; 446 break; 447 448 case DRM_MODE_TV_MODE_PAL_N: 449 *val = VC4_VEC_TV_MODE_PAL_N; 450 break; 451 452 case DRM_MODE_TV_MODE_SECAM: 453 *val = VC4_VEC_TV_MODE_SECAM; 454 break; 455 456 default: 457 return -EINVAL; 458 } 459 460 return 0; 461 } 462 463 static const struct drm_connector_funcs vc4_vec_connector_funcs = { 464 .detect = vc4_vec_connector_detect, 465 .fill_modes = drm_helper_probe_single_connector_modes, 466 .reset = vc4_vec_connector_reset, 467 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 468 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 469 .atomic_get_property = vc4_vec_connector_get_property, 470 .atomic_set_property = vc4_vec_connector_set_property, 471 }; 472 473 static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = { 474 .atomic_check = drm_atomic_helper_connector_tv_check, 475 .get_modes = drm_connector_helper_tv_get_modes, 476 }; 477 478 static int vc4_vec_connector_init(struct drm_device *dev, struct vc4_vec *vec) 479 { 480 struct drm_connector *connector = &vec->connector; 481 struct drm_property *prop; 482 int ret; 483 484 connector->interlace_allowed = true; 485 486 ret = drmm_connector_init(dev, connector, &vc4_vec_connector_funcs, 487 DRM_MODE_CONNECTOR_Composite, NULL); 488 if (ret) 489 return ret; 490 491 drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs); 492 493 drm_object_attach_property(&connector->base, 494 dev->mode_config.tv_mode_property, 495 DRM_MODE_TV_MODE_NTSC); 496 497 prop = drm_property_create_enum(dev, 0, "mode", 498 legacy_tv_mode_names, 499 ARRAY_SIZE(legacy_tv_mode_names)); 500 if (!prop) 501 return -ENOMEM; 502 vec->legacy_tv_mode_property = prop; 503 504 drm_object_attach_property(&connector->base, prop, VC4_VEC_TV_MODE_NTSC); 505 506 drm_connector_attach_encoder(connector, &vec->encoder.base); 507 508 return 0; 509 } 510 511 static void vc4_vec_encoder_disable(struct drm_encoder *encoder, 512 struct drm_atomic_state *state) 513 { 514 struct drm_device *drm = encoder->dev; 515 struct vc4_vec *vec = encoder_to_vc4_vec(encoder); 516 int idx, ret; 517 518 if (!drm_dev_enter(drm, &idx)) 519 return; 520 521 VEC_WRITE(VEC_CFG, 0); 522 VEC_WRITE(VEC_DAC_MISC, 523 VEC_DAC_MISC_VCD_PWRDN | 524 VEC_DAC_MISC_BIAS_PWRDN | 525 VEC_DAC_MISC_DAC_PWRDN | 526 VEC_DAC_MISC_LDO_PWRDN); 527 528 clk_disable_unprepare(vec->clock); 529 530 ret = pm_runtime_put(&vec->pdev->dev); 531 if (ret < 0) { 532 DRM_ERROR("Failed to release power domain: %d\n", ret); 533 goto err_dev_exit; 534 } 535 536 drm_dev_exit(idx); 537 return; 538 539 err_dev_exit: 540 drm_dev_exit(idx); 541 } 542 543 static void vc4_vec_encoder_enable(struct drm_encoder *encoder, 544 struct drm_atomic_state *state) 545 { 546 struct drm_device *drm = encoder->dev; 547 struct vc4_vec *vec = encoder_to_vc4_vec(encoder); 548 struct drm_connector *connector = &vec->connector; 549 struct drm_connector_state *conn_state = 550 drm_atomic_get_new_connector_state(state, connector); 551 struct drm_display_mode *adjusted_mode = 552 &encoder->crtc->state->adjusted_mode; 553 const struct vc4_vec_tv_mode *tv_mode; 554 int idx, ret; 555 556 if (!drm_dev_enter(drm, &idx)) 557 return; 558 559 tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, 560 adjusted_mode->htotal); 561 if (!tv_mode) 562 goto err_dev_exit; 563 564 ret = pm_runtime_resume_and_get(&vec->pdev->dev); 565 if (ret < 0) { 566 DRM_ERROR("Failed to retain power domain: %d\n", ret); 567 goto err_dev_exit; 568 } 569 570 /* 571 * We need to set the clock rate each time we enable the encoder 572 * because there's a chance we share the same parent with the HDMI 573 * clock, and both drivers are requesting different rates. 574 * The good news is, these 2 encoders cannot be enabled at the same 575 * time, thus preventing incompatible rate requests. 576 */ 577 ret = clk_set_rate(vec->clock, 108000000); 578 if (ret) { 579 DRM_ERROR("Failed to set clock rate: %d\n", ret); 580 goto err_put_runtime_pm; 581 } 582 583 ret = clk_prepare_enable(vec->clock); 584 if (ret) { 585 DRM_ERROR("Failed to turn on core clock: %d\n", ret); 586 goto err_put_runtime_pm; 587 } 588 589 /* Reset the different blocks */ 590 VEC_WRITE(VEC_WSE_RESET, 1); 591 VEC_WRITE(VEC_SOFT_RESET, 1); 592 593 /* Disable the CGSM-A and WSE blocks */ 594 VEC_WRITE(VEC_WSE_CONTROL, 0); 595 596 /* Write config common to all modes. */ 597 598 /* 599 * Color subcarrier phase: phase = 360 * SCHPH / 256. 600 * 0x28 <=> 39.375 deg. 601 */ 602 VEC_WRITE(VEC_SCHPH, 0x28); 603 604 /* 605 * Reset to default values. 606 */ 607 VEC_WRITE(VEC_CLMP0_START, 0xac); 608 VEC_WRITE(VEC_CLMP0_END, 0xec); 609 VEC_WRITE(VEC_CONFIG2, 610 VEC_CONFIG2_UV_DIG_DIS | 611 VEC_CONFIG2_RGB_DIG_DIS | 612 ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 0 : VEC_CONFIG2_PROG_SCAN)); 613 VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD); 614 VEC_WRITE(VEC_DAC_CONFIG, vec->variant->dac_config); 615 616 /* Mask all interrupts. */ 617 VEC_WRITE(VEC_MASK0, 0); 618 619 VEC_WRITE(VEC_CONFIG0, tv_mode->config0); 620 VEC_WRITE(VEC_CONFIG1, tv_mode->config1); 621 622 if (tv_mode->custom_freq) { 623 VEC_WRITE(VEC_FREQ3_2, 624 (tv_mode->custom_freq >> 16) & 0xffff); 625 VEC_WRITE(VEC_FREQ1_0, 626 tv_mode->custom_freq & 0xffff); 627 } 628 629 VEC_WRITE(VEC_DAC_MISC, 630 VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N); 631 VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN); 632 633 drm_dev_exit(idx); 634 return; 635 636 err_put_runtime_pm: 637 pm_runtime_put(&vec->pdev->dev); 638 err_dev_exit: 639 drm_dev_exit(idx); 640 } 641 642 static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder, 643 struct drm_crtc_state *crtc_state, 644 struct drm_connector_state *conn_state) 645 { 646 const struct drm_display_mode *mode = &crtc_state->adjusted_mode; 647 const struct vc4_vec_tv_mode *tv_mode; 648 649 tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, mode->htotal); 650 if (!tv_mode) 651 return -EINVAL; 652 653 if (mode->crtc_hdisplay % 4) 654 return -EINVAL; 655 656 if (!(mode->crtc_hsync_end - mode->crtc_hsync_start)) 657 return -EINVAL; 658 659 switch (mode->htotal) { 660 /* NTSC */ 661 case 858: 662 if (mode->crtc_vtotal > 262) 663 return -EINVAL; 664 665 if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 253) 666 return -EINVAL; 667 668 if (!(mode->crtc_vsync_start - mode->crtc_vdisplay)) 669 return -EINVAL; 670 671 if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3) 672 return -EINVAL; 673 674 if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 4) 675 return -EINVAL; 676 677 break; 678 679 /* PAL/SECAM */ 680 case 864: 681 if (mode->crtc_vtotal > 312) 682 return -EINVAL; 683 684 if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 305) 685 return -EINVAL; 686 687 if (!(mode->crtc_vsync_start - mode->crtc_vdisplay)) 688 return -EINVAL; 689 690 if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3) 691 return -EINVAL; 692 693 if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 2) 694 return -EINVAL; 695 696 break; 697 698 default: 699 return -EINVAL; 700 } 701 702 return 0; 703 } 704 705 static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = { 706 .atomic_check = vc4_vec_encoder_atomic_check, 707 .atomic_disable = vc4_vec_encoder_disable, 708 .atomic_enable = vc4_vec_encoder_enable, 709 }; 710 711 static int vc4_vec_late_register(struct drm_encoder *encoder) 712 { 713 struct drm_device *drm = encoder->dev; 714 struct vc4_vec *vec = encoder_to_vc4_vec(encoder); 715 716 vc4_debugfs_add_regset32(drm, "vec_regs", &vec->regset); 717 718 return 0; 719 } 720 721 static const struct drm_encoder_funcs vc4_vec_encoder_funcs = { 722 .late_register = vc4_vec_late_register, 723 }; 724 725 static const struct vc4_vec_variant bcm2835_vec_variant = { 726 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0xc) | 727 VEC_DAC_CONFIG_DRIVER_CTRL(0xc) | 728 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46) 729 }; 730 731 static const struct vc4_vec_variant bcm2711_vec_variant = { 732 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0x0) | 733 VEC_DAC_CONFIG_DRIVER_CTRL(0x80) | 734 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x61) 735 }; 736 737 static const struct of_device_id vc4_vec_dt_match[] = { 738 { .compatible = "brcm,bcm2835-vec", .data = &bcm2835_vec_variant }, 739 { .compatible = "brcm,bcm2711-vec", .data = &bcm2711_vec_variant }, 740 { /* sentinel */ }, 741 }; 742 743 static int vc4_vec_bind(struct device *dev, struct device *master, void *data) 744 { 745 struct platform_device *pdev = to_platform_device(dev); 746 struct drm_device *drm = dev_get_drvdata(master); 747 struct vc4_vec *vec; 748 int ret; 749 750 ret = drm_mode_create_tv_properties(drm, 751 BIT(DRM_MODE_TV_MODE_NTSC) | 752 BIT(DRM_MODE_TV_MODE_NTSC_443) | 753 BIT(DRM_MODE_TV_MODE_NTSC_J) | 754 BIT(DRM_MODE_TV_MODE_PAL) | 755 BIT(DRM_MODE_TV_MODE_PAL_M) | 756 BIT(DRM_MODE_TV_MODE_PAL_N) | 757 BIT(DRM_MODE_TV_MODE_SECAM)); 758 if (ret) 759 return ret; 760 761 vec = drmm_kzalloc(drm, sizeof(*vec), GFP_KERNEL); 762 if (!vec) 763 return -ENOMEM; 764 765 vec->encoder.type = VC4_ENCODER_TYPE_VEC; 766 vec->pdev = pdev; 767 vec->variant = (const struct vc4_vec_variant *) 768 of_device_get_match_data(dev); 769 vec->regs = vc4_ioremap_regs(pdev, 0); 770 if (IS_ERR(vec->regs)) 771 return PTR_ERR(vec->regs); 772 vec->regset.base = vec->regs; 773 vec->regset.regs = vec_regs; 774 vec->regset.nregs = ARRAY_SIZE(vec_regs); 775 776 vec->clock = devm_clk_get(dev, NULL); 777 if (IS_ERR(vec->clock)) { 778 ret = PTR_ERR(vec->clock); 779 if (ret != -EPROBE_DEFER) 780 DRM_ERROR("Failed to get clock: %d\n", ret); 781 return ret; 782 } 783 784 ret = devm_pm_runtime_enable(dev); 785 if (ret) 786 return ret; 787 788 ret = drmm_encoder_init(drm, &vec->encoder.base, 789 &vc4_vec_encoder_funcs, 790 DRM_MODE_ENCODER_TVDAC, 791 NULL); 792 if (ret) 793 return ret; 794 795 drm_encoder_helper_add(&vec->encoder.base, &vc4_vec_encoder_helper_funcs); 796 797 ret = vc4_vec_connector_init(drm, vec); 798 if (ret) 799 return ret; 800 801 dev_set_drvdata(dev, vec); 802 803 return 0; 804 } 805 806 static const struct component_ops vc4_vec_ops = { 807 .bind = vc4_vec_bind, 808 }; 809 810 static int vc4_vec_dev_probe(struct platform_device *pdev) 811 { 812 return component_add(&pdev->dev, &vc4_vec_ops); 813 } 814 815 static void vc4_vec_dev_remove(struct platform_device *pdev) 816 { 817 component_del(&pdev->dev, &vc4_vec_ops); 818 } 819 820 struct platform_driver vc4_vec_driver = { 821 .probe = vc4_vec_dev_probe, 822 .remove_new = vc4_vec_dev_remove, 823 .driver = { 824 .name = "vc4_vec", 825 .of_match_table = vc4_vec_dt_match, 826 }, 827 }; 828