1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2016 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 SDTV module 8 * 9 * The VEC encoder generates PAL or NTSC composite video output. 10 * 11 * TV mode selection is done by an atomic property on the encoder, 12 * because a drm_mode_modeinfo is insufficient to distinguish between 13 * PAL and PAL-M or NTSC and NTSC-J. 14 */ 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_panel.h> 20 #include <drm/drm_probe_helper.h> 21 #include <drm/drm_simple_kms_helper.h> 22 #include <linux/clk.h> 23 #include <linux/component.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_platform.h> 26 #include <linux/pm_runtime.h> 27 28 #include "vc4_drv.h" 29 #include "vc4_regs.h" 30 31 /* WSE Registers */ 32 #define VEC_WSE_RESET 0xc0 33 34 #define VEC_WSE_CONTROL 0xc4 35 #define VEC_WSE_WSS_ENABLE BIT(7) 36 37 #define VEC_WSE_WSS_DATA 0xc8 38 #define VEC_WSE_VPS_DATA1 0xcc 39 #define VEC_WSE_VPS_CONTROL 0xd0 40 41 /* VEC Registers */ 42 #define VEC_REVID 0x100 43 44 #define VEC_CONFIG0 0x104 45 #define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26) 46 #define VEC_CONFIG0_YDEL(x) ((x) << 26) 47 #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) 48 #define VEC_CONFIG0_CDEL(x) ((x) << 24) 49 #define VEC_CONFIG0_SECAM_STD BIT(21) 50 #define VEC_CONFIG0_PBPR_FIL BIT(18) 51 #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) 52 #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) 53 #define VEC_CONFIG0_CHROMA_GAIN_1_32 (1 << 16) 54 #define VEC_CONFIG0_CHROMA_GAIN_1_16 (2 << 16) 55 #define VEC_CONFIG0_CHROMA_GAIN_1_8 (3 << 16) 56 #define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13) 57 #define VEC_CONFIG0_CBURST_GAIN_UNITY (0 << 13) 58 #define VEC_CONFIG0_CBURST_GAIN_1_128 (1 << 13) 59 #define VEC_CONFIG0_CBURST_GAIN_1_64 (2 << 13) 60 #define VEC_CONFIG0_CBURST_GAIN_1_32 (3 << 13) 61 #define VEC_CONFIG0_CHRBW1 BIT(11) 62 #define VEC_CONFIG0_CHRBW0 BIT(10) 63 #define VEC_CONFIG0_SYNCDIS BIT(9) 64 #define VEC_CONFIG0_BURDIS BIT(8) 65 #define VEC_CONFIG0_CHRDIS BIT(7) 66 #define VEC_CONFIG0_PDEN BIT(6) 67 #define VEC_CONFIG0_YCDELAY BIT(4) 68 #define VEC_CONFIG0_RAMPEN BIT(2) 69 #define VEC_CONFIG0_YCDIS BIT(2) 70 #define VEC_CONFIG0_STD_MASK GENMASK(1, 0) 71 #define VEC_CONFIG0_NTSC_STD 0 72 #define VEC_CONFIG0_PAL_BDGHI_STD 1 73 #define VEC_CONFIG0_PAL_M_STD 2 74 #define VEC_CONFIG0_PAL_N_STD 3 75 76 #define VEC_SCHPH 0x108 77 #define VEC_SOFT_RESET 0x10c 78 #define VEC_CLMP0_START 0x144 79 #define VEC_CLMP0_END 0x148 80 81 /* 82 * These set the color subcarrier frequency 83 * if VEC_CONFIG1_CUSTOM_FREQ is enabled. 84 * 85 * VEC_FREQ1_0 contains the most significant 16-bit half-word, 86 * VEC_FREQ3_2 contains the least significant 16-bit half-word. 87 * 0x80000000 seems to be equivalent to the pixel clock 88 * (which itself is the VEC clock divided by 8). 89 * 90 * Reference values (with the default pixel clock of 13.5 MHz): 91 * 92 * NTSC (3579545.[45] Hz) - 0x21F07C1F 93 * PAL (4433618.75 Hz) - 0x2A098ACB 94 * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3 95 * PAL-N (3582056.25 Hz) - 0x21F69446 96 * 97 * NOTE: For SECAM, it is used as the Dr center frequency, 98 * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not; 99 * that is specified as 4406250 Hz, which corresponds to 0x29C71C72. 100 */ 101 #define VEC_FREQ3_2 0x180 102 #define VEC_FREQ1_0 0x184 103 104 #define VEC_CONFIG1 0x188 105 #define VEC_CONFIG_VEC_RESYNC_OFF BIT(18) 106 #define VEC_CONFIG_RGB219 BIT(17) 107 #define VEC_CONFIG_CBAR_EN BIT(16) 108 #define VEC_CONFIG_TC_OBB BIT(15) 109 #define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10) 110 #define VEC_CONFIG1_C_Y_CVBS (0 << 10) 111 #define VEC_CONFIG1_CVBS_Y_C (1 << 10) 112 #define VEC_CONFIG1_PR_Y_PB (2 << 10) 113 #define VEC_CONFIG1_RGB (4 << 10) 114 #define VEC_CONFIG1_Y_C_CVBS (5 << 10) 115 #define VEC_CONFIG1_C_CVBS_Y (6 << 10) 116 #define VEC_CONFIG1_C_CVBS_CVBS (7 << 10) 117 #define VEC_CONFIG1_DIS_CHR BIT(9) 118 #define VEC_CONFIG1_DIS_LUMA BIT(8) 119 #define VEC_CONFIG1_YCBCR_IN BIT(6) 120 #define VEC_CONFIG1_DITHER_TYPE_LFSR 0 121 #define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5) 122 #define VEC_CONFIG1_DITHER_EN BIT(4) 123 #define VEC_CONFIG1_CYDELAY BIT(3) 124 #define VEC_CONFIG1_LUMADIS BIT(2) 125 #define VEC_CONFIG1_COMPDIS BIT(1) 126 #define VEC_CONFIG1_CUSTOM_FREQ BIT(0) 127 128 #define VEC_CONFIG2 0x18c 129 #define VEC_CONFIG2_PROG_SCAN BIT(15) 130 #define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12) 131 #define VEC_CONFIG2_SYNC_ADJ(x) (((x) / 2) << 12) 132 #define VEC_CONFIG2_PBPR_EN BIT(10) 133 #define VEC_CONFIG2_UV_DIG_DIS BIT(6) 134 #define VEC_CONFIG2_RGB_DIG_DIS BIT(5) 135 #define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2) 136 #define VEC_CONFIG2_TMUX_DRIVE0 (0 << 2) 137 #define VEC_CONFIG2_TMUX_RG_COMP (1 << 2) 138 #define VEC_CONFIG2_TMUX_UV_YC (2 << 2) 139 #define VEC_CONFIG2_TMUX_SYNC_YC (3 << 2) 140 141 #define VEC_INTERRUPT_CONTROL 0x190 142 #define VEC_INTERRUPT_STATUS 0x194 143 144 /* 145 * Db center frequency for SECAM; the clock for this is the same as for 146 * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency. 147 * 148 * This is specified as 4250000 Hz, which corresponds to 0x284BDA13. 149 * That is also the default value, so no need to set it explicitly. 150 */ 151 #define VEC_FCW_SECAM_B 0x198 152 #define VEC_SECAM_GAIN_VAL 0x19c 153 154 #define VEC_CONFIG3 0x1a0 155 #define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0) 156 #define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0) 157 #define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1) 158 159 #define VEC_STATUS0 0x200 160 #define VEC_MASK0 0x204 161 162 #define VEC_CFG 0x208 163 #define VEC_CFG_SG_MODE_MASK GENMASK(6, 5) 164 #define VEC_CFG_SG_MODE(x) ((x) << 5) 165 #define VEC_CFG_SG_EN BIT(4) 166 #define VEC_CFG_VEC_EN BIT(3) 167 #define VEC_CFG_MB_EN BIT(2) 168 #define VEC_CFG_ENABLE BIT(1) 169 #define VEC_CFG_TB_EN BIT(0) 170 171 #define VEC_DAC_TEST 0x20c 172 173 #define VEC_DAC_CONFIG 0x210 174 #define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24) 175 #define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16) 176 #define VEC_DAC_CONFIG_DAC_CTRL(x) (x) 177 178 #define VEC_DAC_MISC 0x214 179 #define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16) 180 #define VEC_DAC_MISC_VCD_CTRL(x) ((x) << 16) 181 #define VEC_DAC_MISC_VID_ACT BIT(8) 182 #define VEC_DAC_MISC_VCD_PWRDN BIT(6) 183 #define VEC_DAC_MISC_BIAS_PWRDN BIT(5) 184 #define VEC_DAC_MISC_DAC_PWRDN BIT(2) 185 #define VEC_DAC_MISC_LDO_PWRDN BIT(1) 186 #define VEC_DAC_MISC_DAC_RST_N BIT(0) 187 188 189 struct vc4_vec_variant { 190 u32 dac_config; 191 }; 192 193 /* General VEC hardware state. */ 194 struct vc4_vec { 195 struct vc4_encoder encoder; 196 struct drm_connector connector; 197 198 struct platform_device *pdev; 199 const struct vc4_vec_variant *variant; 200 201 void __iomem *regs; 202 203 struct clk *clock; 204 205 struct drm_property *legacy_tv_mode_property; 206 207 struct debugfs_regset32 regset; 208 }; 209 210 #define VEC_READ(offset) \ 211 ({ \ 212 kunit_fail_current_test("Accessing a register in a unit test!\n"); \ 213 readl(vec->regs + (offset)); \ 214 }) 215 216 #define VEC_WRITE(offset, val) \ 217 do { \ 218 kunit_fail_current_test("Accessing a register in a unit test!\n"); \ 219 writel(val, vec->regs + (offset)); \ 220 } while (0) 221 222 static inline struct vc4_vec * 223 encoder_to_vc4_vec(struct drm_encoder *encoder) 224 { 225 return container_of(encoder, struct vc4_vec, encoder.base); 226 } 227 228 static inline struct vc4_vec * 229 connector_to_vc4_vec(struct drm_connector *connector) 230 { 231 return container_of(connector, struct vc4_vec, connector); 232 } 233 234 enum vc4_vec_tv_mode_id { 235 VC4_VEC_TV_MODE_NTSC, 236 VC4_VEC_TV_MODE_NTSC_J, 237 VC4_VEC_TV_MODE_PAL, 238 VC4_VEC_TV_MODE_PAL_M, 239 VC4_VEC_TV_MODE_NTSC_443, 240 VC4_VEC_TV_MODE_PAL_60, 241 VC4_VEC_TV_MODE_PAL_N, 242 VC4_VEC_TV_MODE_SECAM, 243 }; 244 245 struct vc4_vec_tv_mode { 246 unsigned int mode; 247 u16 expected_htotal; 248 u32 config0; 249 u32 config1; 250 u32 custom_freq; 251 }; 252 253 static const struct debugfs_reg32 vec_regs[] = { 254 VC4_REG32(VEC_WSE_CONTROL), 255 VC4_REG32(VEC_WSE_WSS_DATA), 256 VC4_REG32(VEC_WSE_VPS_DATA1), 257 VC4_REG32(VEC_WSE_VPS_CONTROL), 258 VC4_REG32(VEC_REVID), 259 VC4_REG32(VEC_CONFIG0), 260 VC4_REG32(VEC_SCHPH), 261 VC4_REG32(VEC_CLMP0_START), 262 VC4_REG32(VEC_CLMP0_END), 263 VC4_REG32(VEC_FREQ3_2), 264 VC4_REG32(VEC_FREQ1_0), 265 VC4_REG32(VEC_CONFIG1), 266 VC4_REG32(VEC_CONFIG2), 267 VC4_REG32(VEC_INTERRUPT_CONTROL), 268 VC4_REG32(VEC_INTERRUPT_STATUS), 269 VC4_REG32(VEC_FCW_SECAM_B), 270 VC4_REG32(VEC_SECAM_GAIN_VAL), 271 VC4_REG32(VEC_CONFIG3), 272 VC4_REG32(VEC_STATUS0), 273 VC4_REG32(VEC_MASK0), 274 VC4_REG32(VEC_CFG), 275 VC4_REG32(VEC_DAC_TEST), 276 VC4_REG32(VEC_DAC_CONFIG), 277 VC4_REG32(VEC_DAC_MISC), 278 }; 279 280 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { 281 { 282 .mode = DRM_MODE_TV_MODE_NTSC, 283 .expected_htotal = 858, 284 .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN, 285 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 286 }, 287 { 288 .mode = DRM_MODE_TV_MODE_NTSC_443, 289 .expected_htotal = 858, 290 .config0 = VEC_CONFIG0_NTSC_STD, 291 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, 292 .custom_freq = 0x2a098acb, 293 }, 294 { 295 .mode = DRM_MODE_TV_MODE_NTSC_J, 296 .expected_htotal = 858, 297 .config0 = VEC_CONFIG0_NTSC_STD, 298 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 299 }, 300 { 301 .mode = DRM_MODE_TV_MODE_PAL, 302 .expected_htotal = 864, 303 .config0 = VEC_CONFIG0_PAL_BDGHI_STD, 304 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 305 }, 306 { 307 /* PAL-60 */ 308 .mode = DRM_MODE_TV_MODE_PAL, 309 .expected_htotal = 858, 310 .config0 = VEC_CONFIG0_PAL_M_STD, 311 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, 312 .custom_freq = 0x2a098acb, 313 }, 314 { 315 .mode = DRM_MODE_TV_MODE_PAL_M, 316 .expected_htotal = 858, 317 .config0 = VEC_CONFIG0_PAL_M_STD, 318 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 319 }, 320 { 321 .mode = DRM_MODE_TV_MODE_PAL_N, 322 .expected_htotal = 864, 323 .config0 = VEC_CONFIG0_PAL_N_STD, 324 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 325 }, 326 { 327 .mode = DRM_MODE_TV_MODE_SECAM, 328 .expected_htotal = 864, 329 .config0 = VEC_CONFIG0_SECAM_STD, 330 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 331 .custom_freq = 0x29c71c72, 332 }, 333 }; 334 335 static inline const struct vc4_vec_tv_mode * 336 vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal) 337 { 338 unsigned int i; 339 340 for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) { 341 const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i]; 342 343 if (tv_mode->mode == mode && 344 tv_mode->expected_htotal == htotal) 345 return tv_mode; 346 } 347 348 return NULL; 349 } 350 351 static const struct drm_prop_enum_list legacy_tv_mode_names[] = { 352 { VC4_VEC_TV_MODE_NTSC, "NTSC", }, 353 { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", }, 354 { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", }, 355 { VC4_VEC_TV_MODE_PAL, "PAL", }, 356 { VC4_VEC_TV_MODE_PAL_60, "PAL-60", }, 357 { VC4_VEC_TV_MODE_PAL_M, "PAL-M", }, 358 { VC4_VEC_TV_MODE_PAL_N, "PAL-N", }, 359 { VC4_VEC_TV_MODE_SECAM, "SECAM", }, 360 }; 361 362 static enum drm_connector_status 363 vc4_vec_connector_detect(struct drm_connector *connector, bool force) 364 { 365 return connector_status_unknown; 366 } 367 368 static void vc4_vec_connector_reset(struct drm_connector *connector) 369 { 370 drm_atomic_helper_connector_reset(connector); 371 drm_atomic_helper_connector_tv_reset(connector); 372 } 373 374 static int 375 vc4_vec_connector_set_property(struct drm_connector *connector, 376 struct drm_connector_state *state, 377 struct drm_property *property, 378 uint64_t val) 379 { 380 struct vc4_vec *vec = connector_to_vc4_vec(connector); 381 382 if (property != vec->legacy_tv_mode_property) 383 return -EINVAL; 384 385 switch (val) { 386 case VC4_VEC_TV_MODE_NTSC: 387 state->tv.mode = DRM_MODE_TV_MODE_NTSC; 388 break; 389 390 case VC4_VEC_TV_MODE_NTSC_443: 391 state->tv.mode = DRM_MODE_TV_MODE_NTSC_443; 392 break; 393 394 case VC4_VEC_TV_MODE_NTSC_J: 395 state->tv.mode = DRM_MODE_TV_MODE_NTSC_J; 396 break; 397 398 case VC4_VEC_TV_MODE_PAL: 399 case VC4_VEC_TV_MODE_PAL_60: 400 state->tv.mode = DRM_MODE_TV_MODE_PAL; 401 break; 402 403 case VC4_VEC_TV_MODE_PAL_M: 404 state->tv.mode = DRM_MODE_TV_MODE_PAL_M; 405 break; 406 407 case VC4_VEC_TV_MODE_PAL_N: 408 state->tv.mode = DRM_MODE_TV_MODE_PAL_N; 409 break; 410 411 case VC4_VEC_TV_MODE_SECAM: 412 state->tv.mode = DRM_MODE_TV_MODE_SECAM; 413 break; 414 415 default: 416 return -EINVAL; 417 } 418 419 return 0; 420 } 421 422 static int 423 vc4_vec_connector_get_property(struct drm_connector *connector, 424 const struct drm_connector_state *state, 425 struct drm_property *property, 426 uint64_t *val) 427 { 428 struct vc4_vec *vec = connector_to_vc4_vec(connector); 429 430 if (property != vec->legacy_tv_mode_property) 431 return -EINVAL; 432 433 switch (state->tv.mode) { 434 case DRM_MODE_TV_MODE_NTSC: 435 *val = VC4_VEC_TV_MODE_NTSC; 436 break; 437 438 case DRM_MODE_TV_MODE_NTSC_443: 439 *val = VC4_VEC_TV_MODE_NTSC_443; 440 break; 441 442 case DRM_MODE_TV_MODE_NTSC_J: 443 *val = VC4_VEC_TV_MODE_NTSC_J; 444 break; 445 446 case DRM_MODE_TV_MODE_PAL: 447 *val = VC4_VEC_TV_MODE_PAL; 448 break; 449 450 case DRM_MODE_TV_MODE_PAL_M: 451 *val = VC4_VEC_TV_MODE_PAL_M; 452 break; 453 454 case DRM_MODE_TV_MODE_PAL_N: 455 *val = VC4_VEC_TV_MODE_PAL_N; 456 break; 457 458 case DRM_MODE_TV_MODE_SECAM: 459 *val = VC4_VEC_TV_MODE_SECAM; 460 break; 461 462 default: 463 return -EINVAL; 464 } 465 466 return 0; 467 } 468 469 static const struct drm_connector_funcs vc4_vec_connector_funcs = { 470 .detect = vc4_vec_connector_detect, 471 .fill_modes = drm_helper_probe_single_connector_modes, 472 .reset = vc4_vec_connector_reset, 473 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 474 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 475 .atomic_get_property = vc4_vec_connector_get_property, 476 .atomic_set_property = vc4_vec_connector_set_property, 477 }; 478 479 static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = { 480 .atomic_check = drm_atomic_helper_connector_tv_check, 481 .get_modes = drm_connector_helper_tv_get_modes, 482 }; 483 484 static int vc4_vec_connector_init(struct drm_device *dev, struct vc4_vec *vec) 485 { 486 struct drm_connector *connector = &vec->connector; 487 struct drm_property *prop; 488 int ret; 489 490 connector->interlace_allowed = true; 491 492 ret = drmm_connector_init(dev, connector, &vc4_vec_connector_funcs, 493 DRM_MODE_CONNECTOR_Composite, NULL); 494 if (ret) 495 return ret; 496 497 drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs); 498 499 drm_object_attach_property(&connector->base, 500 dev->mode_config.tv_mode_property, 501 DRM_MODE_TV_MODE_NTSC); 502 503 prop = drm_property_create_enum(dev, 0, "mode", 504 legacy_tv_mode_names, 505 ARRAY_SIZE(legacy_tv_mode_names)); 506 if (!prop) 507 return -ENOMEM; 508 vec->legacy_tv_mode_property = prop; 509 510 drm_object_attach_property(&connector->base, prop, VC4_VEC_TV_MODE_NTSC); 511 512 drm_connector_attach_encoder(connector, &vec->encoder.base); 513 514 return 0; 515 } 516 517 static void vc4_vec_encoder_disable(struct drm_encoder *encoder, 518 struct drm_atomic_state *state) 519 { 520 struct drm_device *drm = encoder->dev; 521 struct vc4_vec *vec = encoder_to_vc4_vec(encoder); 522 int idx, ret; 523 524 if (!drm_dev_enter(drm, &idx)) 525 return; 526 527 VEC_WRITE(VEC_CFG, 0); 528 VEC_WRITE(VEC_DAC_MISC, 529 VEC_DAC_MISC_VCD_PWRDN | 530 VEC_DAC_MISC_BIAS_PWRDN | 531 VEC_DAC_MISC_DAC_PWRDN | 532 VEC_DAC_MISC_LDO_PWRDN); 533 534 clk_disable_unprepare(vec->clock); 535 536 ret = pm_runtime_put(&vec->pdev->dev); 537 if (ret < 0) { 538 DRM_ERROR("Failed to release power domain: %d\n", ret); 539 goto err_dev_exit; 540 } 541 542 drm_dev_exit(idx); 543 return; 544 545 err_dev_exit: 546 drm_dev_exit(idx); 547 } 548 549 static void vc4_vec_encoder_enable(struct drm_encoder *encoder, 550 struct drm_atomic_state *state) 551 { 552 struct drm_device *drm = encoder->dev; 553 struct vc4_vec *vec = encoder_to_vc4_vec(encoder); 554 struct drm_connector *connector = &vec->connector; 555 struct drm_connector_state *conn_state = 556 drm_atomic_get_new_connector_state(state, connector); 557 struct drm_display_mode *adjusted_mode = 558 &encoder->crtc->state->adjusted_mode; 559 const struct vc4_vec_tv_mode *tv_mode; 560 int idx, ret; 561 562 if (!drm_dev_enter(drm, &idx)) 563 return; 564 565 tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, 566 adjusted_mode->htotal); 567 if (!tv_mode) 568 goto err_dev_exit; 569 570 ret = pm_runtime_resume_and_get(&vec->pdev->dev); 571 if (ret < 0) { 572 DRM_ERROR("Failed to retain power domain: %d\n", ret); 573 goto err_dev_exit; 574 } 575 576 /* 577 * We need to set the clock rate each time we enable the encoder 578 * because there's a chance we share the same parent with the HDMI 579 * clock, and both drivers are requesting different rates. 580 * The good news is, these 2 encoders cannot be enabled at the same 581 * time, thus preventing incompatible rate requests. 582 */ 583 ret = clk_set_rate(vec->clock, 108000000); 584 if (ret) { 585 DRM_ERROR("Failed to set clock rate: %d\n", ret); 586 goto err_put_runtime_pm; 587 } 588 589 ret = clk_prepare_enable(vec->clock); 590 if (ret) { 591 DRM_ERROR("Failed to turn on core clock: %d\n", ret); 592 goto err_put_runtime_pm; 593 } 594 595 /* Reset the different blocks */ 596 VEC_WRITE(VEC_WSE_RESET, 1); 597 VEC_WRITE(VEC_SOFT_RESET, 1); 598 599 /* Disable the CGSM-A and WSE blocks */ 600 VEC_WRITE(VEC_WSE_CONTROL, 0); 601 602 /* Write config common to all modes. */ 603 604 /* 605 * Color subcarrier phase: phase = 360 * SCHPH / 256. 606 * 0x28 <=> 39.375 deg. 607 */ 608 VEC_WRITE(VEC_SCHPH, 0x28); 609 610 /* 611 * Reset to default values. 612 */ 613 VEC_WRITE(VEC_CLMP0_START, 0xac); 614 VEC_WRITE(VEC_CLMP0_END, 0xec); 615 VEC_WRITE(VEC_CONFIG2, 616 VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS); 617 VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD); 618 VEC_WRITE(VEC_DAC_CONFIG, vec->variant->dac_config); 619 620 /* Mask all interrupts. */ 621 VEC_WRITE(VEC_MASK0, 0); 622 623 VEC_WRITE(VEC_CONFIG0, tv_mode->config0); 624 VEC_WRITE(VEC_CONFIG1, tv_mode->config1); 625 626 if (tv_mode->custom_freq) { 627 VEC_WRITE(VEC_FREQ3_2, 628 (tv_mode->custom_freq >> 16) & 0xffff); 629 VEC_WRITE(VEC_FREQ1_0, 630 tv_mode->custom_freq & 0xffff); 631 } 632 633 VEC_WRITE(VEC_DAC_MISC, 634 VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N); 635 VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN); 636 637 drm_dev_exit(idx); 638 return; 639 640 err_put_runtime_pm: 641 pm_runtime_put(&vec->pdev->dev); 642 err_dev_exit: 643 drm_dev_exit(idx); 644 } 645 646 static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder, 647 struct drm_crtc_state *crtc_state, 648 struct drm_connector_state *conn_state) 649 { 650 const struct drm_display_mode *mode = &crtc_state->adjusted_mode; 651 const struct vc4_vec_tv_mode *tv_mode; 652 653 tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, mode->htotal); 654 if (!tv_mode) 655 return -EINVAL; 656 657 if (mode->crtc_hdisplay % 4) 658 return -EINVAL; 659 660 if (!(mode->crtc_hsync_end - mode->crtc_hsync_start)) 661 return -EINVAL; 662 663 switch (mode->htotal) { 664 /* NTSC */ 665 case 858: 666 if (mode->crtc_vtotal > 262) 667 return -EINVAL; 668 669 if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 253) 670 return -EINVAL; 671 672 if (!(mode->crtc_vsync_start - mode->crtc_vdisplay)) 673 return -EINVAL; 674 675 if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3) 676 return -EINVAL; 677 678 if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 4) 679 return -EINVAL; 680 681 break; 682 683 /* PAL/SECAM */ 684 case 864: 685 if (mode->crtc_vtotal > 312) 686 return -EINVAL; 687 688 if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 305) 689 return -EINVAL; 690 691 if (!(mode->crtc_vsync_start - mode->crtc_vdisplay)) 692 return -EINVAL; 693 694 if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3) 695 return -EINVAL; 696 697 if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 2) 698 return -EINVAL; 699 700 break; 701 702 default: 703 return -EINVAL; 704 } 705 706 return 0; 707 } 708 709 static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = { 710 .atomic_check = vc4_vec_encoder_atomic_check, 711 .atomic_disable = vc4_vec_encoder_disable, 712 .atomic_enable = vc4_vec_encoder_enable, 713 }; 714 715 static int vc4_vec_late_register(struct drm_encoder *encoder) 716 { 717 struct drm_device *drm = encoder->dev; 718 struct vc4_vec *vec = encoder_to_vc4_vec(encoder); 719 int ret; 720 721 ret = vc4_debugfs_add_regset32(drm->primary, "vec_regs", 722 &vec->regset); 723 if (ret) 724 return ret; 725 726 return 0; 727 } 728 729 static const struct drm_encoder_funcs vc4_vec_encoder_funcs = { 730 .late_register = vc4_vec_late_register, 731 }; 732 733 static const struct vc4_vec_variant bcm2835_vec_variant = { 734 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0xc) | 735 VEC_DAC_CONFIG_DRIVER_CTRL(0xc) | 736 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46) 737 }; 738 739 static const struct vc4_vec_variant bcm2711_vec_variant = { 740 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0x0) | 741 VEC_DAC_CONFIG_DRIVER_CTRL(0x80) | 742 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x61) 743 }; 744 745 static const struct of_device_id vc4_vec_dt_match[] = { 746 { .compatible = "brcm,bcm2835-vec", .data = &bcm2835_vec_variant }, 747 { .compatible = "brcm,bcm2711-vec", .data = &bcm2711_vec_variant }, 748 { /* sentinel */ }, 749 }; 750 751 static int vc4_vec_bind(struct device *dev, struct device *master, void *data) 752 { 753 struct platform_device *pdev = to_platform_device(dev); 754 struct drm_device *drm = dev_get_drvdata(master); 755 struct vc4_vec *vec; 756 int ret; 757 758 ret = drm_mode_create_tv_properties(drm, 759 BIT(DRM_MODE_TV_MODE_NTSC) | 760 BIT(DRM_MODE_TV_MODE_NTSC_443) | 761 BIT(DRM_MODE_TV_MODE_NTSC_J) | 762 BIT(DRM_MODE_TV_MODE_PAL) | 763 BIT(DRM_MODE_TV_MODE_PAL_M) | 764 BIT(DRM_MODE_TV_MODE_PAL_N) | 765 BIT(DRM_MODE_TV_MODE_SECAM)); 766 if (ret) 767 return ret; 768 769 vec = drmm_kzalloc(drm, sizeof(*vec), GFP_KERNEL); 770 if (!vec) 771 return -ENOMEM; 772 773 vec->encoder.type = VC4_ENCODER_TYPE_VEC; 774 vec->pdev = pdev; 775 vec->variant = (const struct vc4_vec_variant *) 776 of_device_get_match_data(dev); 777 vec->regs = vc4_ioremap_regs(pdev, 0); 778 if (IS_ERR(vec->regs)) 779 return PTR_ERR(vec->regs); 780 vec->regset.base = vec->regs; 781 vec->regset.regs = vec_regs; 782 vec->regset.nregs = ARRAY_SIZE(vec_regs); 783 784 vec->clock = devm_clk_get(dev, NULL); 785 if (IS_ERR(vec->clock)) { 786 ret = PTR_ERR(vec->clock); 787 if (ret != -EPROBE_DEFER) 788 DRM_ERROR("Failed to get clock: %d\n", ret); 789 return ret; 790 } 791 792 ret = devm_pm_runtime_enable(dev); 793 if (ret) 794 return ret; 795 796 ret = drmm_encoder_init(drm, &vec->encoder.base, 797 &vc4_vec_encoder_funcs, 798 DRM_MODE_ENCODER_TVDAC, 799 NULL); 800 if (ret) 801 return ret; 802 803 drm_encoder_helper_add(&vec->encoder.base, &vc4_vec_encoder_helper_funcs); 804 805 ret = vc4_vec_connector_init(drm, vec); 806 if (ret) 807 return ret; 808 809 dev_set_drvdata(dev, vec); 810 811 return 0; 812 } 813 814 static const struct component_ops vc4_vec_ops = { 815 .bind = vc4_vec_bind, 816 }; 817 818 static int vc4_vec_dev_probe(struct platform_device *pdev) 819 { 820 return component_add(&pdev->dev, &vc4_vec_ops); 821 } 822 823 static int vc4_vec_dev_remove(struct platform_device *pdev) 824 { 825 component_del(&pdev->dev, &vc4_vec_ops); 826 return 0; 827 } 828 829 struct platform_driver vc4_vec_driver = { 830 .probe = vc4_vec_dev_probe, 831 .remove = vc4_vec_dev_remove, 832 .driver = { 833 .name = "vc4_vec", 834 .of_match_table = vc4_vec_dt_match, 835 }, 836 }; 837