xref: /linux/drivers/gpu/drm/vc4/vc4_vec.c (revision 26fbb4c8c7c3ee9a4c3b4de555a8587b5a19154e) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2016 Broadcom
4  */
5 
6 /**
7  * DOC: VC4 SDTV module
8  *
9  * The VEC encoder generates PAL or NTSC composite video output.
10  *
11  * TV mode selection is done by an atomic property on the encoder,
12  * because a drm_mode_modeinfo is insufficient to distinguish between
13  * PAL and PAL-M or NTSC and NTSC-J.
14  */
15 
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_edid.h>
18 #include <drm/drm_panel.h>
19 #include <drm/drm_probe_helper.h>
20 #include <drm/drm_simple_kms_helper.h>
21 #include <linux/clk.h>
22 #include <linux/component.h>
23 #include <linux/of_graph.h>
24 #include <linux/of_platform.h>
25 #include <linux/pm_runtime.h>
26 
27 #include "vc4_drv.h"
28 #include "vc4_regs.h"
29 
30 /* WSE Registers */
31 #define VEC_WSE_RESET			0xc0
32 
33 #define VEC_WSE_CONTROL			0xc4
34 #define VEC_WSE_WSS_ENABLE		BIT(7)
35 
36 #define VEC_WSE_WSS_DATA		0xc8
37 #define VEC_WSE_VPS_DATA1		0xcc
38 #define VEC_WSE_VPS_CONTROL		0xd0
39 
40 /* VEC Registers */
41 #define VEC_REVID			0x100
42 
43 #define VEC_CONFIG0			0x104
44 #define VEC_CONFIG0_YDEL_MASK		GENMASK(28, 26)
45 #define VEC_CONFIG0_YDEL(x)		((x) << 26)
46 #define VEC_CONFIG0_CDEL_MASK		GENMASK(25, 24)
47 #define VEC_CONFIG0_CDEL(x)		((x) << 24)
48 #define VEC_CONFIG0_PBPR_FIL		BIT(18)
49 #define VEC_CONFIG0_CHROMA_GAIN_MASK	GENMASK(17, 16)
50 #define VEC_CONFIG0_CHROMA_GAIN_UNITY	(0 << 16)
51 #define VEC_CONFIG0_CHROMA_GAIN_1_32	(1 << 16)
52 #define VEC_CONFIG0_CHROMA_GAIN_1_16	(2 << 16)
53 #define VEC_CONFIG0_CHROMA_GAIN_1_8	(3 << 16)
54 #define VEC_CONFIG0_CBURST_GAIN_MASK	GENMASK(14, 13)
55 #define VEC_CONFIG0_CBURST_GAIN_UNITY	(0 << 13)
56 #define VEC_CONFIG0_CBURST_GAIN_1_128	(1 << 13)
57 #define VEC_CONFIG0_CBURST_GAIN_1_64	(2 << 13)
58 #define VEC_CONFIG0_CBURST_GAIN_1_32	(3 << 13)
59 #define VEC_CONFIG0_CHRBW1		BIT(11)
60 #define VEC_CONFIG0_CHRBW0		BIT(10)
61 #define VEC_CONFIG0_SYNCDIS		BIT(9)
62 #define VEC_CONFIG0_BURDIS		BIT(8)
63 #define VEC_CONFIG0_CHRDIS		BIT(7)
64 #define VEC_CONFIG0_PDEN		BIT(6)
65 #define VEC_CONFIG0_YCDELAY		BIT(4)
66 #define VEC_CONFIG0_RAMPEN		BIT(2)
67 #define VEC_CONFIG0_YCDIS		BIT(2)
68 #define VEC_CONFIG0_STD_MASK		GENMASK(1, 0)
69 #define VEC_CONFIG0_NTSC_STD		0
70 #define VEC_CONFIG0_PAL_BDGHI_STD	1
71 #define VEC_CONFIG0_PAL_N_STD		3
72 
73 #define VEC_SCHPH			0x108
74 #define VEC_SOFT_RESET			0x10c
75 #define VEC_CLMP0_START			0x144
76 #define VEC_CLMP0_END			0x148
77 #define VEC_FREQ3_2			0x180
78 #define VEC_FREQ1_0			0x184
79 
80 #define VEC_CONFIG1			0x188
81 #define VEC_CONFIG_VEC_RESYNC_OFF	BIT(18)
82 #define VEC_CONFIG_RGB219		BIT(17)
83 #define VEC_CONFIG_CBAR_EN		BIT(16)
84 #define VEC_CONFIG_TC_OBB		BIT(15)
85 #define VEC_CONFIG1_OUTPUT_MODE_MASK	GENMASK(12, 10)
86 #define VEC_CONFIG1_C_Y_CVBS		(0 << 10)
87 #define VEC_CONFIG1_CVBS_Y_C		(1 << 10)
88 #define VEC_CONFIG1_PR_Y_PB		(2 << 10)
89 #define VEC_CONFIG1_RGB			(4 << 10)
90 #define VEC_CONFIG1_Y_C_CVBS		(5 << 10)
91 #define VEC_CONFIG1_C_CVBS_Y		(6 << 10)
92 #define VEC_CONFIG1_C_CVBS_CVBS		(7 << 10)
93 #define VEC_CONFIG1_DIS_CHR		BIT(9)
94 #define VEC_CONFIG1_DIS_LUMA		BIT(8)
95 #define VEC_CONFIG1_YCBCR_IN		BIT(6)
96 #define VEC_CONFIG1_DITHER_TYPE_LFSR	0
97 #define VEC_CONFIG1_DITHER_TYPE_COUNTER	BIT(5)
98 #define VEC_CONFIG1_DITHER_EN		BIT(4)
99 #define VEC_CONFIG1_CYDELAY		BIT(3)
100 #define VEC_CONFIG1_LUMADIS		BIT(2)
101 #define VEC_CONFIG1_COMPDIS		BIT(1)
102 #define VEC_CONFIG1_CUSTOM_FREQ		BIT(0)
103 
104 #define VEC_CONFIG2			0x18c
105 #define VEC_CONFIG2_PROG_SCAN		BIT(15)
106 #define VEC_CONFIG2_SYNC_ADJ_MASK	GENMASK(14, 12)
107 #define VEC_CONFIG2_SYNC_ADJ(x)		(((x) / 2) << 12)
108 #define VEC_CONFIG2_PBPR_EN		BIT(10)
109 #define VEC_CONFIG2_UV_DIG_DIS		BIT(6)
110 #define VEC_CONFIG2_RGB_DIG_DIS		BIT(5)
111 #define VEC_CONFIG2_TMUX_MASK		GENMASK(3, 2)
112 #define VEC_CONFIG2_TMUX_DRIVE0		(0 << 2)
113 #define VEC_CONFIG2_TMUX_RG_COMP	(1 << 2)
114 #define VEC_CONFIG2_TMUX_UV_YC		(2 << 2)
115 #define VEC_CONFIG2_TMUX_SYNC_YC	(3 << 2)
116 
117 #define VEC_INTERRUPT_CONTROL		0x190
118 #define VEC_INTERRUPT_STATUS		0x194
119 #define VEC_FCW_SECAM_B			0x198
120 #define VEC_SECAM_GAIN_VAL		0x19c
121 
122 #define VEC_CONFIG3			0x1a0
123 #define VEC_CONFIG3_HORIZ_LEN_STD	(0 << 0)
124 #define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF	(1 << 0)
125 #define VEC_CONFIG3_SHAPE_NON_LINEAR	BIT(1)
126 
127 #define VEC_STATUS0			0x200
128 #define VEC_MASK0			0x204
129 
130 #define VEC_CFG				0x208
131 #define VEC_CFG_SG_MODE_MASK		GENMASK(6, 5)
132 #define VEC_CFG_SG_MODE(x)		((x) << 5)
133 #define VEC_CFG_SG_EN			BIT(4)
134 #define VEC_CFG_VEC_EN			BIT(3)
135 #define VEC_CFG_MB_EN			BIT(2)
136 #define VEC_CFG_ENABLE			BIT(1)
137 #define VEC_CFG_TB_EN			BIT(0)
138 
139 #define VEC_DAC_TEST			0x20c
140 
141 #define VEC_DAC_CONFIG			0x210
142 #define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x)	((x) << 24)
143 #define VEC_DAC_CONFIG_DRIVER_CTRL(x)	((x) << 16)
144 #define VEC_DAC_CONFIG_DAC_CTRL(x)	(x)
145 
146 #define VEC_DAC_MISC			0x214
147 #define VEC_DAC_MISC_VCD_CTRL_MASK	GENMASK(31, 16)
148 #define VEC_DAC_MISC_VCD_CTRL(x)	((x) << 16)
149 #define VEC_DAC_MISC_VID_ACT		BIT(8)
150 #define VEC_DAC_MISC_VCD_PWRDN		BIT(6)
151 #define VEC_DAC_MISC_BIAS_PWRDN		BIT(5)
152 #define VEC_DAC_MISC_DAC_PWRDN		BIT(2)
153 #define VEC_DAC_MISC_LDO_PWRDN		BIT(1)
154 #define VEC_DAC_MISC_DAC_RST_N		BIT(0)
155 
156 
157 /* General VEC hardware state. */
158 struct vc4_vec {
159 	struct platform_device *pdev;
160 
161 	struct drm_encoder *encoder;
162 	struct drm_connector *connector;
163 
164 	void __iomem *regs;
165 
166 	struct clk *clock;
167 
168 	const struct vc4_vec_tv_mode *tv_mode;
169 
170 	struct debugfs_regset32 regset;
171 };
172 
173 #define VEC_READ(offset) readl(vec->regs + (offset))
174 #define VEC_WRITE(offset, val) writel(val, vec->regs + (offset))
175 
176 /* VC4 VEC encoder KMS struct */
177 struct vc4_vec_encoder {
178 	struct vc4_encoder base;
179 	struct vc4_vec *vec;
180 };
181 
182 static inline struct vc4_vec_encoder *
183 to_vc4_vec_encoder(struct drm_encoder *encoder)
184 {
185 	return container_of(encoder, struct vc4_vec_encoder, base.base);
186 }
187 
188 /* VC4 VEC connector KMS struct */
189 struct vc4_vec_connector {
190 	struct drm_connector base;
191 	struct vc4_vec *vec;
192 
193 	/* Since the connector is attached to just the one encoder,
194 	 * this is the reference to it so we can do the best_encoder()
195 	 * hook.
196 	 */
197 	struct drm_encoder *encoder;
198 };
199 
200 static inline struct vc4_vec_connector *
201 to_vc4_vec_connector(struct drm_connector *connector)
202 {
203 	return container_of(connector, struct vc4_vec_connector, base);
204 }
205 
206 enum vc4_vec_tv_mode_id {
207 	VC4_VEC_TV_MODE_NTSC,
208 	VC4_VEC_TV_MODE_NTSC_J,
209 	VC4_VEC_TV_MODE_PAL,
210 	VC4_VEC_TV_MODE_PAL_M,
211 };
212 
213 struct vc4_vec_tv_mode {
214 	const struct drm_display_mode *mode;
215 	void (*mode_set)(struct vc4_vec *vec);
216 };
217 
218 static const struct debugfs_reg32 vec_regs[] = {
219 	VC4_REG32(VEC_WSE_CONTROL),
220 	VC4_REG32(VEC_WSE_WSS_DATA),
221 	VC4_REG32(VEC_WSE_VPS_DATA1),
222 	VC4_REG32(VEC_WSE_VPS_CONTROL),
223 	VC4_REG32(VEC_REVID),
224 	VC4_REG32(VEC_CONFIG0),
225 	VC4_REG32(VEC_SCHPH),
226 	VC4_REG32(VEC_CLMP0_START),
227 	VC4_REG32(VEC_CLMP0_END),
228 	VC4_REG32(VEC_FREQ3_2),
229 	VC4_REG32(VEC_FREQ1_0),
230 	VC4_REG32(VEC_CONFIG1),
231 	VC4_REG32(VEC_CONFIG2),
232 	VC4_REG32(VEC_INTERRUPT_CONTROL),
233 	VC4_REG32(VEC_INTERRUPT_STATUS),
234 	VC4_REG32(VEC_FCW_SECAM_B),
235 	VC4_REG32(VEC_SECAM_GAIN_VAL),
236 	VC4_REG32(VEC_CONFIG3),
237 	VC4_REG32(VEC_STATUS0),
238 	VC4_REG32(VEC_MASK0),
239 	VC4_REG32(VEC_CFG),
240 	VC4_REG32(VEC_DAC_TEST),
241 	VC4_REG32(VEC_DAC_CONFIG),
242 	VC4_REG32(VEC_DAC_MISC),
243 };
244 
245 static void vc4_vec_ntsc_mode_set(struct vc4_vec *vec)
246 {
247 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN);
248 	VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
249 }
250 
251 static void vc4_vec_ntsc_j_mode_set(struct vc4_vec *vec)
252 {
253 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD);
254 	VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
255 }
256 
257 static const struct drm_display_mode ntsc_mode = {
258 	DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500,
259 		 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
260 		 480, 480 + 3, 480 + 3 + 3, 480 + 3 + 3 + 16, 0,
261 		 DRM_MODE_FLAG_INTERLACE)
262 };
263 
264 static void vc4_vec_pal_mode_set(struct vc4_vec *vec)
265 {
266 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);
267 	VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
268 }
269 
270 static void vc4_vec_pal_m_mode_set(struct vc4_vec *vec)
271 {
272 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);
273 	VEC_WRITE(VEC_CONFIG1,
274 		  VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ);
275 	VEC_WRITE(VEC_FREQ3_2, 0x223b);
276 	VEC_WRITE(VEC_FREQ1_0, 0x61d1);
277 }
278 
279 static const struct drm_display_mode pal_mode = {
280 	DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500,
281 		 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
282 		 576, 576 + 2, 576 + 2 + 3, 576 + 2 + 3 + 20, 0,
283 		 DRM_MODE_FLAG_INTERLACE)
284 };
285 
286 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
287 	[VC4_VEC_TV_MODE_NTSC] = {
288 		.mode = &ntsc_mode,
289 		.mode_set = vc4_vec_ntsc_mode_set,
290 	},
291 	[VC4_VEC_TV_MODE_NTSC_J] = {
292 		.mode = &ntsc_mode,
293 		.mode_set = vc4_vec_ntsc_j_mode_set,
294 	},
295 	[VC4_VEC_TV_MODE_PAL] = {
296 		.mode = &pal_mode,
297 		.mode_set = vc4_vec_pal_mode_set,
298 	},
299 	[VC4_VEC_TV_MODE_PAL_M] = {
300 		.mode = &pal_mode,
301 		.mode_set = vc4_vec_pal_m_mode_set,
302 	},
303 };
304 
305 static enum drm_connector_status
306 vc4_vec_connector_detect(struct drm_connector *connector, bool force)
307 {
308 	return connector_status_unknown;
309 }
310 
311 static void vc4_vec_connector_destroy(struct drm_connector *connector)
312 {
313 	drm_connector_unregister(connector);
314 	drm_connector_cleanup(connector);
315 }
316 
317 static int vc4_vec_connector_get_modes(struct drm_connector *connector)
318 {
319 	struct drm_connector_state *state = connector->state;
320 	struct drm_display_mode *mode;
321 
322 	mode = drm_mode_duplicate(connector->dev,
323 				  vc4_vec_tv_modes[state->tv.mode].mode);
324 	if (!mode) {
325 		DRM_ERROR("Failed to create a new display mode\n");
326 		return -ENOMEM;
327 	}
328 
329 	drm_mode_probed_add(connector, mode);
330 
331 	return 1;
332 }
333 
334 static const struct drm_connector_funcs vc4_vec_connector_funcs = {
335 	.detect = vc4_vec_connector_detect,
336 	.fill_modes = drm_helper_probe_single_connector_modes,
337 	.destroy = vc4_vec_connector_destroy,
338 	.reset = drm_atomic_helper_connector_reset,
339 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
340 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
341 };
342 
343 static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = {
344 	.get_modes = vc4_vec_connector_get_modes,
345 };
346 
347 static struct drm_connector *vc4_vec_connector_init(struct drm_device *dev,
348 						    struct vc4_vec *vec)
349 {
350 	struct drm_connector *connector = NULL;
351 	struct vc4_vec_connector *vec_connector;
352 
353 	vec_connector = devm_kzalloc(dev->dev, sizeof(*vec_connector),
354 				     GFP_KERNEL);
355 	if (!vec_connector)
356 		return ERR_PTR(-ENOMEM);
357 
358 	connector = &vec_connector->base;
359 	connector->interlace_allowed = true;
360 
361 	vec_connector->encoder = vec->encoder;
362 	vec_connector->vec = vec;
363 
364 	drm_connector_init(dev, connector, &vc4_vec_connector_funcs,
365 			   DRM_MODE_CONNECTOR_Composite);
366 	drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs);
367 
368 	drm_object_attach_property(&connector->base,
369 				   dev->mode_config.tv_mode_property,
370 				   VC4_VEC_TV_MODE_NTSC);
371 	vec->tv_mode = &vc4_vec_tv_modes[VC4_VEC_TV_MODE_NTSC];
372 
373 	drm_connector_attach_encoder(connector, vec->encoder);
374 
375 	return connector;
376 }
377 
378 static void vc4_vec_encoder_disable(struct drm_encoder *encoder)
379 {
380 	struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
381 	struct vc4_vec *vec = vc4_vec_encoder->vec;
382 	int ret;
383 
384 	VEC_WRITE(VEC_CFG, 0);
385 	VEC_WRITE(VEC_DAC_MISC,
386 		  VEC_DAC_MISC_VCD_PWRDN |
387 		  VEC_DAC_MISC_BIAS_PWRDN |
388 		  VEC_DAC_MISC_DAC_PWRDN |
389 		  VEC_DAC_MISC_LDO_PWRDN);
390 
391 	clk_disable_unprepare(vec->clock);
392 
393 	ret = pm_runtime_put(&vec->pdev->dev);
394 	if (ret < 0) {
395 		DRM_ERROR("Failed to release power domain: %d\n", ret);
396 		return;
397 	}
398 }
399 
400 static void vc4_vec_encoder_enable(struct drm_encoder *encoder)
401 {
402 	struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
403 	struct vc4_vec *vec = vc4_vec_encoder->vec;
404 	int ret;
405 
406 	ret = pm_runtime_get_sync(&vec->pdev->dev);
407 	if (ret < 0) {
408 		DRM_ERROR("Failed to retain power domain: %d\n", ret);
409 		return;
410 	}
411 
412 	/*
413 	 * We need to set the clock rate each time we enable the encoder
414 	 * because there's a chance we share the same parent with the HDMI
415 	 * clock, and both drivers are requesting different rates.
416 	 * The good news is, these 2 encoders cannot be enabled at the same
417 	 * time, thus preventing incompatible rate requests.
418 	 */
419 	ret = clk_set_rate(vec->clock, 108000000);
420 	if (ret) {
421 		DRM_ERROR("Failed to set clock rate: %d\n", ret);
422 		return;
423 	}
424 
425 	ret = clk_prepare_enable(vec->clock);
426 	if (ret) {
427 		DRM_ERROR("Failed to turn on core clock: %d\n", ret);
428 		return;
429 	}
430 
431 	/* Reset the different blocks */
432 	VEC_WRITE(VEC_WSE_RESET, 1);
433 	VEC_WRITE(VEC_SOFT_RESET, 1);
434 
435 	/* Disable the CGSM-A and WSE blocks */
436 	VEC_WRITE(VEC_WSE_CONTROL, 0);
437 
438 	/* Write config common to all modes. */
439 
440 	/*
441 	 * Color subcarrier phase: phase = 360 * SCHPH / 256.
442 	 * 0x28 <=> 39.375 deg.
443 	 */
444 	VEC_WRITE(VEC_SCHPH, 0x28);
445 
446 	/*
447 	 * Reset to default values.
448 	 */
449 	VEC_WRITE(VEC_CLMP0_START, 0xac);
450 	VEC_WRITE(VEC_CLMP0_END, 0xec);
451 	VEC_WRITE(VEC_CONFIG2,
452 		  VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS);
453 	VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);
454 	VEC_WRITE(VEC_DAC_CONFIG,
455 		  VEC_DAC_CONFIG_DAC_CTRL(0xc) |
456 		  VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |
457 		  VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46));
458 
459 	/* Mask all interrupts. */
460 	VEC_WRITE(VEC_MASK0, 0);
461 
462 	vec->tv_mode->mode_set(vec);
463 
464 	VEC_WRITE(VEC_DAC_MISC,
465 		  VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N);
466 	VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);
467 }
468 
469 
470 static bool vc4_vec_encoder_mode_fixup(struct drm_encoder *encoder,
471 				       const struct drm_display_mode *mode,
472 				       struct drm_display_mode *adjusted_mode)
473 {
474 	return true;
475 }
476 
477 static void vc4_vec_encoder_atomic_mode_set(struct drm_encoder *encoder,
478 					struct drm_crtc_state *crtc_state,
479 					struct drm_connector_state *conn_state)
480 {
481 	struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
482 	struct vc4_vec *vec = vc4_vec_encoder->vec;
483 
484 	vec->tv_mode = &vc4_vec_tv_modes[conn_state->tv.mode];
485 }
486 
487 static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
488 					struct drm_crtc_state *crtc_state,
489 					struct drm_connector_state *conn_state)
490 {
491 	const struct vc4_vec_tv_mode *vec_mode;
492 
493 	vec_mode = &vc4_vec_tv_modes[conn_state->tv.mode];
494 
495 	if (conn_state->crtc &&
496 	    !drm_mode_equal(vec_mode->mode, &crtc_state->adjusted_mode))
497 		return -EINVAL;
498 
499 	return 0;
500 }
501 
502 static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = {
503 	.disable = vc4_vec_encoder_disable,
504 	.enable = vc4_vec_encoder_enable,
505 	.mode_fixup = vc4_vec_encoder_mode_fixup,
506 	.atomic_check = vc4_vec_encoder_atomic_check,
507 	.atomic_mode_set = vc4_vec_encoder_atomic_mode_set,
508 };
509 
510 static const struct of_device_id vc4_vec_dt_match[] = {
511 	{ .compatible = "brcm,bcm2835-vec", .data = NULL },
512 	{ /* sentinel */ },
513 };
514 
515 static const char * const tv_mode_names[] = {
516 	[VC4_VEC_TV_MODE_NTSC] = "NTSC",
517 	[VC4_VEC_TV_MODE_NTSC_J] = "NTSC-J",
518 	[VC4_VEC_TV_MODE_PAL] = "PAL",
519 	[VC4_VEC_TV_MODE_PAL_M] = "PAL-M",
520 };
521 
522 static int vc4_vec_bind(struct device *dev, struct device *master, void *data)
523 {
524 	struct platform_device *pdev = to_platform_device(dev);
525 	struct drm_device *drm = dev_get_drvdata(master);
526 	struct vc4_dev *vc4 = to_vc4_dev(drm);
527 	struct vc4_vec *vec;
528 	struct vc4_vec_encoder *vc4_vec_encoder;
529 	int ret;
530 
531 	ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(tv_mode_names),
532 					    tv_mode_names);
533 	if (ret)
534 		return ret;
535 
536 	vec = devm_kzalloc(dev, sizeof(*vec), GFP_KERNEL);
537 	if (!vec)
538 		return -ENOMEM;
539 
540 	vc4_vec_encoder = devm_kzalloc(dev, sizeof(*vc4_vec_encoder),
541 				       GFP_KERNEL);
542 	if (!vc4_vec_encoder)
543 		return -ENOMEM;
544 	vc4_vec_encoder->base.type = VC4_ENCODER_TYPE_VEC;
545 	vc4_vec_encoder->vec = vec;
546 	vec->encoder = &vc4_vec_encoder->base.base;
547 
548 	vec->pdev = pdev;
549 	vec->regs = vc4_ioremap_regs(pdev, 0);
550 	if (IS_ERR(vec->regs))
551 		return PTR_ERR(vec->regs);
552 	vec->regset.base = vec->regs;
553 	vec->regset.regs = vec_regs;
554 	vec->regset.nregs = ARRAY_SIZE(vec_regs);
555 
556 	vec->clock = devm_clk_get(dev, NULL);
557 	if (IS_ERR(vec->clock)) {
558 		ret = PTR_ERR(vec->clock);
559 		if (ret != -EPROBE_DEFER)
560 			DRM_ERROR("Failed to get clock: %d\n", ret);
561 		return ret;
562 	}
563 
564 	pm_runtime_enable(dev);
565 
566 	drm_simple_encoder_init(drm, vec->encoder, DRM_MODE_ENCODER_TVDAC);
567 	drm_encoder_helper_add(vec->encoder, &vc4_vec_encoder_helper_funcs);
568 
569 	vec->connector = vc4_vec_connector_init(drm, vec);
570 	if (IS_ERR(vec->connector)) {
571 		ret = PTR_ERR(vec->connector);
572 		goto err_destroy_encoder;
573 	}
574 
575 	dev_set_drvdata(dev, vec);
576 
577 	vc4->vec = vec;
578 
579 	vc4_debugfs_add_regset32(drm, "vec_regs", &vec->regset);
580 
581 	return 0;
582 
583 err_destroy_encoder:
584 	drm_encoder_cleanup(vec->encoder);
585 	pm_runtime_disable(dev);
586 
587 	return ret;
588 }
589 
590 static void vc4_vec_unbind(struct device *dev, struct device *master,
591 			   void *data)
592 {
593 	struct drm_device *drm = dev_get_drvdata(master);
594 	struct vc4_dev *vc4 = to_vc4_dev(drm);
595 	struct vc4_vec *vec = dev_get_drvdata(dev);
596 
597 	vc4_vec_connector_destroy(vec->connector);
598 	drm_encoder_cleanup(vec->encoder);
599 	pm_runtime_disable(dev);
600 
601 	vc4->vec = NULL;
602 }
603 
604 static const struct component_ops vc4_vec_ops = {
605 	.bind   = vc4_vec_bind,
606 	.unbind = vc4_vec_unbind,
607 };
608 
609 static int vc4_vec_dev_probe(struct platform_device *pdev)
610 {
611 	return component_add(&pdev->dev, &vc4_vec_ops);
612 }
613 
614 static int vc4_vec_dev_remove(struct platform_device *pdev)
615 {
616 	component_del(&pdev->dev, &vc4_vec_ops);
617 	return 0;
618 }
619 
620 struct platform_driver vc4_vec_driver = {
621 	.probe = vc4_vec_dev_probe,
622 	.remove = vc4_vec_dev_remove,
623 	.driver = {
624 		.name = "vc4_vec",
625 		.of_match_table = vc4_vec_dt_match,
626 	},
627 };
628