1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/timer.h> 13 14 #include <drm/drm_print.h> 15 16 #include "vc4_drv.h" 17 #include "vc4_regs.h" 18 19 static const struct debugfs_reg32 v3d_regs[] = { 20 VC4_REG32(V3D_IDENT0), 21 VC4_REG32(V3D_IDENT1), 22 VC4_REG32(V3D_IDENT2), 23 VC4_REG32(V3D_SCRATCH), 24 VC4_REG32(V3D_L2CACTL), 25 VC4_REG32(V3D_SLCACTL), 26 VC4_REG32(V3D_INTCTL), 27 VC4_REG32(V3D_INTENA), 28 VC4_REG32(V3D_INTDIS), 29 VC4_REG32(V3D_CT0CS), 30 VC4_REG32(V3D_CT1CS), 31 VC4_REG32(V3D_CT0EA), 32 VC4_REG32(V3D_CT1EA), 33 VC4_REG32(V3D_CT0CA), 34 VC4_REG32(V3D_CT1CA), 35 VC4_REG32(V3D_CT00RA0), 36 VC4_REG32(V3D_CT01RA0), 37 VC4_REG32(V3D_CT0LC), 38 VC4_REG32(V3D_CT1LC), 39 VC4_REG32(V3D_CT0PC), 40 VC4_REG32(V3D_CT1PC), 41 VC4_REG32(V3D_PCS), 42 VC4_REG32(V3D_BFC), 43 VC4_REG32(V3D_RFC), 44 VC4_REG32(V3D_BPCA), 45 VC4_REG32(V3D_BPCS), 46 VC4_REG32(V3D_BPOA), 47 VC4_REG32(V3D_BPOS), 48 VC4_REG32(V3D_BXCF), 49 VC4_REG32(V3D_SQRSV0), 50 VC4_REG32(V3D_SQRSV1), 51 VC4_REG32(V3D_SQCNTL), 52 VC4_REG32(V3D_SRQPC), 53 VC4_REG32(V3D_SRQUA), 54 VC4_REG32(V3D_SRQUL), 55 VC4_REG32(V3D_SRQCS), 56 VC4_REG32(V3D_VPACNTL), 57 VC4_REG32(V3D_VPMBASE), 58 VC4_REG32(V3D_PCTRC), 59 VC4_REG32(V3D_PCTRE), 60 VC4_REG32(V3D_PCTR(0)), 61 VC4_REG32(V3D_PCTRS(0)), 62 VC4_REG32(V3D_PCTR(1)), 63 VC4_REG32(V3D_PCTRS(1)), 64 VC4_REG32(V3D_PCTR(2)), 65 VC4_REG32(V3D_PCTRS(2)), 66 VC4_REG32(V3D_PCTR(3)), 67 VC4_REG32(V3D_PCTRS(3)), 68 VC4_REG32(V3D_PCTR(4)), 69 VC4_REG32(V3D_PCTRS(4)), 70 VC4_REG32(V3D_PCTR(5)), 71 VC4_REG32(V3D_PCTRS(5)), 72 VC4_REG32(V3D_PCTR(6)), 73 VC4_REG32(V3D_PCTRS(6)), 74 VC4_REG32(V3D_PCTR(7)), 75 VC4_REG32(V3D_PCTRS(7)), 76 VC4_REG32(V3D_PCTR(8)), 77 VC4_REG32(V3D_PCTRS(8)), 78 VC4_REG32(V3D_PCTR(9)), 79 VC4_REG32(V3D_PCTRS(9)), 80 VC4_REG32(V3D_PCTR(10)), 81 VC4_REG32(V3D_PCTRS(10)), 82 VC4_REG32(V3D_PCTR(11)), 83 VC4_REG32(V3D_PCTRS(11)), 84 VC4_REG32(V3D_PCTR(12)), 85 VC4_REG32(V3D_PCTRS(12)), 86 VC4_REG32(V3D_PCTR(13)), 87 VC4_REG32(V3D_PCTRS(13)), 88 VC4_REG32(V3D_PCTR(14)), 89 VC4_REG32(V3D_PCTRS(14)), 90 VC4_REG32(V3D_PCTR(15)), 91 VC4_REG32(V3D_PCTRS(15)), 92 VC4_REG32(V3D_DBGE), 93 VC4_REG32(V3D_FDBGO), 94 VC4_REG32(V3D_FDBGB), 95 VC4_REG32(V3D_FDBGR), 96 VC4_REG32(V3D_FDBGS), 97 VC4_REG32(V3D_ERRSTAT), 98 }; 99 100 static int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused) 101 { 102 struct drm_debugfs_entry *entry = m->private; 103 struct drm_device *dev = entry->dev; 104 struct vc4_dev *vc4 = to_vc4_dev(dev); 105 int ret = vc4_v3d_pm_get(vc4); 106 107 if (ret == 0) { 108 uint32_t ident1 = V3D_READ(V3D_IDENT1); 109 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC); 110 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS); 111 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS); 112 113 seq_printf(m, "Revision: %d\n", 114 VC4_GET_FIELD(ident1, V3D_IDENT1_REV)); 115 seq_printf(m, "Slices: %d\n", nslc); 116 seq_printf(m, "TMUs: %d\n", nslc * tups); 117 seq_printf(m, "QPUs: %d\n", nslc * qups); 118 seq_printf(m, "Semaphores: %d\n", 119 VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM)); 120 vc4_v3d_pm_put(vc4); 121 } 122 123 return 0; 124 } 125 126 /* 127 * Wraps pm_runtime_get_sync() in a refcount, so that we can reliably 128 * get the pm_runtime refcount to 0 in vc4_reset(). 129 */ 130 int 131 vc4_v3d_pm_get(struct vc4_dev *vc4) 132 { 133 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 134 return -ENODEV; 135 136 mutex_lock(&vc4->power_lock); 137 if (vc4->power_refcount++ == 0) { 138 int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev); 139 140 if (ret < 0) { 141 vc4->power_refcount--; 142 mutex_unlock(&vc4->power_lock); 143 return ret; 144 } 145 } 146 mutex_unlock(&vc4->power_lock); 147 148 return 0; 149 } 150 151 void 152 vc4_v3d_pm_put(struct vc4_dev *vc4) 153 { 154 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 155 return; 156 157 mutex_lock(&vc4->power_lock); 158 if (--vc4->power_refcount == 0) { 159 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev); 160 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev); 161 } 162 mutex_unlock(&vc4->power_lock); 163 } 164 165 static void vc4_v3d_init_hw(struct drm_device *dev) 166 { 167 struct vc4_dev *vc4 = to_vc4_dev(dev); 168 169 /* Take all the memory that would have been reserved for user 170 * QPU programs, since we don't have an interface for running 171 * them, anyway. 172 */ 173 V3D_WRITE(V3D_VPMBASE, 0); 174 } 175 176 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4) 177 { 178 struct drm_device *dev = &vc4->base; 179 unsigned long irqflags; 180 int slot; 181 uint64_t seqno = 0; 182 struct vc4_exec_info *exec; 183 184 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 185 return -ENODEV; 186 187 try_again: 188 spin_lock_irqsave(&vc4->job_lock, irqflags); 189 slot = ffs(~vc4->bin_alloc_used); 190 if (slot != 0) { 191 /* Switch from ffs() bit index to a 0-based index. */ 192 slot--; 193 vc4->bin_alloc_used |= BIT(slot); 194 spin_unlock_irqrestore(&vc4->job_lock, irqflags); 195 return slot; 196 } 197 198 /* Couldn't find an open slot. Wait for render to complete 199 * and try again. 200 */ 201 exec = vc4_last_render_job(vc4); 202 if (exec) 203 seqno = exec->seqno; 204 spin_unlock_irqrestore(&vc4->job_lock, irqflags); 205 206 if (seqno) { 207 int ret = vc4_wait_for_seqno(dev, seqno, ~0ull, true); 208 209 if (ret == 0) 210 goto try_again; 211 212 return ret; 213 } 214 215 return -ENOMEM; 216 } 217 218 /* 219 * bin_bo_alloc() - allocates the memory that will be used for 220 * tile binning. 221 * 222 * The binner has a limitation that the addresses in the tile state 223 * buffer that point into the tile alloc buffer or binner overflow 224 * memory only have 28 bits (256MB), and the top 4 on the bus for 225 * tile alloc references end up coming from the tile state buffer's 226 * address. 227 * 228 * To work around this, we allocate a single large buffer while V3D is 229 * in use, make sure that it has the top 4 bits constant across its 230 * entire extent, and then put the tile state, tile alloc, and binner 231 * overflow memory inside that buffer. 232 * 233 * This creates a limitation where we may not be able to execute a job 234 * if it doesn't fit within the buffer that we allocated up front. 235 * However, it turns out that 16MB is "enough for anybody", and 236 * real-world applications run into allocation failures from the 237 * overall DMA pool before they make scenes complicated enough to run 238 * out of bin space. 239 */ 240 static int bin_bo_alloc(struct vc4_dev *vc4) 241 { 242 struct vc4_v3d *v3d = vc4->v3d; 243 uint32_t size = 16 * 1024 * 1024; 244 int ret = 0; 245 struct list_head list; 246 247 if (!v3d) 248 return -ENODEV; 249 250 /* We may need to try allocating more than once to get a BO 251 * that doesn't cross 256MB. Track the ones we've allocated 252 * that failed so far, so that we can free them when we've got 253 * one that succeeded (if we freed them right away, our next 254 * allocation would probably be the same chunk of memory). 255 */ 256 INIT_LIST_HEAD(&list); 257 258 while (true) { 259 struct vc4_bo *bo = vc4_bo_create(&vc4->base, size, true, 260 VC4_BO_TYPE_BIN); 261 262 if (IS_ERR(bo)) { 263 ret = PTR_ERR(bo); 264 265 dev_err(&v3d->pdev->dev, 266 "Failed to allocate memory for tile binning: " 267 "%d. You may need to enable DMA or give it " 268 "more memory.", 269 ret); 270 break; 271 } 272 273 /* Check if this BO won't trigger the addressing bug. */ 274 if ((bo->base.dma_addr & 0xf0000000) == 275 ((bo->base.dma_addr + bo->base.base.size - 1) & 0xf0000000)) { 276 vc4->bin_bo = bo; 277 278 /* Set up for allocating 512KB chunks of 279 * binner memory. The biggest allocation we 280 * need to do is for the initial tile alloc + 281 * tile state buffer. We can render to a 282 * maximum of ((2048*2048) / (32*32) = 4096 283 * tiles in a frame (until we do floating 284 * point rendering, at which point it would be 285 * 8192). Tile state is 48b/tile (rounded to 286 * a page), and tile alloc is 32b/tile 287 * (rounded to a page), plus a page of extra, 288 * for a total of 320kb for our worst-case. 289 * We choose 512kb so that it divides evenly 290 * into our 16MB, and the rest of the 512kb 291 * will be used as storage for the overflow 292 * from the initial 32b CL per bin. 293 */ 294 vc4->bin_alloc_size = 512 * 1024; 295 vc4->bin_alloc_used = 0; 296 vc4->bin_alloc_overflow = 0; 297 WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 != 298 bo->base.base.size / vc4->bin_alloc_size); 299 300 kref_init(&vc4->bin_bo_kref); 301 302 /* Enable the out-of-memory interrupt to set our 303 * newly-allocated binner BO, potentially from an 304 * already-pending-but-masked interrupt. 305 */ 306 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); 307 308 break; 309 } 310 311 /* Put it on the list to free later, and try again. */ 312 list_add(&bo->unref_head, &list); 313 } 314 315 /* Free all the BOs we allocated but didn't choose. */ 316 while (!list_empty(&list)) { 317 struct vc4_bo *bo = list_last_entry(&list, 318 struct vc4_bo, unref_head); 319 320 list_del(&bo->unref_head); 321 drm_gem_object_put(&bo->base.base); 322 } 323 324 return ret; 325 } 326 327 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used) 328 { 329 int ret = 0; 330 331 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 332 return -ENODEV; 333 334 mutex_lock(&vc4->bin_bo_lock); 335 336 if (used && *used) 337 goto complete; 338 339 if (vc4->bin_bo) 340 kref_get(&vc4->bin_bo_kref); 341 else 342 ret = bin_bo_alloc(vc4); 343 344 if (ret == 0 && used) 345 *used = true; 346 347 complete: 348 mutex_unlock(&vc4->bin_bo_lock); 349 350 return ret; 351 } 352 353 static void bin_bo_release(struct kref *ref) 354 { 355 struct vc4_dev *vc4 = container_of(ref, struct vc4_dev, bin_bo_kref); 356 357 if (WARN_ON_ONCE(!vc4->bin_bo)) 358 return; 359 360 drm_gem_object_put(&vc4->bin_bo->base.base); 361 vc4->bin_bo = NULL; 362 } 363 364 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4) 365 { 366 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 367 return; 368 369 mutex_lock(&vc4->bin_bo_lock); 370 kref_put(&vc4->bin_bo_kref, bin_bo_release); 371 mutex_unlock(&vc4->bin_bo_lock); 372 } 373 374 #ifdef CONFIG_PM 375 static int vc4_v3d_runtime_suspend(struct device *dev) 376 { 377 struct vc4_v3d *v3d = dev_get_drvdata(dev); 378 struct vc4_dev *vc4 = v3d->vc4; 379 380 vc4_irq_disable(&vc4->base); 381 382 clk_disable_unprepare(v3d->clk); 383 384 return 0; 385 } 386 387 static int vc4_v3d_runtime_resume(struct device *dev) 388 { 389 struct vc4_v3d *v3d = dev_get_drvdata(dev); 390 struct vc4_dev *vc4 = v3d->vc4; 391 int ret; 392 393 ret = clk_prepare_enable(v3d->clk); 394 if (ret != 0) 395 return ret; 396 397 vc4_v3d_init_hw(&vc4->base); 398 399 vc4_irq_enable(&vc4->base); 400 401 return 0; 402 } 403 #endif 404 405 int vc4_v3d_debugfs_init(struct drm_minor *minor) 406 { 407 struct drm_device *drm = minor->dev; 408 struct vc4_dev *vc4 = to_vc4_dev(drm); 409 struct vc4_v3d *v3d = vc4->v3d; 410 411 if (!vc4->v3d) 412 return -ENODEV; 413 414 drm_debugfs_add_file(drm, "v3d_ident", vc4_v3d_debugfs_ident, NULL); 415 416 vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset); 417 418 return 0; 419 } 420 421 static int vc4_v3d_bind(struct device *dev, struct device *master, void *data) 422 { 423 struct platform_device *pdev = to_platform_device(dev); 424 struct drm_device *drm = dev_get_drvdata(master); 425 struct vc4_dev *vc4 = to_vc4_dev(drm); 426 struct vc4_v3d *v3d = NULL; 427 int ret; 428 429 v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL); 430 if (!v3d) 431 return -ENOMEM; 432 433 dev_set_drvdata(dev, v3d); 434 435 v3d->pdev = pdev; 436 437 v3d->regs = vc4_ioremap_regs(pdev, 0); 438 if (IS_ERR(v3d->regs)) 439 return PTR_ERR(v3d->regs); 440 v3d->regset.base = v3d->regs; 441 v3d->regset.regs = v3d_regs; 442 v3d->regset.nregs = ARRAY_SIZE(v3d_regs); 443 444 vc4->v3d = v3d; 445 v3d->vc4 = vc4; 446 447 v3d->clk = devm_clk_get_optional(dev, NULL); 448 if (IS_ERR(v3d->clk)) 449 return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n"); 450 451 ret = platform_get_irq(pdev, 0); 452 if (ret < 0) 453 return ret; 454 vc4->irq = ret; 455 456 ret = devm_pm_runtime_enable(dev); 457 if (ret) 458 return ret; 459 460 ret = pm_runtime_resume_and_get(dev); 461 if (ret) 462 return ret; 463 464 if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) { 465 drm_err(drm, "V3D_IDENT0 read 0x%08x instead of 0x%08x\n", 466 V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0); 467 ret = -EINVAL; 468 goto err_put_runtime_pm; 469 } 470 471 /* Reset the binner overflow address/size at setup, to be sure 472 * we don't reuse an old one. 473 */ 474 V3D_WRITE(V3D_BPOA, 0); 475 V3D_WRITE(V3D_BPOS, 0); 476 477 ret = vc4_irq_install(drm, vc4->irq); 478 if (ret) { 479 drm_err(drm, "Failed to install IRQ handler\n"); 480 goto err_put_runtime_pm; 481 } 482 483 pm_runtime_use_autosuspend(dev); 484 pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */ 485 pm_runtime_put_autosuspend(dev); 486 487 return 0; 488 489 err_put_runtime_pm: 490 pm_runtime_put(dev); 491 492 return ret; 493 } 494 495 static void vc4_v3d_unbind(struct device *dev, struct device *master, 496 void *data) 497 { 498 struct drm_device *drm = data; 499 struct vc4_dev *vc4 = to_vc4_dev(drm); 500 501 /* A straggler vc4_reset() re-enables the interrupt. */ 502 timer_shutdown_sync(&vc4->hangcheck.timer); 503 cancel_work_sync(&vc4->hangcheck.reset_work); 504 505 vc4_irq_uninstall(drm); 506 507 /* Flush rather than cancel, so queued completions release their jobs. */ 508 flush_work(&vc4->job_done_work); 509 510 /* Disable the binner's overflow memory address, so the next 511 * driver probe (if any) doesn't try to reuse our old 512 * allocation. 513 */ 514 V3D_WRITE(V3D_BPOA, 0); 515 V3D_WRITE(V3D_BPOS, 0); 516 517 vc4->v3d = NULL; 518 } 519 520 static const struct dev_pm_ops vc4_v3d_pm_ops = { 521 SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL) 522 }; 523 524 static const struct component_ops vc4_v3d_ops = { 525 .bind = vc4_v3d_bind, 526 .unbind = vc4_v3d_unbind, 527 }; 528 529 static int vc4_v3d_dev_probe(struct platform_device *pdev) 530 { 531 return component_add(&pdev->dev, &vc4_v3d_ops); 532 } 533 534 static void vc4_v3d_dev_remove(struct platform_device *pdev) 535 { 536 component_del(&pdev->dev, &vc4_v3d_ops); 537 } 538 539 const struct of_device_id vc4_v3d_dt_match[] = { 540 { .compatible = "brcm,bcm2835-v3d" }, 541 { .compatible = "brcm,cygnus-v3d" }, 542 { .compatible = "brcm,vc4-v3d" }, 543 {} 544 }; 545 546 struct platform_driver vc4_v3d_driver = { 547 .probe = vc4_v3d_dev_probe, 548 .remove = vc4_v3d_dev_remove, 549 .driver = { 550 .name = "vc4_v3d", 551 .of_match_table = vc4_v3d_dt_match, 552 .pm = &vc4_v3d_pm_ops, 553 }, 554 }; 555