1 /* 2 * Copyright © 2014-2015 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Render command list generation 26 * 27 * In the V3D hardware, render command lists are what load and store 28 * tiles of a framebuffer and optionally call out to binner-generated 29 * command lists to do the 3D drawing for that tile. 30 * 31 * In the VC4 driver, render command list generation is performed by the 32 * kernel instead of userspace. We do this because validating a 33 * user-submitted command list is hard to get right and has high CPU overhead, 34 * while the number of valid configurations for render command lists is 35 * actually fairly low. 36 */ 37 38 #include <drm/drm_print.h> 39 40 #include "vc4_drv.h" 41 #include "vc4_packet.h" 42 43 struct vc4_rcl_setup { 44 struct drm_gem_dma_object *color_read; 45 struct drm_gem_dma_object *color_write; 46 struct drm_gem_dma_object *zs_read; 47 struct drm_gem_dma_object *zs_write; 48 struct drm_gem_dma_object *msaa_color_write; 49 struct drm_gem_dma_object *msaa_zs_write; 50 51 struct drm_gem_dma_object *rcl; 52 u32 next_offset; 53 54 u32 next_write_bo_index; 55 }; 56 57 static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val) 58 { 59 *(u8 *)(setup->rcl->vaddr + setup->next_offset) = val; 60 setup->next_offset += 1; 61 } 62 63 static inline void rcl_u16(struct vc4_rcl_setup *setup, u16 val) 64 { 65 *(u16 *)(setup->rcl->vaddr + setup->next_offset) = val; 66 setup->next_offset += 2; 67 } 68 69 static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val) 70 { 71 *(u32 *)(setup->rcl->vaddr + setup->next_offset) = val; 72 setup->next_offset += 4; 73 } 74 75 /* 76 * Emits a no-op STORE_TILE_BUFFER_GENERAL. 77 * 78 * If we emit a PACKET_TILE_COORDINATES, it must be followed by a store of 79 * some sort before another load is triggered. 80 */ 81 static void vc4_store_before_load(struct vc4_rcl_setup *setup) 82 { 83 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); 84 rcl_u16(setup, 85 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, 86 VC4_LOADSTORE_TILE_BUFFER_BUFFER) | 87 VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR | 88 VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR | 89 VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR); 90 rcl_u32(setup, 0); /* no address, since we're in None mode */ 91 } 92 93 /* 94 * Calculates the physical address of the start of a tile in a RCL surface. 95 * 96 * Unlike the other load/store packets, 97 * VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER don't look at the tile 98 * coordinates packet, and instead just store to the address given. 99 */ 100 static uint32_t vc4_full_res_offset(struct vc4_exec_info *exec, 101 struct drm_gem_dma_object *bo, 102 struct drm_vc4_submit_rcl_surface *surf, 103 uint8_t x, uint8_t y) 104 { 105 return bo->dma_addr + surf->offset + VC4_TILE_BUFFER_SIZE * 106 (DIV_ROUND_UP(exec->args->width, 32) * y + x); 107 } 108 109 /* 110 * Emits a PACKET_TILE_COORDINATES if one isn't already pending. 111 * 112 * The tile coordinates packet triggers a pending load if there is one, are 113 * used for clipping during rendering, and determine where loads/stores happen 114 * relative to their base address. 115 */ 116 static void vc4_tile_coordinates(struct vc4_rcl_setup *setup, 117 uint32_t x, uint32_t y) 118 { 119 rcl_u8(setup, VC4_PACKET_TILE_COORDINATES); 120 rcl_u8(setup, x); 121 rcl_u8(setup, y); 122 } 123 124 static void emit_tile(struct vc4_exec_info *exec, 125 struct vc4_rcl_setup *setup, 126 uint8_t x, uint8_t y, bool first, bool last) 127 { 128 struct drm_vc4_submit_cl *args = exec->args; 129 bool has_bin = args->bin_cl_size != 0; 130 131 /* Note that the load doesn't actually occur until the 132 * tile coords packet is processed, and only one load 133 * may be outstanding at a time. 134 */ 135 if (setup->color_read) { 136 if (args->color_read.flags & 137 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 138 rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER); 139 rcl_u32(setup, 140 vc4_full_res_offset(exec, setup->color_read, 141 &args->color_read, x, y) | 142 VC4_LOADSTORE_FULL_RES_DISABLE_ZS); 143 } else { 144 rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); 145 rcl_u16(setup, args->color_read.bits); 146 rcl_u32(setup, setup->color_read->dma_addr + 147 args->color_read.offset); 148 } 149 } 150 151 if (setup->zs_read) { 152 if (setup->color_read) { 153 /* Exec previous load. */ 154 vc4_tile_coordinates(setup, x, y); 155 vc4_store_before_load(setup); 156 } 157 158 if (args->zs_read.flags & 159 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 160 rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER); 161 rcl_u32(setup, 162 vc4_full_res_offset(exec, setup->zs_read, 163 &args->zs_read, x, y) | 164 VC4_LOADSTORE_FULL_RES_DISABLE_COLOR); 165 } else { 166 rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); 167 rcl_u16(setup, args->zs_read.bits); 168 rcl_u32(setup, setup->zs_read->dma_addr + 169 args->zs_read.offset); 170 } 171 } 172 173 /* Clipping depends on tile coordinates having been 174 * emitted, so we always need one here. 175 */ 176 vc4_tile_coordinates(setup, x, y); 177 178 /* Wait for the binner before jumping to the first 179 * tile's lists. 180 */ 181 if (first && has_bin) 182 rcl_u8(setup, VC4_PACKET_WAIT_ON_SEMAPHORE); 183 184 if (has_bin) { 185 rcl_u8(setup, VC4_PACKET_BRANCH_TO_SUB_LIST); 186 rcl_u32(setup, (exec->tile_alloc_offset + 187 (y * exec->bin_tiles_x + x) * 32)); 188 } 189 190 if (setup->msaa_color_write) { 191 bool last_tile_write = (!setup->msaa_zs_write && 192 !setup->zs_write && 193 !setup->color_write); 194 uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_ZS; 195 196 if (!last_tile_write) 197 bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL; 198 else if (last) 199 bits |= VC4_LOADSTORE_FULL_RES_EOF; 200 rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER); 201 rcl_u32(setup, 202 vc4_full_res_offset(exec, setup->msaa_color_write, 203 &args->msaa_color_write, x, y) | 204 bits); 205 } 206 207 if (setup->msaa_zs_write) { 208 bool last_tile_write = (!setup->zs_write && 209 !setup->color_write); 210 uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_COLOR; 211 212 if (setup->msaa_color_write) 213 vc4_tile_coordinates(setup, x, y); 214 if (!last_tile_write) 215 bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL; 216 else if (last) 217 bits |= VC4_LOADSTORE_FULL_RES_EOF; 218 rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER); 219 rcl_u32(setup, 220 vc4_full_res_offset(exec, setup->msaa_zs_write, 221 &args->msaa_zs_write, x, y) | 222 bits); 223 } 224 225 if (setup->zs_write) { 226 bool last_tile_write = !setup->color_write; 227 228 if (setup->msaa_color_write || setup->msaa_zs_write) 229 vc4_tile_coordinates(setup, x, y); 230 231 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); 232 rcl_u16(setup, args->zs_write.bits | 233 (last_tile_write ? 234 0 : VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR)); 235 rcl_u32(setup, 236 (setup->zs_write->dma_addr + args->zs_write.offset) | 237 ((last && last_tile_write) ? 238 VC4_LOADSTORE_TILE_BUFFER_EOF : 0)); 239 } 240 241 if (setup->color_write) { 242 if (setup->msaa_color_write || setup->msaa_zs_write || 243 setup->zs_write) { 244 vc4_tile_coordinates(setup, x, y); 245 } 246 247 if (last) 248 rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF); 249 else 250 rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER); 251 } 252 } 253 254 static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, 255 struct vc4_rcl_setup *setup) 256 { 257 struct drm_vc4_submit_cl *args = exec->args; 258 bool has_bin = args->bin_cl_size != 0; 259 uint8_t min_x_tile = args->min_x_tile; 260 uint8_t min_y_tile = args->min_y_tile; 261 uint8_t max_x_tile = args->max_x_tile; 262 uint8_t max_y_tile = args->max_y_tile; 263 uint8_t xtiles = max_x_tile - min_x_tile + 1; 264 uint8_t ytiles = max_y_tile - min_y_tile + 1; 265 uint8_t xi, yi; 266 uint32_t size, loop_body_size; 267 bool positive_x = true; 268 bool positive_y = true; 269 270 if (args->flags & VC4_SUBMIT_CL_FIXED_RCL_ORDER) { 271 if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X)) 272 positive_x = false; 273 if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y)) 274 positive_y = false; 275 } 276 277 size = VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE; 278 loop_body_size = VC4_PACKET_TILE_COORDINATES_SIZE; 279 280 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) { 281 size += VC4_PACKET_CLEAR_COLORS_SIZE + 282 VC4_PACKET_TILE_COORDINATES_SIZE + 283 VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; 284 } 285 286 if (setup->color_read) { 287 if (args->color_read.flags & 288 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 289 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; 290 } else { 291 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; 292 } 293 } 294 if (setup->zs_read) { 295 if (setup->color_read) { 296 loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; 297 loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; 298 } 299 300 if (args->zs_read.flags & 301 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 302 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; 303 } else { 304 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; 305 } 306 } 307 308 if (has_bin) { 309 size += VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE; 310 loop_body_size += VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE; 311 } 312 313 if (setup->msaa_color_write) 314 loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE; 315 if (setup->msaa_zs_write) 316 loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE; 317 318 if (setup->zs_write) 319 loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; 320 if (setup->color_write) 321 loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE; 322 323 /* We need a VC4_PACKET_TILE_COORDINATES in between each store. */ 324 loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE * 325 ((setup->msaa_color_write != NULL) + 326 (setup->msaa_zs_write != NULL) + 327 (setup->color_write != NULL) + 328 (setup->zs_write != NULL) - 1); 329 330 size += xtiles * ytiles * loop_body_size; 331 332 setup->rcl = &vc4_bo_create(dev, size, true, VC4_BO_TYPE_RCL)->base; 333 if (IS_ERR(setup->rcl)) 334 return PTR_ERR(setup->rcl); 335 list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head, 336 &exec->unref_list); 337 338 /* The tile buffer gets cleared when the previous tile is stored. If 339 * the clear values changed between frames, then the tile buffer has 340 * stale clear values in it, so we have to do a store in None mode (no 341 * writes) so that we trigger the tile buffer clear. 342 */ 343 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) { 344 rcl_u8(setup, VC4_PACKET_CLEAR_COLORS); 345 rcl_u32(setup, args->clear_color[0]); 346 rcl_u32(setup, args->clear_color[1]); 347 rcl_u32(setup, args->clear_z); 348 rcl_u8(setup, args->clear_s); 349 350 vc4_tile_coordinates(setup, 0, 0); 351 352 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); 353 rcl_u16(setup, VC4_LOADSTORE_TILE_BUFFER_NONE); 354 rcl_u32(setup, 0); /* no address, since we're in None mode */ 355 } 356 357 rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG); 358 rcl_u32(setup, 359 (setup->color_write ? (setup->color_write->dma_addr + 360 args->color_write.offset) : 361 0)); 362 rcl_u16(setup, args->width); 363 rcl_u16(setup, args->height); 364 rcl_u16(setup, args->color_write.bits); 365 366 for (yi = 0; yi < ytiles; yi++) { 367 int y = positive_y ? min_y_tile + yi : max_y_tile - yi; 368 for (xi = 0; xi < xtiles; xi++) { 369 int x = positive_x ? min_x_tile + xi : max_x_tile - xi; 370 bool first = (xi == 0 && yi == 0); 371 bool last = (xi == xtiles - 1 && yi == ytiles - 1); 372 373 emit_tile(exec, setup, x, y, first, last); 374 } 375 } 376 377 BUG_ON(setup->next_offset != size); 378 exec->ct1ca = setup->rcl->dma_addr; 379 exec->ct1ea = setup->rcl->dma_addr + setup->next_offset; 380 381 return 0; 382 } 383 384 static int vc4_full_res_bounds_check(struct vc4_exec_info *exec, 385 struct drm_gem_dma_object *obj, 386 struct drm_vc4_submit_rcl_surface *surf) 387 { 388 struct drm_vc4_submit_cl *args = exec->args; 389 u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32); 390 391 if (surf->offset > obj->base.size) { 392 DRM_DEBUG("surface offset %d > BO size %zd\n", 393 surf->offset, obj->base.size); 394 return -EINVAL; 395 } 396 397 if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE < 398 render_tiles_stride * args->max_y_tile + args->max_x_tile) { 399 DRM_DEBUG("MSAA tile %d, %d out of bounds " 400 "(bo size %zd, offset %d).\n", 401 args->max_x_tile, args->max_y_tile, 402 obj->base.size, 403 surf->offset); 404 return -EINVAL; 405 } 406 407 return 0; 408 } 409 410 static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec, 411 struct drm_gem_dma_object **obj, 412 struct drm_vc4_submit_rcl_surface *surf) 413 { 414 if (surf->flags != 0 || surf->bits != 0) { 415 DRM_DEBUG("MSAA surface had nonzero flags/bits\n"); 416 return -EINVAL; 417 } 418 419 if (surf->hindex == ~0) 420 return 0; 421 422 *obj = vc4_use_bo(exec, surf->hindex); 423 if (!*obj) 424 return -EINVAL; 425 426 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; 427 428 if (surf->offset & 0xf) { 429 DRM_DEBUG("MSAA write must be 16b aligned.\n"); 430 return -EINVAL; 431 } 432 433 return vc4_full_res_bounds_check(exec, *obj, surf); 434 } 435 436 static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, 437 struct drm_gem_dma_object **obj, 438 struct drm_vc4_submit_rcl_surface *surf, 439 bool is_write) 440 { 441 uint8_t tiling = VC4_GET_FIELD(surf->bits, 442 VC4_LOADSTORE_TILE_BUFFER_TILING); 443 uint8_t buffer = VC4_GET_FIELD(surf->bits, 444 VC4_LOADSTORE_TILE_BUFFER_BUFFER); 445 uint8_t format = VC4_GET_FIELD(surf->bits, 446 VC4_LOADSTORE_TILE_BUFFER_FORMAT); 447 int cpp; 448 int ret; 449 450 if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 451 DRM_DEBUG("Extra flags set\n"); 452 return -EINVAL; 453 } 454 455 if (surf->hindex == ~0) 456 return 0; 457 458 *obj = vc4_use_bo(exec, surf->hindex); 459 if (!*obj) 460 return -EINVAL; 461 462 if (is_write) 463 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; 464 465 if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 466 if (surf == &exec->args->zs_write) { 467 DRM_DEBUG("general zs write may not be a full-res.\n"); 468 return -EINVAL; 469 } 470 471 if (surf->bits != 0) { 472 DRM_DEBUG("load/store general bits set with " 473 "full res load/store.\n"); 474 return -EINVAL; 475 } 476 477 ret = vc4_full_res_bounds_check(exec, *obj, surf); 478 if (ret) 479 return ret; 480 481 return 0; 482 } 483 484 if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK | 485 VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK | 486 VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) { 487 DRM_DEBUG("Unknown bits in load/store: 0x%04x\n", 488 surf->bits); 489 return -EINVAL; 490 } 491 492 if (tiling > VC4_TILING_FORMAT_LT) { 493 DRM_DEBUG("Bad tiling format\n"); 494 return -EINVAL; 495 } 496 497 if (buffer == VC4_LOADSTORE_TILE_BUFFER_ZS) { 498 if (format != 0) { 499 DRM_DEBUG("No color format should be set for ZS\n"); 500 return -EINVAL; 501 } 502 cpp = 4; 503 } else if (buffer == VC4_LOADSTORE_TILE_BUFFER_COLOR) { 504 switch (format) { 505 case VC4_LOADSTORE_TILE_BUFFER_BGR565: 506 case VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER: 507 cpp = 2; 508 break; 509 case VC4_LOADSTORE_TILE_BUFFER_RGBA8888: 510 cpp = 4; 511 break; 512 default: 513 DRM_DEBUG("Bad tile buffer format\n"); 514 return -EINVAL; 515 } 516 } else { 517 DRM_DEBUG("Bad load/store buffer %d.\n", buffer); 518 return -EINVAL; 519 } 520 521 if (surf->offset & 0xf) { 522 DRM_DEBUG("load/store buffer must be 16b aligned.\n"); 523 return -EINVAL; 524 } 525 526 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, 527 exec->args->width, exec->args->height, cpp)) { 528 return -EINVAL; 529 } 530 531 return 0; 532 } 533 534 static int 535 vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, 536 struct vc4_rcl_setup *setup, 537 struct drm_gem_dma_object **obj, 538 struct drm_vc4_submit_rcl_surface *surf) 539 { 540 uint8_t tiling = VC4_GET_FIELD(surf->bits, 541 VC4_RENDER_CONFIG_MEMORY_FORMAT); 542 uint8_t format = VC4_GET_FIELD(surf->bits, 543 VC4_RENDER_CONFIG_FORMAT); 544 int cpp; 545 546 if (surf->flags != 0) { 547 DRM_DEBUG("No flags supported on render config.\n"); 548 return -EINVAL; 549 } 550 551 if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK | 552 VC4_RENDER_CONFIG_FORMAT_MASK | 553 VC4_RENDER_CONFIG_MS_MODE_4X | 554 VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) { 555 DRM_DEBUG("Unknown bits in render config: 0x%04x\n", 556 surf->bits); 557 return -EINVAL; 558 } 559 560 if (surf->hindex == ~0) 561 return 0; 562 563 *obj = vc4_use_bo(exec, surf->hindex); 564 if (!*obj) 565 return -EINVAL; 566 567 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; 568 569 if (tiling > VC4_TILING_FORMAT_LT) { 570 DRM_DEBUG("Bad tiling format\n"); 571 return -EINVAL; 572 } 573 574 switch (format) { 575 case VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED: 576 case VC4_RENDER_CONFIG_FORMAT_BGR565: 577 cpp = 2; 578 break; 579 case VC4_RENDER_CONFIG_FORMAT_RGBA8888: 580 cpp = 4; 581 break; 582 default: 583 DRM_DEBUG("Bad tile buffer format\n"); 584 return -EINVAL; 585 } 586 587 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, 588 exec->args->width, exec->args->height, cpp)) { 589 return -EINVAL; 590 } 591 592 return 0; 593 } 594 595 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec) 596 { 597 struct vc4_dev *vc4 = to_vc4_dev(dev); 598 struct vc4_rcl_setup setup = {0}; 599 struct drm_vc4_submit_cl *args = exec->args; 600 bool has_bin = args->bin_cl_size != 0; 601 int ret; 602 603 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 604 return -ENODEV; 605 606 if (args->min_x_tile > args->max_x_tile || 607 args->min_y_tile > args->max_y_tile) { 608 DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n", 609 args->min_x_tile, args->min_y_tile, 610 args->max_x_tile, args->max_y_tile); 611 return -EINVAL; 612 } 613 614 if (has_bin && 615 (args->max_x_tile > exec->bin_tiles_x || 616 args->max_y_tile > exec->bin_tiles_y)) { 617 DRM_DEBUG("Render tiles (%d,%d) outside of bin config " 618 "(%d,%d)\n", 619 args->max_x_tile, args->max_y_tile, 620 exec->bin_tiles_x, exec->bin_tiles_y); 621 return -EINVAL; 622 } 623 624 ret = vc4_rcl_render_config_surface_setup(exec, &setup, 625 &setup.color_write, 626 &args->color_write); 627 if (ret) 628 return ret; 629 630 ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read, 631 false); 632 if (ret) 633 return ret; 634 635 ret = vc4_rcl_surface_setup(exec, &setup.zs_read, &args->zs_read, 636 false); 637 if (ret) 638 return ret; 639 640 ret = vc4_rcl_surface_setup(exec, &setup.zs_write, &args->zs_write, 641 true); 642 if (ret) 643 return ret; 644 645 ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_color_write, 646 &args->msaa_color_write); 647 if (ret) 648 return ret; 649 650 ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_zs_write, 651 &args->msaa_zs_write); 652 if (ret) 653 return ret; 654 655 /* We shouldn't even have the job submitted to us if there's no 656 * surface to write out. 657 */ 658 if (!setup.color_write && !setup.zs_write && 659 !setup.msaa_color_write && !setup.msaa_zs_write) { 660 DRM_DEBUG("RCL requires color or Z/S write\n"); 661 return -EINVAL; 662 } 663 664 return vc4_create_rcl_bo(dev, exec, &setup); 665 } 666