1 /* 2 * Copyright (C) 2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 /** 10 * DOC: VC4 plane module 11 * 12 * Each DRM plane is a layer of pixels being scanned out by the HVS. 13 * 14 * At atomic modeset check time, we compute the HVS display element 15 * state that would be necessary for displaying the plane (giving us a 16 * chance to figure out if a plane configuration is invalid), then at 17 * atomic flush time the CRTC will ask us to write our element state 18 * into the region of the HVS that it has allocated for us. 19 */ 20 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_fb_cma_helper.h> 24 #include <drm/drm_plane_helper.h> 25 26 #include "uapi/drm/vc4_drm.h" 27 #include "vc4_drv.h" 28 #include "vc4_regs.h" 29 30 static const struct hvs_format { 31 u32 drm; /* DRM_FORMAT_* */ 32 u32 hvs; /* HVS_FORMAT_* */ 33 u32 pixel_order; 34 } hvs_formats[] = { 35 { 36 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, 37 .pixel_order = HVS_PIXEL_ORDER_ABGR, 38 }, 39 { 40 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, 41 .pixel_order = HVS_PIXEL_ORDER_ABGR, 42 }, 43 { 44 .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, 45 .pixel_order = HVS_PIXEL_ORDER_ARGB, 46 }, 47 { 48 .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, 49 .pixel_order = HVS_PIXEL_ORDER_ARGB, 50 }, 51 { 52 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565, 53 .pixel_order = HVS_PIXEL_ORDER_XRGB, 54 }, 55 { 56 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565, 57 .pixel_order = HVS_PIXEL_ORDER_XBGR, 58 }, 59 { 60 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551, 61 .pixel_order = HVS_PIXEL_ORDER_ABGR, 62 }, 63 { 64 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551, 65 .pixel_order = HVS_PIXEL_ORDER_ABGR, 66 }, 67 { 68 .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888, 69 .pixel_order = HVS_PIXEL_ORDER_XRGB, 70 }, 71 { 72 .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888, 73 .pixel_order = HVS_PIXEL_ORDER_XBGR, 74 }, 75 { 76 .drm = DRM_FORMAT_YUV422, 77 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, 78 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 79 }, 80 { 81 .drm = DRM_FORMAT_YVU422, 82 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, 83 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 84 }, 85 { 86 .drm = DRM_FORMAT_YUV420, 87 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, 88 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 89 }, 90 { 91 .drm = DRM_FORMAT_YVU420, 92 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, 93 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 94 }, 95 { 96 .drm = DRM_FORMAT_NV12, 97 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, 98 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 99 }, 100 { 101 .drm = DRM_FORMAT_NV21, 102 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, 103 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 104 }, 105 { 106 .drm = DRM_FORMAT_NV16, 107 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, 108 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 109 }, 110 { 111 .drm = DRM_FORMAT_NV61, 112 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, 113 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 114 }, 115 }; 116 117 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format) 118 { 119 unsigned i; 120 121 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) { 122 if (hvs_formats[i].drm == drm_format) 123 return &hvs_formats[i]; 124 } 125 126 return NULL; 127 } 128 129 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst) 130 { 131 if (dst > src) 132 return VC4_SCALING_PPF; 133 else if (dst < src) 134 return VC4_SCALING_TPZ; 135 else 136 return VC4_SCALING_NONE; 137 } 138 139 static bool plane_enabled(struct drm_plane_state *state) 140 { 141 return state->fb && state->crtc; 142 } 143 144 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane) 145 { 146 struct vc4_plane_state *vc4_state; 147 148 if (WARN_ON(!plane->state)) 149 return NULL; 150 151 vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL); 152 if (!vc4_state) 153 return NULL; 154 155 memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm)); 156 157 __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base); 158 159 if (vc4_state->dlist) { 160 vc4_state->dlist = kmemdup(vc4_state->dlist, 161 vc4_state->dlist_count * 4, 162 GFP_KERNEL); 163 if (!vc4_state->dlist) { 164 kfree(vc4_state); 165 return NULL; 166 } 167 vc4_state->dlist_size = vc4_state->dlist_count; 168 } 169 170 return &vc4_state->base; 171 } 172 173 static void vc4_plane_destroy_state(struct drm_plane *plane, 174 struct drm_plane_state *state) 175 { 176 struct vc4_dev *vc4 = to_vc4_dev(plane->dev); 177 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 178 179 if (vc4_state->lbm.allocated) { 180 unsigned long irqflags; 181 182 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); 183 drm_mm_remove_node(&vc4_state->lbm); 184 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); 185 } 186 187 kfree(vc4_state->dlist); 188 __drm_atomic_helper_plane_destroy_state(&vc4_state->base); 189 kfree(state); 190 } 191 192 /* Called during init to allocate the plane's atomic state. */ 193 static void vc4_plane_reset(struct drm_plane *plane) 194 { 195 struct vc4_plane_state *vc4_state; 196 197 WARN_ON(plane->state); 198 199 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); 200 if (!vc4_state) 201 return; 202 203 plane->state = &vc4_state->base; 204 plane->state->alpha = DRM_BLEND_ALPHA_OPAQUE; 205 vc4_state->base.plane = plane; 206 } 207 208 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val) 209 { 210 if (vc4_state->dlist_count == vc4_state->dlist_size) { 211 u32 new_size = max(4u, vc4_state->dlist_count * 2); 212 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL); 213 214 if (!new_dlist) 215 return; 216 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4); 217 218 kfree(vc4_state->dlist); 219 vc4_state->dlist = new_dlist; 220 vc4_state->dlist_size = new_size; 221 } 222 223 vc4_state->dlist[vc4_state->dlist_count++] = val; 224 } 225 226 /* Returns the scl0/scl1 field based on whether the dimensions need to 227 * be up/down/non-scaled. 228 * 229 * This is a replication of a table from the spec. 230 */ 231 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane) 232 { 233 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 234 235 switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) { 236 case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF: 237 return SCALER_CTL0_SCL_H_PPF_V_PPF; 238 case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF: 239 return SCALER_CTL0_SCL_H_TPZ_V_PPF; 240 case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ: 241 return SCALER_CTL0_SCL_H_PPF_V_TPZ; 242 case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ: 243 return SCALER_CTL0_SCL_H_TPZ_V_TPZ; 244 case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE: 245 return SCALER_CTL0_SCL_H_PPF_V_NONE; 246 case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF: 247 return SCALER_CTL0_SCL_H_NONE_V_PPF; 248 case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ: 249 return SCALER_CTL0_SCL_H_NONE_V_TPZ; 250 case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE: 251 return SCALER_CTL0_SCL_H_TPZ_V_NONE; 252 default: 253 case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE: 254 /* The unity case is independently handled by 255 * SCALER_CTL0_UNITY. 256 */ 257 return 0; 258 } 259 } 260 261 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state) 262 { 263 struct drm_plane *plane = state->plane; 264 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 265 struct drm_framebuffer *fb = state->fb; 266 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0); 267 u32 subpixel_src_mask = (1 << 16) - 1; 268 u32 format = fb->format->format; 269 int num_planes = fb->format->num_planes; 270 u32 h_subsample = 1; 271 u32 v_subsample = 1; 272 int i; 273 274 for (i = 0; i < num_planes; i++) 275 vc4_state->offsets[i] = bo->paddr + fb->offsets[i]; 276 277 /* We don't support subpixel source positioning for scaling. */ 278 if ((state->src_x & subpixel_src_mask) || 279 (state->src_y & subpixel_src_mask) || 280 (state->src_w & subpixel_src_mask) || 281 (state->src_h & subpixel_src_mask)) { 282 return -EINVAL; 283 } 284 285 vc4_state->src_x = state->src_x >> 16; 286 vc4_state->src_y = state->src_y >> 16; 287 vc4_state->src_w[0] = state->src_w >> 16; 288 vc4_state->src_h[0] = state->src_h >> 16; 289 290 vc4_state->crtc_x = state->crtc_x; 291 vc4_state->crtc_y = state->crtc_y; 292 vc4_state->crtc_w = state->crtc_w; 293 vc4_state->crtc_h = state->crtc_h; 294 295 vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0], 296 vc4_state->crtc_w); 297 vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0], 298 vc4_state->crtc_h); 299 300 vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE && 301 vc4_state->y_scaling[0] == VC4_SCALING_NONE); 302 303 if (num_planes > 1) { 304 vc4_state->is_yuv = true; 305 306 h_subsample = drm_format_horz_chroma_subsampling(format); 307 v_subsample = drm_format_vert_chroma_subsampling(format); 308 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample; 309 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample; 310 311 vc4_state->x_scaling[1] = 312 vc4_get_scaling_mode(vc4_state->src_w[1], 313 vc4_state->crtc_w); 314 vc4_state->y_scaling[1] = 315 vc4_get_scaling_mode(vc4_state->src_h[1], 316 vc4_state->crtc_h); 317 318 /* YUV conversion requires that horizontal scaling be enabled, 319 * even on a plane that's otherwise 1:1. Looks like only PPF 320 * works in that case, so let's pick that one. 321 */ 322 if (vc4_state->is_unity) 323 vc4_state->x_scaling[0] = VC4_SCALING_PPF; 324 } else { 325 vc4_state->x_scaling[1] = VC4_SCALING_NONE; 326 vc4_state->y_scaling[1] = VC4_SCALING_NONE; 327 } 328 329 /* No configuring scaling on the cursor plane, since it gets 330 non-vblank-synced updates, and scaling requires requires 331 LBM changes which have to be vblank-synced. 332 */ 333 if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity) 334 return -EINVAL; 335 336 /* Clamp the on-screen start x/y to 0. The hardware doesn't 337 * support negative y, and negative x wastes bandwidth. 338 */ 339 if (vc4_state->crtc_x < 0) { 340 for (i = 0; i < num_planes; i++) { 341 u32 cpp = fb->format->cpp[i]; 342 u32 subs = ((i == 0) ? 1 : h_subsample); 343 344 vc4_state->offsets[i] += (cpp * 345 (-vc4_state->crtc_x) / subs); 346 } 347 vc4_state->src_w[0] += vc4_state->crtc_x; 348 vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample; 349 vc4_state->crtc_x = 0; 350 } 351 352 if (vc4_state->crtc_y < 0) { 353 for (i = 0; i < num_planes; i++) { 354 u32 subs = ((i == 0) ? 1 : v_subsample); 355 356 vc4_state->offsets[i] += (fb->pitches[i] * 357 (-vc4_state->crtc_y) / subs); 358 } 359 vc4_state->src_h[0] += vc4_state->crtc_y; 360 vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample; 361 vc4_state->crtc_y = 0; 362 } 363 364 return 0; 365 } 366 367 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst) 368 { 369 u32 scale, recip; 370 371 scale = (1 << 16) * src / dst; 372 373 /* The specs note that while the reciprocal would be defined 374 * as (1<<32)/scale, ~0 is close enough. 375 */ 376 recip = ~0 / scale; 377 378 vc4_dlist_write(vc4_state, 379 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | 380 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); 381 vc4_dlist_write(vc4_state, 382 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); 383 } 384 385 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst) 386 { 387 u32 scale = (1 << 16) * src / dst; 388 389 vc4_dlist_write(vc4_state, 390 SCALER_PPF_AGC | 391 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | 392 VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); 393 } 394 395 static u32 vc4_lbm_size(struct drm_plane_state *state) 396 { 397 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 398 /* This is the worst case number. One of the two sizes will 399 * be used depending on the scaling configuration. 400 */ 401 u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w); 402 u32 lbm; 403 404 if (!vc4_state->is_yuv) { 405 if (vc4_state->is_unity) 406 return 0; 407 else if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ) 408 lbm = pix_per_line * 8; 409 else { 410 /* In special cases, this multiplier might be 12. */ 411 lbm = pix_per_line * 16; 412 } 413 } else { 414 /* There are cases for this going down to a multiplier 415 * of 2, but according to the firmware source, the 416 * table in the docs is somewhat wrong. 417 */ 418 lbm = pix_per_line * 16; 419 } 420 421 lbm = roundup(lbm, 32); 422 423 return lbm; 424 } 425 426 static void vc4_write_scaling_parameters(struct drm_plane_state *state, 427 int channel) 428 { 429 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 430 431 /* Ch0 H-PPF Word 0: Scaling Parameters */ 432 if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) { 433 vc4_write_ppf(vc4_state, 434 vc4_state->src_w[channel], vc4_state->crtc_w); 435 } 436 437 /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */ 438 if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) { 439 vc4_write_ppf(vc4_state, 440 vc4_state->src_h[channel], vc4_state->crtc_h); 441 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 442 } 443 444 /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */ 445 if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) { 446 vc4_write_tpz(vc4_state, 447 vc4_state->src_w[channel], vc4_state->crtc_w); 448 } 449 450 /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */ 451 if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) { 452 vc4_write_tpz(vc4_state, 453 vc4_state->src_h[channel], vc4_state->crtc_h); 454 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 455 } 456 } 457 458 /* Writes out a full display list for an active plane to the plane's 459 * private dlist state. 460 */ 461 static int vc4_plane_mode_set(struct drm_plane *plane, 462 struct drm_plane_state *state) 463 { 464 struct vc4_dev *vc4 = to_vc4_dev(plane->dev); 465 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 466 struct drm_framebuffer *fb = state->fb; 467 u32 ctl0_offset = vc4_state->dlist_count; 468 const struct hvs_format *format = vc4_get_hvs_format(fb->format->format); 469 u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier); 470 int num_planes = drm_format_num_planes(format->drm); 471 bool mix_plane_alpha; 472 bool covers_screen; 473 u32 scl0, scl1, pitch0; 474 u32 lbm_size, tiling; 475 unsigned long irqflags; 476 u32 hvs_format = format->hvs; 477 int ret, i; 478 479 ret = vc4_plane_setup_clipping_and_scaling(state); 480 if (ret) 481 return ret; 482 483 /* Allocate the LBM memory that the HVS will use for temporary 484 * storage due to our scaling/format conversion. 485 */ 486 lbm_size = vc4_lbm_size(state); 487 if (lbm_size) { 488 if (!vc4_state->lbm.allocated) { 489 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); 490 ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm, 491 &vc4_state->lbm, 492 lbm_size, 32, 0, 0); 493 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); 494 } else { 495 WARN_ON_ONCE(lbm_size != vc4_state->lbm.size); 496 } 497 } 498 499 if (ret) 500 return ret; 501 502 /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB 503 * and 4:4:4, scl1 should be set to scl0 so both channels of 504 * the scaler do the same thing. For YUV, the Y plane needs 505 * to be put in channel 1 and Cb/Cr in channel 0, so we swap 506 * the scl fields here. 507 */ 508 if (num_planes == 1) { 509 scl0 = vc4_get_scl_field(state, 0); 510 scl1 = scl0; 511 } else { 512 scl0 = vc4_get_scl_field(state, 1); 513 scl1 = vc4_get_scl_field(state, 0); 514 } 515 516 switch (base_format_mod) { 517 case DRM_FORMAT_MOD_LINEAR: 518 tiling = SCALER_CTL0_TILING_LINEAR; 519 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH); 520 break; 521 522 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: { 523 /* For T-tiled, the FB pitch is "how many bytes from 524 * one row to the next, such that pitch * tile_h == 525 * tile_size * tiles_per_row." 526 */ 527 u32 tile_size_shift = 12; /* T tiles are 4kb */ 528 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */ 529 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift); 530 531 tiling = SCALER_CTL0_TILING_256B_OR_T; 532 533 pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) | 534 VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) | 535 VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R)); 536 break; 537 } 538 539 case DRM_FORMAT_MOD_BROADCOM_SAND64: 540 case DRM_FORMAT_MOD_BROADCOM_SAND128: 541 case DRM_FORMAT_MOD_BROADCOM_SAND256: { 542 uint32_t param = fourcc_mod_broadcom_param(fb->modifier); 543 544 /* Column-based NV12 or RGBA. 545 */ 546 if (fb->format->num_planes > 1) { 547 if (hvs_format != HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE) { 548 DRM_DEBUG_KMS("SAND format only valid for NV12/21"); 549 return -EINVAL; 550 } 551 hvs_format = HVS_PIXEL_FORMAT_H264; 552 } else { 553 if (base_format_mod == DRM_FORMAT_MOD_BROADCOM_SAND256) { 554 DRM_DEBUG_KMS("SAND256 format only valid for H.264"); 555 return -EINVAL; 556 } 557 } 558 559 switch (base_format_mod) { 560 case DRM_FORMAT_MOD_BROADCOM_SAND64: 561 tiling = SCALER_CTL0_TILING_64B; 562 break; 563 case DRM_FORMAT_MOD_BROADCOM_SAND128: 564 tiling = SCALER_CTL0_TILING_128B; 565 break; 566 case DRM_FORMAT_MOD_BROADCOM_SAND256: 567 tiling = SCALER_CTL0_TILING_256B_OR_T; 568 break; 569 default: 570 break; 571 } 572 573 if (param > SCALER_TILE_HEIGHT_MASK) { 574 DRM_DEBUG_KMS("SAND height too large (%d)\n", param); 575 return -EINVAL; 576 } 577 578 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT); 579 break; 580 } 581 582 default: 583 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx", 584 (long long)fb->modifier); 585 return -EINVAL; 586 } 587 588 /* Control word */ 589 vc4_dlist_write(vc4_state, 590 SCALER_CTL0_VALID | 591 VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) | 592 (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) | 593 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) | 594 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | 595 (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) | 596 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) | 597 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1)); 598 599 /* Position Word 0: Image Positions and Alpha Value */ 600 vc4_state->pos0_offset = vc4_state->dlist_count; 601 vc4_dlist_write(vc4_state, 602 VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) | 603 VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) | 604 VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y)); 605 606 /* Position Word 1: Scaled Image Dimensions. */ 607 if (!vc4_state->is_unity) { 608 vc4_dlist_write(vc4_state, 609 VC4_SET_FIELD(vc4_state->crtc_w, 610 SCALER_POS1_SCL_WIDTH) | 611 VC4_SET_FIELD(vc4_state->crtc_h, 612 SCALER_POS1_SCL_HEIGHT)); 613 } 614 615 /* Don't waste cycles mixing with plane alpha if the set alpha 616 * is opaque or there is no per-pixel alpha information. 617 * In any case we use the alpha property value as the fixed alpha. 618 */ 619 mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE && 620 fb->format->has_alpha; 621 622 /* Position Word 2: Source Image Size, Alpha */ 623 vc4_state->pos2_offset = vc4_state->dlist_count; 624 vc4_dlist_write(vc4_state, 625 VC4_SET_FIELD(fb->format->has_alpha ? 626 SCALER_POS2_ALPHA_MODE_PIPELINE : 627 SCALER_POS2_ALPHA_MODE_FIXED, 628 SCALER_POS2_ALPHA_MODE) | 629 (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) | 630 (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) | 631 VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) | 632 VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT)); 633 634 /* Position Word 3: Context. Written by the HVS. */ 635 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 636 637 638 /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers 639 * 640 * The pointers may be any byte address. 641 */ 642 vc4_state->ptr0_offset = vc4_state->dlist_count; 643 for (i = 0; i < num_planes; i++) 644 vc4_dlist_write(vc4_state, vc4_state->offsets[i]); 645 646 /* Pointer Context Word 0/1/2: Written by the HVS */ 647 for (i = 0; i < num_planes; i++) 648 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 649 650 /* Pitch word 0 */ 651 vc4_dlist_write(vc4_state, pitch0); 652 653 /* Pitch word 1/2 */ 654 for (i = 1; i < num_planes; i++) { 655 if (hvs_format != HVS_PIXEL_FORMAT_H264) { 656 vc4_dlist_write(vc4_state, 657 VC4_SET_FIELD(fb->pitches[i], 658 SCALER_SRC_PITCH)); 659 } else { 660 vc4_dlist_write(vc4_state, pitch0); 661 } 662 } 663 664 /* Colorspace conversion words */ 665 if (vc4_state->is_yuv) { 666 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5); 667 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5); 668 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5); 669 } 670 671 if (vc4_state->x_scaling[0] != VC4_SCALING_NONE || 672 vc4_state->x_scaling[1] != VC4_SCALING_NONE || 673 vc4_state->y_scaling[0] != VC4_SCALING_NONE || 674 vc4_state->y_scaling[1] != VC4_SCALING_NONE) { 675 /* LBM Base Address. */ 676 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE || 677 vc4_state->y_scaling[1] != VC4_SCALING_NONE) { 678 vc4_dlist_write(vc4_state, vc4_state->lbm.start); 679 } 680 681 if (num_planes > 1) { 682 /* Emit Cb/Cr as channel 0 and Y as channel 683 * 1. This matches how we set up scl0/scl1 684 * above. 685 */ 686 vc4_write_scaling_parameters(state, 1); 687 } 688 vc4_write_scaling_parameters(state, 0); 689 690 /* If any PPF setup was done, then all the kernel 691 * pointers get uploaded. 692 */ 693 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF || 694 vc4_state->y_scaling[0] == VC4_SCALING_PPF || 695 vc4_state->x_scaling[1] == VC4_SCALING_PPF || 696 vc4_state->y_scaling[1] == VC4_SCALING_PPF) { 697 u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start, 698 SCALER_PPF_KERNEL_OFFSET); 699 700 /* HPPF plane 0 */ 701 vc4_dlist_write(vc4_state, kernel); 702 /* VPPF plane 0 */ 703 vc4_dlist_write(vc4_state, kernel); 704 /* HPPF plane 1 */ 705 vc4_dlist_write(vc4_state, kernel); 706 /* VPPF plane 1 */ 707 vc4_dlist_write(vc4_state, kernel); 708 } 709 } 710 711 vc4_state->dlist[ctl0_offset] |= 712 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE); 713 714 /* crtc_* are already clipped coordinates. */ 715 covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 && 716 vc4_state->crtc_w == state->crtc->mode.hdisplay && 717 vc4_state->crtc_h == state->crtc->mode.vdisplay; 718 /* Background fill might be necessary when the plane has per-pixel 719 * alpha content or a non-opaque plane alpha and could blend from the 720 * background or does not cover the entire screen. 721 */ 722 vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen || 723 state->alpha != DRM_BLEND_ALPHA_OPAQUE; 724 725 return 0; 726 } 727 728 /* If a modeset involves changing the setup of a plane, the atomic 729 * infrastructure will call this to validate a proposed plane setup. 730 * However, if a plane isn't getting updated, this (and the 731 * corresponding vc4_plane_atomic_update) won't get called. Thus, we 732 * compute the dlist here and have all active plane dlists get updated 733 * in the CRTC's flush. 734 */ 735 static int vc4_plane_atomic_check(struct drm_plane *plane, 736 struct drm_plane_state *state) 737 { 738 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 739 740 vc4_state->dlist_count = 0; 741 742 if (plane_enabled(state)) 743 return vc4_plane_mode_set(plane, state); 744 else 745 return 0; 746 } 747 748 static void vc4_plane_atomic_update(struct drm_plane *plane, 749 struct drm_plane_state *old_state) 750 { 751 /* No contents here. Since we don't know where in the CRTC's 752 * dlist we should be stored, our dlist is uploaded to the 753 * hardware with vc4_plane_write_dlist() at CRTC atomic_flush 754 * time. 755 */ 756 } 757 758 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist) 759 { 760 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); 761 int i; 762 763 vc4_state->hw_dlist = dlist; 764 765 /* Can't memcpy_toio() because it needs to be 32-bit writes. */ 766 for (i = 0; i < vc4_state->dlist_count; i++) 767 writel(vc4_state->dlist[i], &dlist[i]); 768 769 return vc4_state->dlist_count; 770 } 771 772 u32 vc4_plane_dlist_size(const struct drm_plane_state *state) 773 { 774 const struct vc4_plane_state *vc4_state = 775 container_of(state, typeof(*vc4_state), base); 776 777 return vc4_state->dlist_count; 778 } 779 780 /* Updates the plane to immediately (well, once the FIFO needs 781 * refilling) scan out from at a new framebuffer. 782 */ 783 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb) 784 { 785 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); 786 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0); 787 uint32_t addr; 788 789 /* We're skipping the address adjustment for negative origin, 790 * because this is only called on the primary plane. 791 */ 792 WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0); 793 addr = bo->paddr + fb->offsets[0]; 794 795 /* Write the new address into the hardware immediately. The 796 * scanout will start from this address as soon as the FIFO 797 * needs to refill with pixels. 798 */ 799 writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]); 800 801 /* Also update the CPU-side dlist copy, so that any later 802 * atomic updates that don't do a new modeset on our plane 803 * also use our updated address. 804 */ 805 vc4_state->dlist[vc4_state->ptr0_offset] = addr; 806 } 807 808 static void vc4_plane_atomic_async_update(struct drm_plane *plane, 809 struct drm_plane_state *state) 810 { 811 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); 812 813 if (plane->state->fb != state->fb) { 814 vc4_plane_async_set_fb(plane, state->fb); 815 drm_atomic_set_fb_for_plane(plane->state, state->fb); 816 } 817 818 /* Set the cursor's position on the screen. This is the 819 * expected change from the drm_mode_cursor_universal() 820 * helper. 821 */ 822 plane->state->crtc_x = state->crtc_x; 823 plane->state->crtc_y = state->crtc_y; 824 825 /* Allow changing the start position within the cursor BO, if 826 * that matters. 827 */ 828 plane->state->src_x = state->src_x; 829 plane->state->src_y = state->src_y; 830 831 /* Update the display list based on the new crtc_x/y. */ 832 vc4_plane_atomic_check(plane, plane->state); 833 834 /* Note that we can't just call vc4_plane_write_dlist() 835 * because that would smash the context data that the HVS is 836 * currently using. 837 */ 838 writel(vc4_state->dlist[vc4_state->pos0_offset], 839 &vc4_state->hw_dlist[vc4_state->pos0_offset]); 840 writel(vc4_state->dlist[vc4_state->pos2_offset], 841 &vc4_state->hw_dlist[vc4_state->pos2_offset]); 842 writel(vc4_state->dlist[vc4_state->ptr0_offset], 843 &vc4_state->hw_dlist[vc4_state->ptr0_offset]); 844 } 845 846 static int vc4_plane_atomic_async_check(struct drm_plane *plane, 847 struct drm_plane_state *state) 848 { 849 /* No configuring new scaling in the fast path. */ 850 if (plane->state->crtc_w != state->crtc_w || 851 plane->state->crtc_h != state->crtc_h || 852 plane->state->src_w != state->src_w || 853 plane->state->src_h != state->src_h) 854 return -EINVAL; 855 856 return 0; 857 } 858 859 static int vc4_prepare_fb(struct drm_plane *plane, 860 struct drm_plane_state *state) 861 { 862 struct vc4_bo *bo; 863 struct dma_fence *fence; 864 int ret; 865 866 if (!state->fb) 867 return 0; 868 869 bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base); 870 871 fence = reservation_object_get_excl_rcu(bo->resv); 872 drm_atomic_set_fence_for_plane(state, fence); 873 874 if (plane->state->fb == state->fb) 875 return 0; 876 877 ret = vc4_bo_inc_usecnt(bo); 878 if (ret) 879 return ret; 880 881 return 0; 882 } 883 884 static void vc4_cleanup_fb(struct drm_plane *plane, 885 struct drm_plane_state *state) 886 { 887 struct vc4_bo *bo; 888 889 if (plane->state->fb == state->fb || !state->fb) 890 return; 891 892 bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base); 893 vc4_bo_dec_usecnt(bo); 894 } 895 896 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = { 897 .atomic_check = vc4_plane_atomic_check, 898 .atomic_update = vc4_plane_atomic_update, 899 .prepare_fb = vc4_prepare_fb, 900 .cleanup_fb = vc4_cleanup_fb, 901 .atomic_async_check = vc4_plane_atomic_async_check, 902 .atomic_async_update = vc4_plane_atomic_async_update, 903 }; 904 905 static void vc4_plane_destroy(struct drm_plane *plane) 906 { 907 drm_plane_helper_disable(plane, NULL); 908 drm_plane_cleanup(plane); 909 } 910 911 static bool vc4_format_mod_supported(struct drm_plane *plane, 912 uint32_t format, 913 uint64_t modifier) 914 { 915 /* Support T_TILING for RGB formats only. */ 916 switch (format) { 917 case DRM_FORMAT_XRGB8888: 918 case DRM_FORMAT_ARGB8888: 919 case DRM_FORMAT_ABGR8888: 920 case DRM_FORMAT_XBGR8888: 921 case DRM_FORMAT_RGB565: 922 case DRM_FORMAT_BGR565: 923 case DRM_FORMAT_ARGB1555: 924 case DRM_FORMAT_XRGB1555: 925 switch (fourcc_mod_broadcom_mod(modifier)) { 926 case DRM_FORMAT_MOD_LINEAR: 927 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: 928 case DRM_FORMAT_MOD_BROADCOM_SAND64: 929 case DRM_FORMAT_MOD_BROADCOM_SAND128: 930 return true; 931 default: 932 return false; 933 } 934 case DRM_FORMAT_NV12: 935 case DRM_FORMAT_NV21: 936 switch (fourcc_mod_broadcom_mod(modifier)) { 937 case DRM_FORMAT_MOD_LINEAR: 938 case DRM_FORMAT_MOD_BROADCOM_SAND64: 939 case DRM_FORMAT_MOD_BROADCOM_SAND128: 940 case DRM_FORMAT_MOD_BROADCOM_SAND256: 941 return true; 942 default: 943 return false; 944 } 945 case DRM_FORMAT_YUV422: 946 case DRM_FORMAT_YVU422: 947 case DRM_FORMAT_YUV420: 948 case DRM_FORMAT_YVU420: 949 case DRM_FORMAT_NV16: 950 case DRM_FORMAT_NV61: 951 default: 952 return (modifier == DRM_FORMAT_MOD_LINEAR); 953 } 954 } 955 956 static const struct drm_plane_funcs vc4_plane_funcs = { 957 .update_plane = drm_atomic_helper_update_plane, 958 .disable_plane = drm_atomic_helper_disable_plane, 959 .destroy = vc4_plane_destroy, 960 .set_property = NULL, 961 .reset = vc4_plane_reset, 962 .atomic_duplicate_state = vc4_plane_duplicate_state, 963 .atomic_destroy_state = vc4_plane_destroy_state, 964 .format_mod_supported = vc4_format_mod_supported, 965 }; 966 967 struct drm_plane *vc4_plane_init(struct drm_device *dev, 968 enum drm_plane_type type) 969 { 970 struct drm_plane *plane = NULL; 971 struct vc4_plane *vc4_plane; 972 u32 formats[ARRAY_SIZE(hvs_formats)]; 973 u32 num_formats = 0; 974 int ret = 0; 975 unsigned i; 976 static const uint64_t modifiers[] = { 977 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED, 978 DRM_FORMAT_MOD_BROADCOM_SAND128, 979 DRM_FORMAT_MOD_BROADCOM_SAND64, 980 DRM_FORMAT_MOD_BROADCOM_SAND256, 981 DRM_FORMAT_MOD_LINEAR, 982 DRM_FORMAT_MOD_INVALID 983 }; 984 985 vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane), 986 GFP_KERNEL); 987 if (!vc4_plane) 988 return ERR_PTR(-ENOMEM); 989 990 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) { 991 /* Don't allow YUV in cursor planes, since that means 992 * tuning on the scaler, which we don't allow for the 993 * cursor. 994 */ 995 if (type != DRM_PLANE_TYPE_CURSOR || 996 hvs_formats[i].hvs < HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE) { 997 formats[num_formats++] = hvs_formats[i].drm; 998 } 999 } 1000 plane = &vc4_plane->base; 1001 ret = drm_universal_plane_init(dev, plane, 0, 1002 &vc4_plane_funcs, 1003 formats, num_formats, 1004 modifiers, type, NULL); 1005 1006 drm_plane_helper_add(plane, &vc4_plane_helper_funcs); 1007 1008 drm_plane_create_alpha_property(plane); 1009 1010 return plane; 1011 } 1012