1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 HVS module. 8 * 9 * The Hardware Video Scaler (HVS) is the piece of hardware that does 10 * translation, scaling, colorspace conversion, and compositing of 11 * pixels stored in framebuffers into a FIFO of pixels going out to 12 * the Pixel Valve (CRTC). It operates at the system clock rate (the 13 * system audio clock gate, specifically), which is much higher than 14 * the pixel clock rate. 15 * 16 * There is a single global HVS, with multiple output FIFOs that can 17 * be consumed by the PVs. This file just manages the resources for 18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for 19 * each CRTC. 20 */ 21 22 #include <linux/bitfield.h> 23 #include <linux/clk.h> 24 #include <linux/component.h> 25 #include <linux/platform_device.h> 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_drv.h> 29 #include <drm/drm_vblank.h> 30 31 #include <soc/bcm2835/raspberrypi-firmware.h> 32 33 #include "vc4_drv.h" 34 #include "vc4_regs.h" 35 36 static const struct debugfs_reg32 vc4_hvs_regs[] = { 37 VC4_REG32(SCALER_DISPCTRL), 38 VC4_REG32(SCALER_DISPSTAT), 39 VC4_REG32(SCALER_DISPID), 40 VC4_REG32(SCALER_DISPECTRL), 41 VC4_REG32(SCALER_DISPPROF), 42 VC4_REG32(SCALER_DISPDITHER), 43 VC4_REG32(SCALER_DISPEOLN), 44 VC4_REG32(SCALER_DISPLIST0), 45 VC4_REG32(SCALER_DISPLIST1), 46 VC4_REG32(SCALER_DISPLIST2), 47 VC4_REG32(SCALER_DISPLSTAT), 48 VC4_REG32(SCALER_DISPLACT0), 49 VC4_REG32(SCALER_DISPLACT1), 50 VC4_REG32(SCALER_DISPLACT2), 51 VC4_REG32(SCALER_DISPCTRL0), 52 VC4_REG32(SCALER_DISPBKGND0), 53 VC4_REG32(SCALER_DISPSTAT0), 54 VC4_REG32(SCALER_DISPBASE0), 55 VC4_REG32(SCALER_DISPCTRL1), 56 VC4_REG32(SCALER_DISPBKGND1), 57 VC4_REG32(SCALER_DISPSTAT1), 58 VC4_REG32(SCALER_DISPBASE1), 59 VC4_REG32(SCALER_DISPCTRL2), 60 VC4_REG32(SCALER_DISPBKGND2), 61 VC4_REG32(SCALER_DISPSTAT2), 62 VC4_REG32(SCALER_DISPBASE2), 63 VC4_REG32(SCALER_DISPALPHA2), 64 VC4_REG32(SCALER_OLEDOFFS), 65 VC4_REG32(SCALER_OLEDCOEF0), 66 VC4_REG32(SCALER_OLEDCOEF1), 67 VC4_REG32(SCALER_OLEDCOEF2), 68 }; 69 70 void vc4_hvs_dump_state(struct vc4_hvs *hvs) 71 { 72 struct drm_device *drm = &hvs->vc4->base; 73 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); 74 int idx, i; 75 76 if (!drm_dev_enter(drm, &idx)) 77 return; 78 79 drm_print_regset32(&p, &hvs->regset); 80 81 DRM_INFO("HVS ctx:\n"); 82 for (i = 0; i < 64; i += 4) { 83 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n", 84 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D", 85 readl((u32 __iomem *)hvs->dlist + i + 0), 86 readl((u32 __iomem *)hvs->dlist + i + 1), 87 readl((u32 __iomem *)hvs->dlist + i + 2), 88 readl((u32 __iomem *)hvs->dlist + i + 3)); 89 } 90 91 drm_dev_exit(idx); 92 } 93 94 static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data) 95 { 96 struct drm_debugfs_entry *entry = m->private; 97 struct drm_device *dev = entry->dev; 98 struct vc4_dev *vc4 = to_vc4_dev(dev); 99 struct drm_printer p = drm_seq_file_printer(m); 100 101 drm_printf(&p, "%d\n", atomic_read(&vc4->underrun)); 102 103 return 0; 104 } 105 106 static int vc4_hvs_debugfs_dlist(struct seq_file *m, void *data) 107 { 108 struct drm_debugfs_entry *entry = m->private; 109 struct drm_device *dev = entry->dev; 110 struct vc4_dev *vc4 = to_vc4_dev(dev); 111 struct vc4_hvs *hvs = vc4->hvs; 112 struct drm_printer p = drm_seq_file_printer(m); 113 unsigned int dlist_mem_size = hvs->dlist_mem_size; 114 unsigned int next_entry_start; 115 unsigned int i, j; 116 u32 dlist_word, dispstat; 117 118 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) { 119 dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)), 120 SCALER_DISPSTATX_MODE); 121 if (dispstat == SCALER_DISPSTATX_MODE_DISABLED || 122 dispstat == SCALER_DISPSTATX_MODE_EOF) { 123 drm_printf(&p, "HVS chan %u disabled\n", i); 124 continue; 125 } 126 127 drm_printf(&p, "HVS chan %u:\n", i); 128 next_entry_start = 0; 129 130 for (j = HVS_READ(SCALER_DISPLISTX(i)); j < dlist_mem_size; j++) { 131 dlist_word = readl((u32 __iomem *)vc4->hvs->dlist + j); 132 drm_printf(&p, "dlist: %02d: 0x%08x\n", j, 133 dlist_word); 134 if (!next_entry_start || 135 next_entry_start == j) { 136 if (dlist_word & SCALER_CTL0_END) 137 break; 138 next_entry_start = j + 139 VC4_GET_FIELD(dlist_word, 140 SCALER_CTL0_SIZE); 141 } 142 } 143 } 144 145 return 0; 146 } 147 148 /* The filter kernel is composed of dwords each containing 3 9-bit 149 * signed integers packed next to each other. 150 */ 151 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff) 152 #define VC4_PPF_FILTER_WORD(c0, c1, c2) \ 153 ((((c0) & 0x1ff) << 0) | \ 154 (((c1) & 0x1ff) << 9) | \ 155 (((c2) & 0x1ff) << 18)) 156 157 /* The whole filter kernel is arranged as the coefficients 0-16 going 158 * up, then a pad, then 17-31 going down and reversed within the 159 * dwords. This means that a linear phase kernel (where it's 160 * symmetrical at the boundary between 15 and 16) has the last 5 161 * dwords matching the first 5, but reversed. 162 */ 163 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \ 164 c9, c10, c11, c12, c13, c14, c15) \ 165 {VC4_PPF_FILTER_WORD(c0, c1, c2), \ 166 VC4_PPF_FILTER_WORD(c3, c4, c5), \ 167 VC4_PPF_FILTER_WORD(c6, c7, c8), \ 168 VC4_PPF_FILTER_WORD(c9, c10, c11), \ 169 VC4_PPF_FILTER_WORD(c12, c13, c14), \ 170 VC4_PPF_FILTER_WORD(c15, c15, 0)} 171 172 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6 173 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1) 174 175 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali. 176 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf 177 */ 178 static const u32 mitchell_netravali_1_3_1_3_kernel[] = 179 VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18, 180 50, 82, 119, 155, 187, 213, 227); 181 182 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs, 183 struct drm_mm_node *space, 184 const u32 *kernel) 185 { 186 int ret, i; 187 u32 __iomem *dst_kernel; 188 189 /* 190 * NOTE: We don't need a call to drm_dev_enter()/drm_dev_exit() 191 * here since that function is only called from vc4_hvs_bind(). 192 */ 193 194 ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS); 195 if (ret) { 196 drm_err(&hvs->vc4->base, "Failed to allocate space for filter kernel: %d\n", 197 ret); 198 return ret; 199 } 200 201 dst_kernel = hvs->dlist + space->start; 202 203 for (i = 0; i < VC4_KERNEL_DWORDS; i++) { 204 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS) 205 writel(kernel[i], &dst_kernel[i]); 206 else { 207 writel(kernel[VC4_KERNEL_DWORDS - i - 1], 208 &dst_kernel[i]); 209 } 210 } 211 212 return 0; 213 } 214 215 static void vc4_hvs_lut_load(struct vc4_hvs *hvs, 216 struct vc4_crtc *vc4_crtc) 217 { 218 struct drm_device *drm = &hvs->vc4->base; 219 struct drm_crtc *crtc = &vc4_crtc->base; 220 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 221 int idx; 222 u32 i; 223 224 if (!drm_dev_enter(drm, &idx)) 225 return; 226 227 if (hvs->vc4->gen == VC4_GEN_4) 228 return; 229 230 /* The LUT memory is laid out with each HVS channel in order, 231 * each of which takes 256 writes for R, 256 for G, then 256 232 * for B. 233 */ 234 HVS_WRITE(SCALER_GAMADDR, 235 SCALER_GAMADDR_AUTOINC | 236 (vc4_state->assigned_channel * 3 * crtc->gamma_size)); 237 238 for (i = 0; i < crtc->gamma_size; i++) 239 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); 240 for (i = 0; i < crtc->gamma_size; i++) 241 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); 242 for (i = 0; i < crtc->gamma_size; i++) 243 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); 244 245 drm_dev_exit(idx); 246 } 247 248 static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs, 249 struct vc4_crtc *vc4_crtc) 250 { 251 struct drm_crtc_state *crtc_state = vc4_crtc->base.state; 252 struct drm_color_lut *lut = crtc_state->gamma_lut->data; 253 u32 length = drm_color_lut_size(crtc_state->gamma_lut); 254 u32 i; 255 256 for (i = 0; i < length; i++) { 257 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8); 258 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8); 259 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8); 260 } 261 262 vc4_hvs_lut_load(hvs, vc4_crtc); 263 } 264 265 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo) 266 { 267 struct drm_device *drm = &hvs->vc4->base; 268 u8 field = 0; 269 int idx; 270 271 if (!drm_dev_enter(drm, &idx)) 272 return 0; 273 274 switch (fifo) { 275 case 0: 276 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 277 SCALER_DISPSTAT1_FRCNT0); 278 break; 279 case 1: 280 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 281 SCALER_DISPSTAT1_FRCNT1); 282 break; 283 case 2: 284 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), 285 SCALER_DISPSTAT2_FRCNT2); 286 break; 287 } 288 289 drm_dev_exit(idx); 290 return field; 291 } 292 293 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output) 294 { 295 struct vc4_dev *vc4 = hvs->vc4; 296 u32 reg; 297 int ret; 298 299 switch (vc4->gen) { 300 case VC4_GEN_4: 301 return output; 302 303 case VC4_GEN_5: 304 /* 305 * NOTE: We should probably use 306 * drm_dev_enter()/drm_dev_exit() here, but this 307 * function is only used during the DRM device 308 * initialization, so we should be fine. 309 */ 310 311 switch (output) { 312 case 0: 313 return 0; 314 315 case 1: 316 return 1; 317 318 case 2: 319 reg = HVS_READ(SCALER_DISPECTRL); 320 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg); 321 if (ret == 0) 322 return 2; 323 324 return 0; 325 326 case 3: 327 reg = HVS_READ(SCALER_DISPCTRL); 328 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg); 329 if (ret == 3) 330 return -EPIPE; 331 332 return ret; 333 334 case 4: 335 reg = HVS_READ(SCALER_DISPEOLN); 336 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg); 337 if (ret == 3) 338 return -EPIPE; 339 340 return ret; 341 342 case 5: 343 reg = HVS_READ(SCALER_DISPDITHER); 344 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg); 345 if (ret == 3) 346 return -EPIPE; 347 348 return ret; 349 350 default: 351 return -EPIPE; 352 } 353 354 default: 355 return -EPIPE; 356 } 357 } 358 359 static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc, 360 struct drm_display_mode *mode, bool oneshot) 361 { 362 struct vc4_dev *vc4 = hvs->vc4; 363 struct drm_device *drm = &vc4->base; 364 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 365 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 366 unsigned int chan = vc4_crtc_state->assigned_channel; 367 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 368 u32 dispbkgndx; 369 u32 dispctrl; 370 int idx; 371 372 if (!drm_dev_enter(drm, &idx)) 373 return -ENODEV; 374 375 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 376 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); 377 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 378 379 /* Turn on the scaler, which will wait for vstart to start 380 * compositing. 381 * When feeding the transposer, we should operate in oneshot 382 * mode. 383 */ 384 dispctrl = SCALER_DISPCTRLX_ENABLE; 385 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan)); 386 387 if (vc4->gen == VC4_GEN_4) { 388 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 389 SCALER_DISPCTRLX_WIDTH) | 390 VC4_SET_FIELD(mode->vdisplay, 391 SCALER_DISPCTRLX_HEIGHT) | 392 (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0); 393 dispbkgndx |= SCALER_DISPBKGND_AUTOHS; 394 } else { 395 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 396 SCALER5_DISPCTRLX_WIDTH) | 397 VC4_SET_FIELD(mode->vdisplay, 398 SCALER5_DISPCTRLX_HEIGHT) | 399 (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0); 400 dispbkgndx &= ~SCALER5_DISPBKGND_BCK2BCK; 401 } 402 403 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl); 404 405 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 406 dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE; 407 408 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx | 409 ((vc4->gen == VC4_GEN_4) ? SCALER_DISPBKGND_GAMMA : 0) | 410 (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); 411 412 /* Reload the LUT, since the SRAMs would have been disabled if 413 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. 414 */ 415 vc4_hvs_lut_load(hvs, vc4_crtc); 416 417 drm_dev_exit(idx); 418 419 return 0; 420 } 421 422 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan) 423 { 424 struct drm_device *drm = &hvs->vc4->base; 425 int idx; 426 427 if (!drm_dev_enter(drm, &idx)) 428 return; 429 430 if (!(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE)) 431 goto out; 432 433 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); 434 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 435 436 /* Once we leave, the scaler should be disabled and its fifo empty. */ 437 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); 438 439 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), 440 SCALER_DISPSTATX_MODE) != 441 SCALER_DISPSTATX_MODE_DISABLED); 442 443 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & 444 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != 445 SCALER_DISPSTATX_EMPTY); 446 447 out: 448 drm_dev_exit(idx); 449 } 450 451 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) 452 { 453 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 454 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 455 struct drm_device *dev = crtc->dev; 456 struct vc4_dev *vc4 = to_vc4_dev(dev); 457 struct drm_plane *plane; 458 unsigned long flags; 459 const struct drm_plane_state *plane_state; 460 u32 dlist_count = 0; 461 int ret; 462 463 /* The pixelvalve can only feed one encoder (and encoders are 464 * 1:1 with connectors.) 465 */ 466 if (hweight32(crtc_state->connector_mask) > 1) 467 return -EINVAL; 468 469 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) { 470 u32 plane_dlist_count = vc4_plane_dlist_size(plane_state); 471 472 drm_dbg_driver(dev, "[CRTC:%d:%s] Found [PLANE:%d:%s] with DLIST size: %u\n", 473 crtc->base.id, crtc->name, 474 plane->base.id, plane->name, 475 plane_dlist_count); 476 477 dlist_count += plane_dlist_count; 478 } 479 480 dlist_count++; /* Account for SCALER_CTL0_END. */ 481 482 drm_dbg_driver(dev, "[CRTC:%d:%s] Allocating DLIST block with size: %u\n", 483 crtc->base.id, crtc->name, dlist_count); 484 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 485 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, 486 dlist_count); 487 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 488 if (ret) { 489 drm_err(dev, "Failed to allocate DLIST entry: %d\n", ret); 490 return ret; 491 } 492 493 return 0; 494 } 495 496 static void vc4_hvs_install_dlist(struct drm_crtc *crtc) 497 { 498 struct drm_device *dev = crtc->dev; 499 struct vc4_dev *vc4 = to_vc4_dev(dev); 500 struct vc4_hvs *hvs = vc4->hvs; 501 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 502 int idx; 503 504 if (!drm_dev_enter(dev, &idx)) 505 return; 506 507 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel), 508 vc4_state->mm.start); 509 510 drm_dev_exit(idx); 511 } 512 513 static void vc4_hvs_update_dlist(struct drm_crtc *crtc) 514 { 515 struct drm_device *dev = crtc->dev; 516 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 517 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 518 unsigned long flags; 519 520 if (crtc->state->event) { 521 crtc->state->event->pipe = drm_crtc_index(crtc); 522 523 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 524 525 spin_lock_irqsave(&dev->event_lock, flags); 526 527 if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) { 528 vc4_crtc->event = crtc->state->event; 529 crtc->state->event = NULL; 530 } 531 532 spin_unlock_irqrestore(&dev->event_lock, flags); 533 } 534 535 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 536 vc4_crtc->current_dlist = vc4_state->mm.start; 537 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 538 } 539 540 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, 541 struct drm_atomic_state *state) 542 { 543 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 544 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 545 unsigned long flags; 546 547 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 548 vc4_crtc->current_hvs_channel = vc4_state->assigned_channel; 549 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 550 } 551 552 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, 553 struct drm_atomic_state *state) 554 { 555 struct drm_device *dev = crtc->dev; 556 struct vc4_dev *vc4 = to_vc4_dev(dev); 557 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 558 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 559 bool oneshot = vc4_crtc->feeds_txp; 560 561 vc4_hvs_install_dlist(crtc); 562 vc4_hvs_update_dlist(crtc); 563 vc4_hvs_init_channel(vc4->hvs, crtc, mode, oneshot); 564 } 565 566 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, 567 struct drm_atomic_state *state) 568 { 569 struct drm_device *dev = crtc->dev; 570 struct vc4_dev *vc4 = to_vc4_dev(dev); 571 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); 572 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state); 573 unsigned int chan = vc4_state->assigned_channel; 574 575 vc4_hvs_stop_channel(vc4->hvs, chan); 576 } 577 578 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, 579 struct drm_atomic_state *state) 580 { 581 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 582 crtc); 583 struct drm_device *dev = crtc->dev; 584 struct vc4_dev *vc4 = to_vc4_dev(dev); 585 struct vc4_hvs *hvs = vc4->hvs; 586 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 587 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 588 unsigned int channel = vc4_state->assigned_channel; 589 struct drm_plane *plane; 590 struct vc4_plane_state *vc4_plane_state; 591 bool debug_dump_regs = false; 592 bool enable_bg_fill = false; 593 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; 594 u32 __iomem *dlist_next = dlist_start; 595 unsigned int zpos = 0; 596 bool found = false; 597 int idx; 598 599 if (!drm_dev_enter(dev, &idx)) { 600 vc4_crtc_send_vblank(crtc); 601 return; 602 } 603 604 if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) 605 return; 606 607 if (debug_dump_regs) { 608 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); 609 vc4_hvs_dump_state(hvs); 610 } 611 612 /* Copy all the active planes' dlist contents to the hardware dlist. */ 613 do { 614 found = false; 615 616 drm_atomic_crtc_for_each_plane(plane, crtc) { 617 if (plane->state->normalized_zpos != zpos) 618 continue; 619 620 /* Is this the first active plane? */ 621 if (dlist_next == dlist_start) { 622 /* We need to enable background fill when a plane 623 * could be alpha blending from the background, i.e. 624 * where no other plane is underneath. It suffices to 625 * consider the first active plane here since we set 626 * needs_bg_fill such that either the first plane 627 * already needs it or all planes on top blend from 628 * the first or a lower plane. 629 */ 630 vc4_plane_state = to_vc4_plane_state(plane->state); 631 enable_bg_fill = vc4_plane_state->needs_bg_fill; 632 } 633 634 dlist_next += vc4_plane_write_dlist(plane, dlist_next); 635 636 found = true; 637 } 638 639 zpos++; 640 } while (found); 641 642 writel(SCALER_CTL0_END, dlist_next); 643 dlist_next++; 644 645 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); 646 647 if (enable_bg_fill) 648 /* This sets a black background color fill, as is the case 649 * with other DRM drivers. 650 */ 651 HVS_WRITE(SCALER_DISPBKGNDX(channel), 652 HVS_READ(SCALER_DISPBKGNDX(channel)) | 653 SCALER_DISPBKGND_FILL); 654 655 /* Only update DISPLIST if the CRTC was already running and is not 656 * being disabled. 657 * vc4_crtc_enable() takes care of updating the dlist just after 658 * re-enabling VBLANK interrupts and before enabling the engine. 659 * If the CRTC is being disabled, there's no point in updating this 660 * information. 661 */ 662 if (crtc->state->active && old_state->active) { 663 vc4_hvs_install_dlist(crtc); 664 vc4_hvs_update_dlist(crtc); 665 } 666 667 if (crtc->state->color_mgmt_changed) { 668 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel)); 669 670 if (crtc->state->gamma_lut) { 671 vc4_hvs_update_gamma_lut(hvs, vc4_crtc); 672 dispbkgndx |= SCALER_DISPBKGND_GAMMA; 673 } else { 674 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step 675 * in hardware, which is the same as a linear lut that 676 * DRM expects us to use in absence of a user lut. 677 */ 678 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 679 } 680 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx); 681 } 682 683 if (debug_dump_regs) { 684 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); 685 vc4_hvs_dump_state(hvs); 686 } 687 688 drm_dev_exit(idx); 689 } 690 691 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel) 692 { 693 struct vc4_dev *vc4 = hvs->vc4; 694 struct drm_device *drm = &vc4->base; 695 u32 dispctrl; 696 int idx; 697 698 if (!drm_dev_enter(drm, &idx)) 699 return; 700 701 dispctrl = HVS_READ(SCALER_DISPCTRL); 702 dispctrl &= ~((vc4->gen == VC4_GEN_5) ? 703 SCALER5_DISPCTRL_DSPEISLUR(channel) : 704 SCALER_DISPCTRL_DSPEISLUR(channel)); 705 706 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 707 708 drm_dev_exit(idx); 709 } 710 711 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel) 712 { 713 struct vc4_dev *vc4 = hvs->vc4; 714 struct drm_device *drm = &vc4->base; 715 u32 dispctrl; 716 int idx; 717 718 if (!drm_dev_enter(drm, &idx)) 719 return; 720 721 dispctrl = HVS_READ(SCALER_DISPCTRL); 722 dispctrl |= ((vc4->gen == VC4_GEN_5) ? 723 SCALER5_DISPCTRL_DSPEISLUR(channel) : 724 SCALER_DISPCTRL_DSPEISLUR(channel)); 725 726 HVS_WRITE(SCALER_DISPSTAT, 727 SCALER_DISPSTAT_EUFLOW(channel)); 728 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 729 730 drm_dev_exit(idx); 731 } 732 733 static void vc4_hvs_report_underrun(struct drm_device *dev) 734 { 735 struct vc4_dev *vc4 = to_vc4_dev(dev); 736 737 atomic_inc(&vc4->underrun); 738 DRM_DEV_ERROR(dev->dev, "HVS underrun\n"); 739 } 740 741 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data) 742 { 743 struct drm_device *dev = data; 744 struct vc4_dev *vc4 = to_vc4_dev(dev); 745 struct vc4_hvs *hvs = vc4->hvs; 746 irqreturn_t irqret = IRQ_NONE; 747 int channel; 748 u32 control; 749 u32 status; 750 u32 dspeislur; 751 752 /* 753 * NOTE: We don't need to protect the register access using 754 * drm_dev_enter() there because the interrupt handler lifetime 755 * is tied to the device itself, and not to the DRM device. 756 * 757 * So when the device will be gone, one of the first thing we 758 * will be doing will be to unregister the interrupt handler, 759 * and then unregister the DRM device. drm_dev_enter() would 760 * thus always succeed if we are here. 761 */ 762 763 status = HVS_READ(SCALER_DISPSTAT); 764 control = HVS_READ(SCALER_DISPCTRL); 765 766 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) { 767 dspeislur = (vc4->gen == VC4_GEN_5) ? 768 SCALER5_DISPCTRL_DSPEISLUR(channel) : 769 SCALER_DISPCTRL_DSPEISLUR(channel); 770 771 /* Interrupt masking is not always honored, so check it here. */ 772 if (status & SCALER_DISPSTAT_EUFLOW(channel) && 773 control & dspeislur) { 774 vc4_hvs_mask_underrun(hvs, channel); 775 vc4_hvs_report_underrun(dev); 776 777 irqret = IRQ_HANDLED; 778 } 779 } 780 781 /* Clear every per-channel interrupt flag. */ 782 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) | 783 SCALER_DISPSTAT_IRQMASK(1) | 784 SCALER_DISPSTAT_IRQMASK(2)); 785 786 return irqret; 787 } 788 789 int vc4_hvs_debugfs_init(struct drm_minor *minor) 790 { 791 struct drm_device *drm = minor->dev; 792 struct vc4_dev *vc4 = to_vc4_dev(drm); 793 struct vc4_hvs *hvs = vc4->hvs; 794 795 if (!vc4->hvs) 796 return -ENODEV; 797 798 if (vc4->gen == VC4_GEN_4) 799 debugfs_create_bool("hvs_load_tracker", S_IRUGO | S_IWUSR, 800 minor->debugfs_root, 801 &vc4->load_tracker_enabled); 802 803 drm_debugfs_add_file(drm, "hvs_dlists", vc4_hvs_debugfs_dlist, NULL); 804 805 drm_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun, NULL); 806 807 vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset); 808 809 return 0; 810 } 811 812 struct vc4_hvs *__vc4_hvs_alloc(struct vc4_dev *vc4, 813 void __iomem *regs, 814 struct platform_device *pdev) 815 { 816 struct drm_device *drm = &vc4->base; 817 struct vc4_hvs *hvs; 818 819 hvs = drmm_kzalloc(drm, sizeof(*hvs), GFP_KERNEL); 820 if (!hvs) 821 return ERR_PTR(-ENOMEM); 822 823 hvs->vc4 = vc4; 824 hvs->regs = regs; 825 hvs->pdev = pdev; 826 827 spin_lock_init(&hvs->mm_lock); 828 829 /* Set up the HVS display list memory manager. We never 830 * overwrite the setup from the bootloader (just 128b out of 831 * our 16K), since we don't want to scramble the screen when 832 * transitioning from the firmware's boot setup to runtime. 833 */ 834 hvs->dlist_mem_size = (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END; 835 drm_mm_init(&hvs->dlist_mm, 836 HVS_BOOTLOADER_DLIST_END, 837 hvs->dlist_mem_size); 838 839 /* Set up the HVS LBM memory manager. We could have some more 840 * complicated data structure that allowed reuse of LBM areas 841 * between planes when they don't overlap on the screen, but 842 * for now we just allocate globally. 843 */ 844 if (vc4->gen == VC4_GEN_4) 845 /* 48k words of 2x12-bit pixels */ 846 drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024); 847 else 848 /* 60k words of 4x12-bit pixels */ 849 drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024); 850 851 vc4->hvs = hvs; 852 853 return hvs; 854 } 855 856 static int vc4_hvs_hw_init(struct vc4_hvs *hvs) 857 { 858 struct vc4_dev *vc4 = hvs->vc4; 859 u32 dispctrl, reg; 860 861 dispctrl = HVS_READ(SCALER_DISPCTRL); 862 dispctrl |= SCALER_DISPCTRL_ENABLE; 863 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 864 865 reg = HVS_READ(SCALER_DISPECTRL); 866 reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK; 867 HVS_WRITE(SCALER_DISPECTRL, 868 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); 869 870 reg = HVS_READ(SCALER_DISPCTRL); 871 reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK; 872 HVS_WRITE(SCALER_DISPCTRL, 873 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); 874 875 reg = HVS_READ(SCALER_DISPEOLN); 876 reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK; 877 HVS_WRITE(SCALER_DISPEOLN, 878 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); 879 880 reg = HVS_READ(SCALER_DISPDITHER); 881 reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK; 882 HVS_WRITE(SCALER_DISPDITHER, 883 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX)); 884 885 dispctrl = HVS_READ(SCALER_DISPCTRL); 886 dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) | 887 SCALER_DISPCTRL_DISPEIRQ(1) | 888 SCALER_DISPCTRL_DISPEIRQ(2); 889 890 if (vc4->gen == VC4_GEN_4) 891 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ | 892 SCALER_DISPCTRL_SLVWREIRQ | 893 SCALER_DISPCTRL_SLVRDEIRQ | 894 SCALER_DISPCTRL_DSPEIEOF(0) | 895 SCALER_DISPCTRL_DSPEIEOF(1) | 896 SCALER_DISPCTRL_DSPEIEOF(2) | 897 SCALER_DISPCTRL_DSPEIEOLN(0) | 898 SCALER_DISPCTRL_DSPEIEOLN(1) | 899 SCALER_DISPCTRL_DSPEIEOLN(2) | 900 SCALER_DISPCTRL_DSPEISLUR(0) | 901 SCALER_DISPCTRL_DSPEISLUR(1) | 902 SCALER_DISPCTRL_DSPEISLUR(2) | 903 SCALER_DISPCTRL_SCLEIRQ); 904 else 905 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ | 906 SCALER5_DISPCTRL_SLVEIRQ | 907 SCALER5_DISPCTRL_DSPEIEOF(0) | 908 SCALER5_DISPCTRL_DSPEIEOF(1) | 909 SCALER5_DISPCTRL_DSPEIEOF(2) | 910 SCALER5_DISPCTRL_DSPEIEOLN(0) | 911 SCALER5_DISPCTRL_DSPEIEOLN(1) | 912 SCALER5_DISPCTRL_DSPEIEOLN(2) | 913 SCALER5_DISPCTRL_DSPEISLUR(0) | 914 SCALER5_DISPCTRL_DSPEISLUR(1) | 915 SCALER5_DISPCTRL_DSPEISLUR(2) | 916 SCALER_DISPCTRL_SCLEIRQ); 917 918 919 /* Set AXI panic mode. 920 * VC4 panics when < 2 lines in FIFO. 921 * VC5 panics when less than 1 line in the FIFO. 922 */ 923 dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK | 924 SCALER_DISPCTRL_PANIC1_MASK | 925 SCALER_DISPCTRL_PANIC2_MASK); 926 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0); 927 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1); 928 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2); 929 930 /* Set AXI panic mode. 931 * VC4 panics when < 2 lines in FIFO. 932 * VC5 panics when less than 1 line in the FIFO. 933 */ 934 dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK | 935 SCALER_DISPCTRL_PANIC1_MASK | 936 SCALER_DISPCTRL_PANIC2_MASK); 937 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0); 938 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1); 939 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2); 940 941 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 942 943 return 0; 944 } 945 946 static int vc4_hvs_cob_init(struct vc4_hvs *hvs) 947 { 948 struct vc4_dev *vc4 = hvs->vc4; 949 u32 reg, top; 950 951 /* 952 * Recompute Composite Output Buffer (COB) allocations for the 953 * displays 954 */ 955 switch (vc4->gen) { 956 case VC4_GEN_4: 957 /* The COB is 20736 pixels, or just over 10 lines at 2048 wide. 958 * The bottom 2048 pixels are full 32bpp RGBA (intended for the 959 * TXP composing RGBA to memory), whilst the remainder are only 960 * 24bpp RGB. 961 * 962 * Assign 3 lines to channels 1 & 2, and just over 4 lines to 963 * channel 0. 964 */ 965 #define VC4_COB_SIZE 20736 966 #define VC4_COB_LINE_WIDTH 2048 967 #define VC4_COB_NUM_LINES 3 968 reg = 0; 969 top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES; 970 reg |= (top - 1) << 16; 971 HVS_WRITE(SCALER_DISPBASE2, reg); 972 reg = top; 973 top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES; 974 reg |= (top - 1) << 16; 975 HVS_WRITE(SCALER_DISPBASE1, reg); 976 reg = top; 977 top = VC4_COB_SIZE; 978 reg |= (top - 1) << 16; 979 HVS_WRITE(SCALER_DISPBASE0, reg); 980 break; 981 982 case VC4_GEN_5: 983 /* The COB is 44416 pixels, or 10.8 lines at 4096 wide. 984 * The bottom 4096 pixels are full RGBA (intended for the TXP 985 * composing RGBA to memory), whilst the remainder are only 986 * RGB. Addressing is always pixel wide. 987 * 988 * Assign 3 lines of 4096 to channels 1 & 2, and just over 4 989 * lines. to channel 0. 990 */ 991 #define VC5_COB_SIZE 44416 992 #define VC5_COB_LINE_WIDTH 4096 993 #define VC5_COB_NUM_LINES 3 994 reg = 0; 995 top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES; 996 reg |= top << 16; 997 HVS_WRITE(SCALER_DISPBASE2, reg); 998 top += 16; 999 reg = top; 1000 top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES; 1001 reg |= top << 16; 1002 HVS_WRITE(SCALER_DISPBASE1, reg); 1003 top += 16; 1004 reg = top; 1005 top = VC5_COB_SIZE; 1006 reg |= top << 16; 1007 HVS_WRITE(SCALER_DISPBASE0, reg); 1008 break; 1009 1010 default: 1011 return -EINVAL; 1012 } 1013 1014 return 0; 1015 } 1016 1017 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) 1018 { 1019 struct platform_device *pdev = to_platform_device(dev); 1020 struct drm_device *drm = dev_get_drvdata(master); 1021 struct vc4_dev *vc4 = to_vc4_dev(drm); 1022 struct vc4_hvs *hvs = NULL; 1023 void __iomem *regs; 1024 int ret; 1025 1026 regs = vc4_ioremap_regs(pdev, 0); 1027 if (IS_ERR(regs)) 1028 return PTR_ERR(regs); 1029 1030 hvs = __vc4_hvs_alloc(vc4, regs, pdev); 1031 if (IS_ERR(hvs)) 1032 return PTR_ERR(hvs); 1033 1034 hvs->regset.base = hvs->regs; 1035 hvs->regset.regs = vc4_hvs_regs; 1036 hvs->regset.nregs = ARRAY_SIZE(vc4_hvs_regs); 1037 1038 if (vc4->gen == VC4_GEN_5) { 1039 struct rpi_firmware *firmware; 1040 struct device_node *node; 1041 unsigned int max_rate; 1042 1043 node = rpi_firmware_find_node(); 1044 if (!node) 1045 return -EINVAL; 1046 1047 firmware = rpi_firmware_get(node); 1048 of_node_put(node); 1049 if (!firmware) 1050 return -EPROBE_DEFER; 1051 1052 hvs->core_clk = devm_clk_get(&pdev->dev, NULL); 1053 if (IS_ERR(hvs->core_clk)) { 1054 dev_err(&pdev->dev, "Couldn't get core clock\n"); 1055 return PTR_ERR(hvs->core_clk); 1056 } 1057 1058 max_rate = rpi_firmware_clk_get_max_rate(firmware, 1059 RPI_FIRMWARE_CORE_CLK_ID); 1060 rpi_firmware_put(firmware); 1061 if (max_rate >= 550000000) 1062 hvs->vc5_hdmi_enable_hdmi_20 = true; 1063 1064 if (max_rate >= 600000000) 1065 hvs->vc5_hdmi_enable_4096by2160 = true; 1066 1067 hvs->max_core_rate = max_rate; 1068 1069 ret = clk_prepare_enable(hvs->core_clk); 1070 if (ret) { 1071 dev_err(&pdev->dev, "Couldn't enable the core clock\n"); 1072 return ret; 1073 } 1074 } 1075 1076 if (vc4->gen == VC4_GEN_4) 1077 hvs->dlist = hvs->regs + SCALER_DLIST_START; 1078 else 1079 hvs->dlist = hvs->regs + SCALER5_DLIST_START; 1080 1081 ret = vc4_hvs_hw_init(hvs); 1082 if (ret) 1083 return ret; 1084 1085 /* Upload filter kernels. We only have the one for now, so we 1086 * keep it around for the lifetime of the driver. 1087 */ 1088 ret = vc4_hvs_upload_linear_kernel(hvs, 1089 &hvs->mitchell_netravali_filter, 1090 mitchell_netravali_1_3_1_3_kernel); 1091 if (ret) 1092 return ret; 1093 1094 ret = vc4_hvs_cob_init(hvs); 1095 if (ret) 1096 return ret; 1097 1098 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 1099 vc4_hvs_irq_handler, 0, "vc4 hvs", drm); 1100 if (ret) 1101 return ret; 1102 1103 return 0; 1104 } 1105 1106 static void vc4_hvs_unbind(struct device *dev, struct device *master, 1107 void *data) 1108 { 1109 struct drm_device *drm = dev_get_drvdata(master); 1110 struct vc4_dev *vc4 = to_vc4_dev(drm); 1111 struct vc4_hvs *hvs = vc4->hvs; 1112 struct drm_mm_node *node, *next; 1113 1114 if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter)) 1115 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter); 1116 1117 drm_mm_for_each_node_safe(node, next, &vc4->hvs->dlist_mm) 1118 drm_mm_remove_node(node); 1119 1120 drm_mm_takedown(&vc4->hvs->dlist_mm); 1121 1122 drm_mm_for_each_node_safe(node, next, &vc4->hvs->lbm_mm) 1123 drm_mm_remove_node(node); 1124 drm_mm_takedown(&vc4->hvs->lbm_mm); 1125 1126 clk_disable_unprepare(hvs->core_clk); 1127 1128 vc4->hvs = NULL; 1129 } 1130 1131 static const struct component_ops vc4_hvs_ops = { 1132 .bind = vc4_hvs_bind, 1133 .unbind = vc4_hvs_unbind, 1134 }; 1135 1136 static int vc4_hvs_dev_probe(struct platform_device *pdev) 1137 { 1138 return component_add(&pdev->dev, &vc4_hvs_ops); 1139 } 1140 1141 static void vc4_hvs_dev_remove(struct platform_device *pdev) 1142 { 1143 component_del(&pdev->dev, &vc4_hvs_ops); 1144 } 1145 1146 static const struct of_device_id vc4_hvs_dt_match[] = { 1147 { .compatible = "brcm,bcm2711-hvs" }, 1148 { .compatible = "brcm,bcm2835-hvs" }, 1149 {} 1150 }; 1151 1152 struct platform_driver vc4_hvs_driver = { 1153 .probe = vc4_hvs_dev_probe, 1154 .remove_new = vc4_hvs_dev_remove, 1155 .driver = { 1156 .name = "vc4_hvs", 1157 .of_match_table = vc4_hvs_dt_match, 1158 }, 1159 }; 1160