1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_audio_helper.h> 35 #include <drm/display/drm_hdmi_cec_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_hdmi_state_helper.h> 38 #include <drm/display/drm_scdc_helper.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_drv.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_simple_kms_helper.h> 44 #include <linux/clk.h> 45 #include <linux/component.h> 46 #include <linux/gpio/consumer.h> 47 #include <linux/i2c.h> 48 #include <linux/of.h> 49 #include <linux/of_address.h> 50 #include <linux/pm_runtime.h> 51 #include <linux/rational.h> 52 #include <linux/reset.h> 53 #include <sound/dmaengine_pcm.h> 54 #include <sound/hdmi-codec.h> 55 #include <sound/jack.h> 56 #include <sound/pcm_drm_eld.h> 57 #include <sound/pcm_params.h> 58 #include <sound/soc.h> 59 #include "media/cec.h" 60 #include "vc4_drv.h" 61 #include "vc4_hdmi.h" 62 #include "vc4_hdmi_regs.h" 63 #include "vc4_regs.h" 64 65 #define VC5_HDMI_HORZA_HFP_SHIFT 16 66 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 67 #define VC5_HDMI_HORZA_VPOS BIT(15) 68 #define VC5_HDMI_HORZA_HPOS BIT(14) 69 #define VC5_HDMI_HORZA_HAP_SHIFT 0 70 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 71 72 #define VC5_HDMI_HORZB_HBP_SHIFT 16 73 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 74 #define VC5_HDMI_HORZB_HSP_SHIFT 0 75 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 76 77 #define VC5_HDMI_VERTA_VSP_SHIFT 24 78 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 79 #define VC5_HDMI_VERTA_VFP_SHIFT 16 80 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 81 #define VC5_HDMI_VERTA_VAL_SHIFT 0 82 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 83 84 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 85 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 86 87 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 88 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 89 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 90 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 91 92 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 93 94 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 96 97 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 98 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 99 100 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 101 102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 104 105 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0) 106 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0) 107 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4) 108 109 # define VC4_HD_M_SW_RST BIT(2) 110 # define VC4_HD_M_ENABLE BIT(0) 111 112 #define HSM_MIN_CLOCK_FREQ 120000000 113 #define CEC_CLOCK_FREQ 40000 114 115 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 116 117 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 118 { 119 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 120 121 lockdep_assert_held(&vc4_hdmi->mutex); 122 123 if (!display->is_hdmi) 124 return false; 125 126 if (!display->hdmi.scdc.supported || 127 !display->hdmi.scdc.scrambling.supported) 128 return false; 129 130 return true; 131 } 132 133 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 134 unsigned int bpc, 135 enum hdmi_colorspace fmt) 136 { 137 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt); 138 139 return clock > HDMI_14_MAX_TMDS_CLK; 140 } 141 142 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 143 { 144 struct drm_debugfs_entry *entry = m->private; 145 struct vc4_hdmi *vc4_hdmi = entry->file.data; 146 struct drm_device *drm = vc4_hdmi->connector.dev; 147 struct drm_printer p = drm_seq_file_printer(m); 148 int idx; 149 150 if (!drm_dev_enter(drm, &idx)) 151 return -ENODEV; 152 153 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 154 155 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 156 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 157 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 158 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 159 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 160 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 161 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 162 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 163 164 pm_runtime_put(&vc4_hdmi->pdev->dev); 165 166 drm_dev_exit(idx); 167 168 return 0; 169 } 170 171 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 172 { 173 struct drm_device *drm = vc4_hdmi->connector.dev; 174 unsigned long flags; 175 int idx; 176 177 /* 178 * We can be called by our bind callback, when the 179 * connector->dev pointer might not be initialised yet. 180 */ 181 if (drm && !drm_dev_enter(drm, &idx)) 182 return; 183 184 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 185 186 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 187 udelay(1); 188 HDMI_WRITE(HDMI_M_CTL, 0); 189 190 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 191 192 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 193 VC4_HDMI_SW_RESET_HDMI | 194 VC4_HDMI_SW_RESET_FORMAT_DETECT); 195 196 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 197 198 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 199 200 if (drm) 201 drm_dev_exit(idx); 202 } 203 204 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 205 { 206 struct drm_device *drm = vc4_hdmi->connector.dev; 207 unsigned long flags; 208 int idx; 209 210 /* 211 * We can be called by our bind callback, when the 212 * connector->dev pointer might not be initialised yet. 213 */ 214 if (drm && !drm_dev_enter(drm, &idx)) 215 return; 216 217 reset_control_reset(vc4_hdmi->reset); 218 219 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 220 221 HDMI_WRITE(HDMI_DVP_CTL, 0); 222 223 HDMI_WRITE(HDMI_CLOCK_STOP, 224 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 225 226 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 227 228 if (drm) 229 drm_dev_exit(idx); 230 } 231 232 #ifdef CONFIG_DRM_VC4_HDMI_CEC 233 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 234 { 235 struct drm_device *drm = vc4_hdmi->connector.dev; 236 unsigned long cec_rate; 237 unsigned long flags; 238 u16 clk_cnt; 239 u32 value; 240 int idx; 241 242 /* 243 * This function is called by our runtime_resume implementation 244 * and thus at bind time, when we haven't registered our 245 * connector yet and thus don't have a pointer to the DRM 246 * device. 247 */ 248 if (drm && !drm_dev_enter(drm, &idx)) 249 return; 250 251 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 252 253 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 254 255 value = HDMI_READ(HDMI_CEC_CNTRL_1); 256 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 257 258 /* 259 * Set the clock divider: the hsm_clock rate and this divider 260 * setting will give a 40 kHz CEC clock. 261 */ 262 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 263 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 264 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 265 266 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 267 268 if (drm) 269 drm_dev_exit(idx); 270 } 271 #else 272 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 273 #endif 274 275 static int vc4_hdmi_reset_link(struct drm_connector *connector, 276 struct drm_modeset_acquire_ctx *ctx) 277 { 278 struct drm_device *drm; 279 struct vc4_hdmi *vc4_hdmi; 280 struct drm_connector_state *conn_state; 281 struct drm_crtc_state *crtc_state; 282 struct drm_crtc *crtc; 283 bool scrambling_needed; 284 u8 config; 285 int ret; 286 287 if (!connector) 288 return 0; 289 290 drm = connector->dev; 291 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 292 if (ret) 293 return ret; 294 295 conn_state = connector->state; 296 crtc = conn_state->crtc; 297 if (!crtc) 298 return 0; 299 300 ret = drm_modeset_lock(&crtc->mutex, ctx); 301 if (ret) 302 return ret; 303 304 crtc_state = crtc->state; 305 if (!crtc_state->active) 306 return 0; 307 308 vc4_hdmi = connector_to_vc4_hdmi(connector); 309 mutex_lock(&vc4_hdmi->mutex); 310 311 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 312 mutex_unlock(&vc4_hdmi->mutex); 313 return 0; 314 } 315 316 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 317 vc4_hdmi->output_bpc, 318 vc4_hdmi->output_format); 319 if (!scrambling_needed) { 320 mutex_unlock(&vc4_hdmi->mutex); 321 return 0; 322 } 323 324 if (conn_state->commit && 325 !try_wait_for_completion(&conn_state->commit->hw_done)) { 326 mutex_unlock(&vc4_hdmi->mutex); 327 return 0; 328 } 329 330 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 331 if (ret < 0) { 332 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 333 mutex_unlock(&vc4_hdmi->mutex); 334 return 0; 335 } 336 337 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 338 mutex_unlock(&vc4_hdmi->mutex); 339 return 0; 340 } 341 342 mutex_unlock(&vc4_hdmi->mutex); 343 344 /* 345 * HDMI 2.0 says that one should not send scrambled data 346 * prior to configuring the sink scrambling, and that 347 * TMDS clock/data transmission should be suspended when 348 * changing the TMDS clock rate in the sink. So let's 349 * just do a full modeset here, even though some sinks 350 * would be perfectly happy if were to just reconfigure 351 * the SCDC settings on the fly. 352 */ 353 return drm_atomic_helper_reset_crtc(crtc, ctx); 354 } 355 356 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 357 struct drm_modeset_acquire_ctx *ctx, 358 enum drm_connector_status status) 359 { 360 struct drm_connector *connector = &vc4_hdmi->connector; 361 int ret; 362 363 /* 364 * NOTE: This function should really be called with vc4_hdmi->mutex 365 * held, but doing so results in reentrancy issues since 366 * cec_s_phys_addr() might call .adap_enable, which leads to that 367 * funtion being called with our mutex held. 368 * 369 * A similar situation occurs with vc4_hdmi_reset_link() that 370 * will call into our KMS hooks if the scrambling was enabled. 371 * 372 * Concurrency isn't an issue at the moment since we don't share 373 * any state with any of the other frameworks so we can ignore 374 * the lock for now. 375 */ 376 377 drm_atomic_helper_connector_hdmi_hotplug(connector, status); 378 379 if (status != connector_status_connected) 380 return; 381 382 for (;;) { 383 ret = vc4_hdmi_reset_link(connector, ctx); 384 if (ret == -EDEADLK) { 385 drm_modeset_backoff(ctx); 386 continue; 387 } 388 389 break; 390 } 391 } 392 393 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 394 struct drm_modeset_acquire_ctx *ctx, 395 bool force) 396 { 397 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 398 enum drm_connector_status status = connector_status_disconnected; 399 int ret; 400 401 /* 402 * NOTE: This function should really take vc4_hdmi->mutex, but 403 * doing so results in reentrancy issues since 404 * vc4_hdmi_handle_hotplug() can call into other functions that 405 * would take the mutex while it's held here. 406 * 407 * Concurrency isn't an issue at the moment since we don't share 408 * any state with any of the other frameworks so we can ignore 409 * the lock for now. 410 */ 411 412 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 413 if (ret) { 414 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n", 415 ret); 416 return connector_status_unknown; 417 } 418 419 if (vc4_hdmi->hpd_gpio) { 420 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 421 status = connector_status_connected; 422 } else { 423 if (vc4_hdmi->variant->hp_detect && 424 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 425 status = connector_status_connected; 426 } 427 428 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 429 pm_runtime_put(&vc4_hdmi->pdev->dev); 430 431 return status; 432 } 433 434 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 435 { 436 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 437 int ret = 0; 438 439 ret = drm_edid_connector_add_modes(connector); 440 441 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 442 struct drm_device *drm = connector->dev; 443 const struct drm_display_mode *mode; 444 445 list_for_each_entry(mode, &connector->probed_modes, head) { 446 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) { 447 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 448 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 449 } 450 } 451 } 452 453 return ret; 454 } 455 456 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 457 struct drm_atomic_state *state) 458 { 459 struct drm_connector_state *old_state = 460 drm_atomic_get_old_connector_state(state, connector); 461 struct drm_connector_state *new_state = 462 drm_atomic_get_new_connector_state(state, connector); 463 struct drm_crtc *crtc = new_state->crtc; 464 465 if (!crtc) 466 return 0; 467 468 if (old_state->tv.margins.left != new_state->tv.margins.left || 469 old_state->tv.margins.right != new_state->tv.margins.right || 470 old_state->tv.margins.top != new_state->tv.margins.top || 471 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 472 struct drm_crtc_state *crtc_state; 473 int ret; 474 475 crtc_state = drm_atomic_get_crtc_state(state, crtc); 476 if (IS_ERR(crtc_state)) 477 return PTR_ERR(crtc_state); 478 479 /* 480 * Strictly speaking, we should be calling 481 * drm_atomic_helper_check_planes() after our call to 482 * drm_atomic_add_affected_planes(). However, the 483 * connector atomic_check is called as part of 484 * drm_atomic_helper_check_modeset() that already 485 * happens before a call to 486 * drm_atomic_helper_check_planes() in 487 * drm_atomic_helper_check(). 488 */ 489 ret = drm_atomic_add_affected_planes(state, crtc); 490 if (ret) 491 return ret; 492 } 493 494 if (old_state->colorspace != new_state->colorspace) { 495 struct drm_crtc_state *crtc_state; 496 497 crtc_state = drm_atomic_get_crtc_state(state, crtc); 498 if (IS_ERR(crtc_state)) 499 return PTR_ERR(crtc_state); 500 501 crtc_state->mode_changed = true; 502 } 503 504 return drm_atomic_helper_connector_hdmi_check(connector, state); 505 } 506 507 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 508 { 509 drm_atomic_helper_connector_reset(connector); 510 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); 511 drm_atomic_helper_connector_tv_margins_reset(connector); 512 } 513 514 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 515 .force = drm_atomic_helper_connector_hdmi_force, 516 .fill_modes = drm_helper_probe_single_connector_modes, 517 .reset = vc4_hdmi_connector_reset, 518 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 519 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 520 }; 521 522 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 523 .detect_ctx = vc4_hdmi_connector_detect_ctx, 524 .get_modes = vc4_hdmi_connector_get_modes, 525 .atomic_check = vc4_hdmi_connector_atomic_check, 526 .mode_valid = drm_hdmi_connector_mode_valid, 527 }; 528 529 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs; 530 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs; 531 532 static int vc4_hdmi_connector_init(struct drm_device *dev, 533 struct vc4_hdmi *vc4_hdmi) 534 { 535 struct drm_connector *connector = &vc4_hdmi->connector; 536 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 537 unsigned int max_bpc = 8; 538 int ret; 539 540 if (vc4_hdmi->variant->supports_hdr) 541 max_bpc = 12; 542 543 ret = drmm_connector_hdmi_init(dev, connector, 544 "Broadcom", "Videocore", 545 &vc4_hdmi_connector_funcs, 546 &vc4_hdmi_hdmi_connector_funcs, 547 DRM_MODE_CONNECTOR_HDMIA, 548 vc4_hdmi->ddc, 549 BIT(HDMI_COLORSPACE_RGB) | 550 BIT(HDMI_COLORSPACE_YUV422) | 551 BIT(HDMI_COLORSPACE_YUV444), 552 max_bpc); 553 if (ret) 554 return ret; 555 556 ret = drm_connector_hdmi_audio_init(connector, dev->dev, 557 &vc4_hdmi_audio_funcs, 558 8, 0, false, -1); 559 if (ret) 560 return ret; 561 562 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 563 564 /* 565 * Some of the properties below require access to state, like bpc. 566 * Allocate some default initial connector state with our reset helper. 567 */ 568 if (connector->funcs->reset) 569 connector->funcs->reset(connector); 570 571 /* Create and attach TV margin props to this connector. */ 572 ret = drm_mode_create_tv_margin_properties(dev); 573 if (ret) 574 return ret; 575 576 ret = drm_mode_create_hdmi_colorspace_property(connector, 0); 577 if (ret) 578 return ret; 579 580 drm_connector_attach_colorspace_property(connector); 581 drm_connector_attach_tv_margin_properties(connector); 582 583 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 584 DRM_CONNECTOR_POLL_DISCONNECT); 585 586 connector->interlace_allowed = 1; 587 connector->doublescan_allowed = 0; 588 connector->stereo_allowed = 1; 589 590 ret = drm_connector_attach_broadcast_rgb_property(connector); 591 if (ret) 592 return ret; 593 594 drm_connector_attach_encoder(connector, encoder); 595 596 return 0; 597 } 598 599 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi, 600 enum hdmi_infoframe_type type, 601 bool poll) 602 { 603 struct drm_device *drm = vc4_hdmi->connector.dev; 604 u32 packet_id = type - 0x80; 605 unsigned long flags; 606 int ret = 0; 607 int idx; 608 609 if (!drm_dev_enter(drm, &idx)) 610 return -ENODEV; 611 612 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 613 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 614 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 615 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 616 617 if (poll) { 618 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 619 BIT(packet_id)), 100); 620 } 621 622 drm_dev_exit(idx); 623 return ret; 624 } 625 626 static int vc4_hdmi_write_infoframe(struct drm_connector *connector, 627 enum hdmi_infoframe_type type, 628 const u8 *infoframe, size_t len) 629 { 630 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 631 struct drm_device *drm = connector->dev; 632 u32 packet_id = type - 0x80; 633 const struct vc4_hdmi_register *ram_packet_start = 634 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 635 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 636 u32 packet_reg_next = ram_packet_start->offset + 637 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 638 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 639 ram_packet_start->reg); 640 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 641 unsigned long flags; 642 ssize_t i; 643 int ret; 644 int idx; 645 646 if (!drm_dev_enter(drm, &idx)) 647 return 0; 648 649 if (len > sizeof(buffer)) { 650 ret = -ENOMEM; 651 goto out; 652 } 653 654 memcpy(buffer, infoframe, len); 655 656 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 657 VC4_HDMI_RAM_PACKET_ENABLE), 658 "Packet RAM has to be on to store the packet."); 659 660 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true); 661 if (ret) { 662 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret); 663 goto out; 664 } 665 666 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 667 668 for (i = 0; i < len; i += 7) { 669 writel(buffer[i + 0] << 0 | 670 buffer[i + 1] << 8 | 671 buffer[i + 2] << 16, 672 base + packet_reg); 673 packet_reg += 4; 674 675 writel(buffer[i + 3] << 0 | 676 buffer[i + 4] << 8 | 677 buffer[i + 5] << 16 | 678 buffer[i + 6] << 24, 679 base + packet_reg); 680 packet_reg += 4; 681 } 682 683 /* 684 * clear remainder of packet ram as it's included in the 685 * infoframe and triggers a checksum error on hdmi analyser 686 */ 687 for (; packet_reg < packet_reg_next; packet_reg += 4) 688 writel(0, base + packet_reg); 689 690 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 691 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 692 693 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 694 695 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 696 BIT(packet_id)), 100); 697 if (ret) 698 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret); 699 700 out: 701 drm_dev_exit(idx); 702 return ret; 703 } 704 705 #define SCRAMBLING_POLLING_DELAY_MS 1000 706 707 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 708 { 709 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 710 struct drm_connector *connector = &vc4_hdmi->connector; 711 struct drm_device *drm = connector->dev; 712 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 713 unsigned long flags; 714 int idx; 715 716 lockdep_assert_held(&vc4_hdmi->mutex); 717 718 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 719 return; 720 721 if (!vc4_hdmi_mode_needs_scrambling(mode, 722 vc4_hdmi->output_bpc, 723 vc4_hdmi->output_format)) 724 return; 725 726 if (!drm_dev_enter(drm, &idx)) 727 return; 728 729 drm_scdc_set_high_tmds_clock_ratio(connector, true); 730 drm_scdc_set_scrambling(connector, true); 731 732 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 733 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 734 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 735 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 736 737 drm_dev_exit(idx); 738 739 vc4_hdmi->scdc_enabled = true; 740 741 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 742 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 743 } 744 745 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 746 { 747 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 748 struct drm_connector *connector = &vc4_hdmi->connector; 749 struct drm_device *drm = connector->dev; 750 unsigned long flags; 751 int idx; 752 753 lockdep_assert_held(&vc4_hdmi->mutex); 754 755 if (!vc4_hdmi->scdc_enabled) 756 return; 757 758 vc4_hdmi->scdc_enabled = false; 759 760 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 761 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 762 763 if (!drm_dev_enter(drm, &idx)) 764 return; 765 766 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 767 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 768 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 769 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 770 771 drm_scdc_set_scrambling(connector, false); 772 drm_scdc_set_high_tmds_clock_ratio(connector, false); 773 774 drm_dev_exit(idx); 775 } 776 777 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 778 { 779 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 780 struct vc4_hdmi, 781 scrambling_work); 782 struct drm_connector *connector = &vc4_hdmi->connector; 783 784 if (drm_scdc_get_scrambling_status(connector)) 785 return; 786 787 drm_scdc_set_high_tmds_clock_ratio(connector, true); 788 drm_scdc_set_scrambling(connector, true); 789 790 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 791 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 792 } 793 794 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 795 struct drm_atomic_state *state) 796 { 797 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 798 struct drm_device *drm = vc4_hdmi->connector.dev; 799 struct vc4_dev *vc4 = to_vc4_dev(drm); 800 unsigned long flags; 801 int idx; 802 803 mutex_lock(&vc4_hdmi->mutex); 804 805 vc4_hdmi->packet_ram_enabled = false; 806 807 if (!drm_dev_enter(drm, &idx)) 808 goto out; 809 810 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 811 812 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 813 814 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 815 816 if (vc4->gen >= VC4_GEN_6_C) 817 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 818 VC4_HD_VID_CTL_BLANKPIX); 819 820 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 821 822 mdelay(1); 823 824 /* 825 * TODO: This should work on BCM2712, but doesn't for some 826 * reason and result in a system lockup. 827 */ 828 if (vc4->gen < VC4_GEN_6_C) { 829 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 830 HDMI_WRITE(HDMI_VID_CTL, 831 HDMI_READ(HDMI_VID_CTL) & 832 ~VC4_HD_VID_CTL_ENABLE); 833 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 834 } 835 836 vc4_hdmi_disable_scrambling(encoder); 837 838 drm_dev_exit(idx); 839 840 out: 841 mutex_unlock(&vc4_hdmi->mutex); 842 } 843 844 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 845 struct drm_atomic_state *state) 846 { 847 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 848 struct drm_device *drm = vc4_hdmi->connector.dev; 849 unsigned long flags; 850 int ret; 851 int idx; 852 853 mutex_lock(&vc4_hdmi->mutex); 854 855 if (!drm_dev_enter(drm, &idx)) 856 goto out; 857 858 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 859 HDMI_WRITE(HDMI_VID_CTL, 860 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 861 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 862 863 if (vc4_hdmi->variant->phy_disable) 864 vc4_hdmi->variant->phy_disable(vc4_hdmi); 865 866 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 867 clk_disable_unprepare(vc4_hdmi->pixel_clock); 868 869 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 870 if (ret < 0) 871 drm_err(drm, "Failed to release power domain: %d\n", ret); 872 873 drm_dev_exit(idx); 874 875 out: 876 mutex_unlock(&vc4_hdmi->mutex); 877 } 878 879 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 880 struct drm_connector_state *state, 881 const struct drm_display_mode *mode) 882 { 883 struct drm_device *drm = vc4_hdmi->connector.dev; 884 unsigned long flags; 885 u32 csc_ctl; 886 int idx; 887 888 if (!drm_dev_enter(drm, &idx)) 889 return; 890 891 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 892 893 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 894 VC4_HD_CSC_CTL_ORDER); 895 896 if (state->hdmi.is_limited_range) { 897 /* CEA VICs other than #1 requre limited range RGB 898 * output unless overridden by an AVI infoframe. 899 * Apply a colorspace conversion to squash 0-255 down 900 * to 16-235. The matrix here is: 901 * 902 * [ 0 0 0.8594 16] 903 * [ 0 0.8594 0 16] 904 * [ 0.8594 0 0 16] 905 * [ 0 0 0 1] 906 */ 907 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 908 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 909 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 910 VC4_HD_CSC_CTL_MODE); 911 912 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 913 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 914 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 915 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 916 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 917 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 918 } 919 920 /* The RGB order applies even when CSC is disabled. */ 921 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 922 923 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 924 925 drm_dev_exit(idx); 926 } 927 928 /* 929 * Matrices for (internal) RGB to RGB output. 930 * 931 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 932 */ 933 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = { 934 { 935 /* 936 * Full range - unity 937 * 938 * [ 1 0 0 0] 939 * [ 0 1 0 0] 940 * [ 0 0 1 0] 941 */ 942 { 0x2000, 0x0000, 0x0000, 0x0000 }, 943 { 0x0000, 0x2000, 0x0000, 0x0000 }, 944 { 0x0000, 0x0000, 0x2000, 0x0000 }, 945 }, 946 { 947 /* 948 * Limited range 949 * 950 * CEA VICs other than #1 require limited range RGB 951 * output unless overridden by an AVI infoframe. Apply a 952 * colorspace conversion to squash 0-255 down to 16-235. 953 * The matrix here is: 954 * 955 * [ 0.8594 0 0 16] 956 * [ 0 0.8594 0 16] 957 * [ 0 0 0.8594 16] 958 */ 959 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 960 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 961 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 962 }, 963 }; 964 965 /* 966 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace 967 * 968 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 969 */ 970 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = { 971 { 972 /* 973 * Full Range 974 * 975 * [ 0.299000 0.587000 0.114000 0 ] 976 * [ -0.168736 -0.331264 0.500000 128 ] 977 * [ 0.500000 -0.418688 -0.081312 128 ] 978 */ 979 { 0x0991, 0x12c9, 0x03a6, 0x0000 }, 980 { 0xfa9b, 0xf567, 0x1000, 0x2000 }, 981 { 0x1000, 0xf29b, 0xfd67, 0x2000 }, 982 }, 983 { 984 /* Limited Range 985 * 986 * [ 0.255785 0.502160 0.097523 16 ] 987 * [ -0.147644 -0.289856 0.437500 128 ] 988 * [ 0.437500 -0.366352 -0.071148 128 ] 989 */ 990 { 0x082f, 0x1012, 0x031f, 0x0400 }, 991 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 992 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 993 }, 994 }; 995 996 /* 997 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace 998 * 999 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1000 */ 1001 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = { 1002 { 1003 /* 1004 * Full Range 1005 * 1006 * [ 0.212600 0.715200 0.072200 0 ] 1007 * [ -0.114572 -0.385428 0.500000 128 ] 1008 * [ 0.500000 -0.454153 -0.045847 128 ] 1009 */ 1010 { 0x06ce, 0x16e3, 0x024f, 0x0000 }, 1011 { 0xfc56, 0xf3ac, 0x1000, 0x2000 }, 1012 { 0x1000, 0xf179, 0xfe89, 0x2000 }, 1013 }, 1014 { 1015 /* 1016 * Limited Range 1017 * 1018 * [ 0.181906 0.611804 0.061758 16 ] 1019 * [ -0.100268 -0.337232 0.437500 128 ] 1020 * [ 0.437500 -0.397386 -0.040114 128 ] 1021 */ 1022 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1023 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1024 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1025 }, 1026 }; 1027 1028 /* 1029 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace 1030 * 1031 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1032 */ 1033 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = { 1034 { 1035 /* 1036 * Full Range 1037 * 1038 * [ 0.262700 0.678000 0.059300 0 ] 1039 * [ -0.139630 -0.360370 0.500000 128 ] 1040 * [ 0.500000 -0.459786 -0.040214 128 ] 1041 */ 1042 { 0x0868, 0x15b2, 0x01e6, 0x0000 }, 1043 { 0xfb89, 0xf479, 0x1000, 0x2000 }, 1044 { 0x1000, 0xf14a, 0xfeb8, 0x2000 }, 1045 }, 1046 { 1047 /* Limited Range 1048 * 1049 * [ 0.224732 0.580008 0.050729 16 ] 1050 * [ -0.122176 -0.315324 0.437500 128 ] 1051 * [ 0.437500 -0.402312 -0.035188 128 ] 1052 */ 1053 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1054 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1055 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1056 }, 1057 }; 1058 1059 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1060 const u16 coeffs[3][4]) 1061 { 1062 lockdep_assert_held(&vc4_hdmi->hw_lock); 1063 1064 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1065 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1066 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1067 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1068 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1069 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1070 } 1071 1072 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi, 1073 const u16 coeffs[3][4]) 1074 { 1075 lockdep_assert_held(&vc4_hdmi->hw_lock); 1076 1077 /* YUV444 needs the CSC matrices using the channels in a different order */ 1078 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]); 1079 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]); 1080 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]); 1081 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]); 1082 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]); 1083 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]); 1084 } 1085 1086 static const u16 1087 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4] 1088 { 1089 switch (colorspace) { 1090 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC: 1091 case DRM_MODE_COLORIMETRY_XVYCC_601: 1092 case DRM_MODE_COLORIMETRY_SYCC_601: 1093 case DRM_MODE_COLORIMETRY_OPYCC_601: 1094 case DRM_MODE_COLORIMETRY_BT601_YCC: 1095 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited]; 1096 1097 default: 1098 case DRM_MODE_COLORIMETRY_NO_DATA: 1099 case DRM_MODE_COLORIMETRY_BT709_YCC: 1100 case DRM_MODE_COLORIMETRY_XVYCC_709: 1101 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED: 1102 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT: 1103 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited]; 1104 1105 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 1106 case DRM_MODE_COLORIMETRY_BT2020_YCC: 1107 case DRM_MODE_COLORIMETRY_BT2020_RGB: 1108 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 1109 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 1110 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited]; 1111 } 1112 } 1113 1114 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1115 struct drm_connector_state *state, 1116 const struct drm_display_mode *mode) 1117 { 1118 struct drm_device *drm = vc4_hdmi->connector.dev; 1119 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0; 1120 unsigned long flags; 1121 const u16 (*csc)[4]; 1122 u32 if_cfg = 0; 1123 u32 if_xbar = 0x543210; 1124 u32 csc_chan_ctl = 0; 1125 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1126 VC5_MT_CP_CSC_CTL_MODE); 1127 int idx; 1128 1129 if (!drm_dev_enter(drm, &idx)) 1130 return; 1131 1132 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1133 1134 switch (state->hdmi.output_format) { 1135 case HDMI_COLORSPACE_YUV444: 1136 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1137 1138 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc); 1139 break; 1140 1141 case HDMI_COLORSPACE_YUV422: 1142 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1143 1144 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1145 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1146 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1147 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1148 1149 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1150 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1151 1152 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1153 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1154 1155 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc); 1156 break; 1157 1158 case HDMI_COLORSPACE_RGB: 1159 if_xbar = 0x354021; 1160 1161 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]); 1162 break; 1163 1164 default: 1165 break; 1166 } 1167 1168 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1169 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1170 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1171 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1172 1173 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1174 1175 drm_dev_exit(idx); 1176 } 1177 1178 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1179 struct drm_connector_state *state, 1180 const struct drm_display_mode *mode) 1181 { 1182 struct drm_device *drm = vc4_hdmi->connector.dev; 1183 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1184 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1185 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1186 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1187 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1188 VC4_HDMI_VERTA_VSP) | 1189 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1190 VC4_HDMI_VERTA_VFP) | 1191 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1192 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1193 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1194 interlaced, 1195 VC4_HDMI_VERTB_VBP)); 1196 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1197 VC4_SET_FIELD(mode->crtc_vtotal - 1198 mode->crtc_vsync_end, 1199 VC4_HDMI_VERTB_VBP)); 1200 unsigned long flags; 1201 u32 reg; 1202 int idx; 1203 1204 if (!drm_dev_enter(drm, &idx)) 1205 return; 1206 1207 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1208 1209 HDMI_WRITE(HDMI_HORZA, 1210 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1211 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1212 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1213 VC4_HDMI_HORZA_HAP)); 1214 1215 HDMI_WRITE(HDMI_HORZB, 1216 VC4_SET_FIELD((mode->htotal - 1217 mode->hsync_end) * pixel_rep, 1218 VC4_HDMI_HORZB_HBP) | 1219 VC4_SET_FIELD((mode->hsync_end - 1220 mode->hsync_start) * pixel_rep, 1221 VC4_HDMI_HORZB_HSP) | 1222 VC4_SET_FIELD((mode->hsync_start - 1223 mode->hdisplay) * pixel_rep, 1224 VC4_HDMI_HORZB_HFP)); 1225 1226 HDMI_WRITE(HDMI_VERTA0, verta); 1227 HDMI_WRITE(HDMI_VERTA1, verta); 1228 1229 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1230 HDMI_WRITE(HDMI_VERTB1, vertb); 1231 1232 reg = HDMI_READ(HDMI_MISC_CONTROL); 1233 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1234 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1235 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1236 1237 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1238 1239 drm_dev_exit(idx); 1240 } 1241 1242 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1243 struct drm_connector_state *state, 1244 const struct drm_display_mode *mode) 1245 { 1246 struct drm_device *drm = vc4_hdmi->connector.dev; 1247 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1248 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1249 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1250 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1251 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1252 VC5_HDMI_VERTA_VSP) | 1253 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1254 VC5_HDMI_VERTA_VFP) | 1255 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1256 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1257 VC5_HDMI_VERTB_VSPO) | 1258 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1259 interlaced, 1260 VC4_HDMI_VERTB_VBP)); 1261 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1262 VC4_SET_FIELD(mode->crtc_vtotal - 1263 mode->crtc_vsync_end, 1264 VC4_HDMI_VERTB_VBP)); 1265 unsigned long flags; 1266 unsigned char gcp; 1267 u32 reg; 1268 int idx; 1269 1270 if (!drm_dev_enter(drm, &idx)) 1271 return; 1272 1273 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1274 1275 HDMI_WRITE(HDMI_HORZA, 1276 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1277 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1278 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1279 VC5_HDMI_HORZA_HAP) | 1280 VC4_SET_FIELD((mode->hsync_start - 1281 mode->hdisplay) * pixel_rep, 1282 VC5_HDMI_HORZA_HFP)); 1283 1284 HDMI_WRITE(HDMI_HORZB, 1285 VC4_SET_FIELD((mode->htotal - 1286 mode->hsync_end) * pixel_rep, 1287 VC5_HDMI_HORZB_HBP) | 1288 VC4_SET_FIELD((mode->hsync_end - 1289 mode->hsync_start) * pixel_rep, 1290 VC5_HDMI_HORZB_HSP)); 1291 1292 HDMI_WRITE(HDMI_VERTA0, verta); 1293 HDMI_WRITE(HDMI_VERTA1, verta); 1294 1295 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1296 HDMI_WRITE(HDMI_VERTB1, vertb); 1297 1298 switch (state->hdmi.output_bpc) { 1299 case 12: 1300 gcp = 6; 1301 break; 1302 case 10: 1303 gcp = 5; 1304 break; 1305 case 8: 1306 default: 1307 gcp = 0; 1308 break; 1309 } 1310 1311 /* 1312 * YCC422 is always 36-bit and not considered deep colour so 1313 * doesn't signal in GCP. 1314 */ 1315 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) { 1316 gcp = 0; 1317 } 1318 1319 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1320 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1321 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1322 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1323 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1324 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1325 1326 reg = HDMI_READ(HDMI_GCP_WORD_1); 1327 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1328 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1329 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK; 1330 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE; 1331 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1332 1333 reg = HDMI_READ(HDMI_GCP_CONFIG); 1334 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1335 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1336 1337 reg = HDMI_READ(HDMI_MISC_CONTROL); 1338 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1339 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1340 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1341 1342 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1343 1344 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1345 1346 drm_dev_exit(idx); 1347 } 1348 1349 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1350 { 1351 struct drm_device *drm = vc4_hdmi->connector.dev; 1352 unsigned long flags; 1353 u32 drift; 1354 int ret; 1355 int idx; 1356 1357 if (!drm_dev_enter(drm, &idx)) 1358 return; 1359 1360 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1361 1362 drift = HDMI_READ(HDMI_FIFO_CTL); 1363 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1364 1365 HDMI_WRITE(HDMI_FIFO_CTL, 1366 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1367 HDMI_WRITE(HDMI_FIFO_CTL, 1368 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1369 1370 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1371 1372 usleep_range(1000, 1100); 1373 1374 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1375 1376 HDMI_WRITE(HDMI_FIFO_CTL, 1377 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1378 HDMI_WRITE(HDMI_FIFO_CTL, 1379 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1380 1381 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1382 1383 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1384 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1385 WARN_ONCE(ret, "Timeout waiting for " 1386 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1387 1388 drm_dev_exit(idx); 1389 } 1390 1391 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1392 struct drm_atomic_state *state) 1393 { 1394 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1395 struct drm_device *drm = vc4_hdmi->connector.dev; 1396 struct drm_connector *connector = &vc4_hdmi->connector; 1397 struct drm_connector_state *conn_state = 1398 drm_atomic_get_new_connector_state(state, connector); 1399 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1400 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate; 1401 unsigned long bvb_rate, hsm_rate; 1402 unsigned long flags; 1403 int ret; 1404 int idx; 1405 1406 mutex_lock(&vc4_hdmi->mutex); 1407 1408 if (!drm_dev_enter(drm, &idx)) 1409 goto out; 1410 1411 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1412 if (ret < 0) { 1413 drm_err(drm, "Failed to retain power domain: %d\n", ret); 1414 goto err_dev_exit; 1415 } 1416 1417 /* 1418 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1419 * be faster than pixel clock, infinitesimally faster, tested in 1420 * simulation. Otherwise, exact value is unimportant for HDMI 1421 * operation." This conflicts with bcm2835's vc4 documentation, which 1422 * states HSM's clock has to be at least 108% of the pixel clock. 1423 * 1424 * Real life tests reveal that vc4's firmware statement holds up, and 1425 * users are able to use pixel clocks closer to HSM's, namely for 1426 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1427 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1428 * 162MHz. 1429 * 1430 * Additionally, the AXI clock needs to be at least 25% of 1431 * pixel clock, but HSM ends up being the limiting factor. 1432 */ 1433 hsm_rate = max_t(unsigned long, 1434 HSM_MIN_CLOCK_FREQ, 1435 div_u64(tmds_char_rate, 100) * 101); 1436 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1437 if (ret) { 1438 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret); 1439 goto err_put_runtime_pm; 1440 } 1441 1442 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1443 if (ret) { 1444 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret); 1445 goto err_put_runtime_pm; 1446 } 1447 1448 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1449 if (ret) { 1450 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret); 1451 goto err_put_runtime_pm; 1452 } 1453 1454 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1455 1456 if (tmds_char_rate > 297000000) 1457 bvb_rate = 300000000; 1458 else if (tmds_char_rate > 148500000) 1459 bvb_rate = 150000000; 1460 else 1461 bvb_rate = 75000000; 1462 1463 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1464 if (ret) { 1465 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret); 1466 goto err_disable_pixel_clock; 1467 } 1468 1469 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1470 if (ret) { 1471 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret); 1472 goto err_disable_pixel_clock; 1473 } 1474 1475 if (vc4_hdmi->variant->phy_init) 1476 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state); 1477 1478 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1479 1480 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1481 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1482 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1483 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1484 1485 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1486 1487 if (vc4_hdmi->variant->set_timings) 1488 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1489 1490 drm_dev_exit(idx); 1491 1492 mutex_unlock(&vc4_hdmi->mutex); 1493 1494 return; 1495 1496 err_disable_pixel_clock: 1497 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1498 err_put_runtime_pm: 1499 pm_runtime_put(&vc4_hdmi->pdev->dev); 1500 err_dev_exit: 1501 drm_dev_exit(idx); 1502 out: 1503 mutex_unlock(&vc4_hdmi->mutex); 1504 return; 1505 } 1506 1507 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1508 struct drm_atomic_state *state) 1509 { 1510 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1511 struct drm_device *drm = vc4_hdmi->connector.dev; 1512 struct drm_connector *connector = &vc4_hdmi->connector; 1513 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1514 struct drm_connector_state *conn_state = 1515 drm_atomic_get_new_connector_state(state, connector); 1516 unsigned long flags; 1517 int idx; 1518 1519 mutex_lock(&vc4_hdmi->mutex); 1520 1521 if (!drm_dev_enter(drm, &idx)) 1522 goto out; 1523 1524 if (vc4_hdmi->variant->csc_setup) 1525 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1526 1527 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1528 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1529 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1530 1531 drm_dev_exit(idx); 1532 1533 out: 1534 mutex_unlock(&vc4_hdmi->mutex); 1535 } 1536 1537 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1538 struct drm_atomic_state *state) 1539 { 1540 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1541 struct drm_connector *connector = &vc4_hdmi->connector; 1542 struct drm_device *drm = connector->dev; 1543 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1544 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1545 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1546 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1547 unsigned long flags; 1548 int ret; 1549 int idx; 1550 1551 mutex_lock(&vc4_hdmi->mutex); 1552 1553 if (!drm_dev_enter(drm, &idx)) 1554 goto out; 1555 1556 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1557 1558 HDMI_WRITE(HDMI_VID_CTL, 1559 (HDMI_READ(HDMI_VID_CTL) & 1560 ~(VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) | 1561 VC4_HD_VID_CTL_ENABLE | 1562 VC4_HD_VID_CTL_CLRRGB | 1563 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1564 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1565 VC4_HD_VID_CTL_BLANK_INSERT_EN | 1566 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1567 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1568 1569 HDMI_WRITE(HDMI_VID_CTL, 1570 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1571 1572 if (display->is_hdmi) { 1573 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1574 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1575 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1576 1577 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1578 1579 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1580 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1581 WARN_ONCE(ret, "Timeout waiting for " 1582 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1583 } else { 1584 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1585 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1586 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1587 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1588 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1589 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1590 1591 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1592 1593 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1594 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1595 WARN_ONCE(ret, "Timeout waiting for " 1596 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1597 } 1598 1599 if (display->is_hdmi) { 1600 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1601 1602 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1603 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1604 1605 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1606 VC4_HDMI_RAM_PACKET_ENABLE); 1607 1608 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1609 vc4_hdmi->packet_ram_enabled = true; 1610 1611 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 1612 } 1613 1614 vc4_hdmi_recenter_fifo(vc4_hdmi); 1615 vc4_hdmi_enable_scrambling(encoder); 1616 1617 drm_dev_exit(idx); 1618 1619 out: 1620 mutex_unlock(&vc4_hdmi->mutex); 1621 } 1622 1623 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1624 struct drm_crtc_state *crtc_state, 1625 struct drm_connector_state *conn_state) 1626 { 1627 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1628 1629 mutex_lock(&vc4_hdmi->mutex); 1630 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1631 &crtc_state->adjusted_mode); 1632 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc; 1633 vc4_hdmi->output_format = conn_state->hdmi.output_format; 1634 mutex_unlock(&vc4_hdmi->mutex); 1635 } 1636 1637 static enum drm_mode_status 1638 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector, 1639 const struct drm_display_mode *mode, 1640 unsigned long long clock) 1641 { 1642 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1643 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 1644 1645 if (clock > vc4_hdmi->variant->max_pixel_clock) 1646 return MODE_CLOCK_HIGH; 1647 1648 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 1649 return MODE_CLOCK_HIGH; 1650 1651 /* 4096x2160@60 is not reliable without overclocking core */ 1652 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 1653 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 1654 drm_mode_vrefresh(mode) >= 50) 1655 return MODE_CLOCK_HIGH; 1656 1657 return MODE_OK; 1658 } 1659 1660 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = { 1661 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid, 1662 .write_infoframe = vc4_hdmi_write_infoframe, 1663 }; 1664 1665 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1666 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1667 1668 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1669 struct drm_crtc_state *crtc_state, 1670 struct drm_connector_state *conn_state) 1671 { 1672 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1673 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1674 unsigned long long tmds_char_rate = mode->clock * 1000; 1675 unsigned long long tmds_bit_rate; 1676 1677 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1678 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1679 /* Only try to fixup DBLCLK modes to get 480i and 576i 1680 * working. 1681 * A generic solution for all modes with odd horizontal 1682 * timing values seems impossible based on trying to 1683 * solve it for 1366x768 monitors. 1684 */ 1685 if ((mode->hsync_start - mode->hdisplay) & 1) 1686 mode->hsync_start--; 1687 if ((mode->hsync_end - mode->hsync_start) & 1) 1688 mode->hsync_end--; 1689 } 1690 1691 /* Now check whether we still have odd values remaining */ 1692 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1693 (mode->hsync_end % 2) || (mode->htotal % 2)) 1694 return -EINVAL; 1695 } 1696 1697 /* 1698 * The 1440p@60 pixel rate is in the same range than the first 1699 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1700 * bandwidth). Slightly lower the frequency to bring it out of 1701 * the WiFi range. 1702 */ 1703 tmds_bit_rate = tmds_char_rate * 10; 1704 if (vc4_hdmi->disable_wifi_frequencies && 1705 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1706 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1707 mode->clock = 238560; 1708 tmds_char_rate = mode->clock * 1000; 1709 } 1710 1711 return 0; 1712 } 1713 1714 static enum drm_mode_status 1715 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1716 const struct drm_display_mode *mode) 1717 { 1718 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1719 1720 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1721 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1722 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1723 (mode->hsync_end % 2) || (mode->htotal % 2))) 1724 return MODE_H_ILLEGAL; 1725 1726 return MODE_OK; 1727 } 1728 1729 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1730 .atomic_check = vc4_hdmi_encoder_atomic_check, 1731 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1732 .mode_valid = vc4_hdmi_encoder_mode_valid, 1733 }; 1734 1735 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 1736 { 1737 struct drm_device *drm = encoder->dev; 1738 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1739 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1740 1741 drm_debugfs_add_file(drm, variant->debugfs_name, 1742 vc4_hdmi_debugfs_regs, vc4_hdmi); 1743 1744 return 0; 1745 } 1746 1747 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 1748 .late_register = vc4_hdmi_late_register, 1749 }; 1750 1751 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1752 { 1753 int i; 1754 u32 channel_map = 0; 1755 1756 for (i = 0; i < 8; i++) { 1757 if (channel_mask & BIT(i)) 1758 channel_map |= i << (3 * i); 1759 } 1760 return channel_map; 1761 } 1762 1763 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1764 { 1765 int i; 1766 u32 channel_map = 0; 1767 1768 for (i = 0; i < 8; i++) { 1769 if (channel_mask & BIT(i)) 1770 channel_map |= i << (4 * i); 1771 } 1772 return channel_map; 1773 } 1774 1775 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1776 { 1777 struct drm_device *drm = vc4_hdmi->connector.dev; 1778 unsigned long flags; 1779 u32 hotplug; 1780 int idx; 1781 1782 if (!drm_dev_enter(drm, &idx)) 1783 return false; 1784 1785 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1786 hotplug = HDMI_READ(HDMI_HOTPLUG); 1787 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1788 1789 drm_dev_exit(idx); 1790 1791 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1792 } 1793 1794 /* HDMI audio codec callbacks */ 1795 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1796 unsigned int samplerate) 1797 { 1798 struct drm_device *drm = vc4_hdmi->connector.dev; 1799 u32 hsm_clock; 1800 unsigned long flags; 1801 unsigned long n, m; 1802 int idx; 1803 1804 if (!drm_dev_enter(drm, &idx)) 1805 return; 1806 1807 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1808 rational_best_approximation(hsm_clock, samplerate, 1809 VC4_HD_MAI_SMP_N_MASK >> 1810 VC4_HD_MAI_SMP_N_SHIFT, 1811 (VC4_HD_MAI_SMP_M_MASK >> 1812 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1813 &n, &m); 1814 1815 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1816 HDMI_WRITE(HDMI_MAI_SMP, 1817 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1818 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1819 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1820 1821 drm_dev_exit(idx); 1822 } 1823 1824 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1825 { 1826 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1827 u32 n, cts; 1828 u64 tmp; 1829 1830 lockdep_assert_held(&vc4_hdmi->mutex); 1831 lockdep_assert_held(&vc4_hdmi->hw_lock); 1832 1833 n = 128 * samplerate / 1000; 1834 tmp = (u64)(mode->clock * 1000) * n; 1835 do_div(tmp, 128 * samplerate); 1836 cts = tmp; 1837 1838 HDMI_WRITE(HDMI_CRP_CFG, 1839 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1840 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1841 1842 /* 1843 * We could get slightly more accurate clocks in some cases by 1844 * providing a CTS_1 value. The two CTS values are alternated 1845 * between based on the period fields 1846 */ 1847 HDMI_WRITE(HDMI_CTS_0, cts); 1848 HDMI_WRITE(HDMI_CTS_1, cts); 1849 } 1850 1851 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1852 { 1853 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1854 1855 return snd_soc_card_get_drvdata(card); 1856 } 1857 1858 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1859 { 1860 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1861 1862 lockdep_assert_held(&vc4_hdmi->mutex); 1863 1864 /* 1865 * If the encoder is currently in DVI mode, treat the codec DAI 1866 * as missing. 1867 */ 1868 if (!display->is_hdmi) 1869 return false; 1870 1871 return true; 1872 } 1873 1874 static int vc4_hdmi_audio_startup(struct drm_connector *connector) 1875 { 1876 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1877 struct drm_device *drm = vc4_hdmi->connector.dev; 1878 unsigned long flags; 1879 int ret = 0; 1880 int idx; 1881 1882 mutex_lock(&vc4_hdmi->mutex); 1883 1884 if (!drm_dev_enter(drm, &idx)) { 1885 ret = -ENODEV; 1886 goto out; 1887 } 1888 1889 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1890 ret = -ENOTSUPP; 1891 goto out_dev_exit; 1892 } 1893 1894 vc4_hdmi->audio.streaming = true; 1895 1896 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1897 HDMI_WRITE(HDMI_MAI_CTL, 1898 VC4_HD_MAI_CTL_RESET | 1899 VC4_HD_MAI_CTL_FLUSH | 1900 VC4_HD_MAI_CTL_DLATE | 1901 VC4_HD_MAI_CTL_ERRORE | 1902 VC4_HD_MAI_CTL_ERRORF); 1903 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1904 1905 if (vc4_hdmi->variant->phy_rng_enable) 1906 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1907 1908 out_dev_exit: 1909 drm_dev_exit(idx); 1910 out: 1911 mutex_unlock(&vc4_hdmi->mutex); 1912 1913 return ret; 1914 } 1915 1916 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1917 { 1918 struct device *dev = &vc4_hdmi->pdev->dev; 1919 unsigned long flags; 1920 int ret; 1921 1922 lockdep_assert_held(&vc4_hdmi->mutex); 1923 1924 vc4_hdmi->audio.streaming = false; 1925 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false); 1926 if (ret) 1927 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1928 1929 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1930 1931 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1932 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1933 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1934 1935 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1936 } 1937 1938 static void vc4_hdmi_audio_shutdown(struct drm_connector *connector) 1939 { 1940 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1941 struct drm_device *drm = vc4_hdmi->connector.dev; 1942 unsigned long flags; 1943 int idx; 1944 1945 mutex_lock(&vc4_hdmi->mutex); 1946 1947 if (!drm_dev_enter(drm, &idx)) 1948 goto out; 1949 1950 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1951 1952 HDMI_WRITE(HDMI_MAI_CTL, 1953 VC4_HD_MAI_CTL_DLATE | 1954 VC4_HD_MAI_CTL_ERRORE | 1955 VC4_HD_MAI_CTL_ERRORF); 1956 1957 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1958 1959 if (vc4_hdmi->variant->phy_rng_disable) 1960 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1961 1962 vc4_hdmi->audio.streaming = false; 1963 vc4_hdmi_audio_reset(vc4_hdmi); 1964 1965 drm_dev_exit(idx); 1966 1967 out: 1968 mutex_unlock(&vc4_hdmi->mutex); 1969 } 1970 1971 static int sample_rate_to_mai_fmt(int samplerate) 1972 { 1973 switch (samplerate) { 1974 case 8000: 1975 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1976 case 11025: 1977 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1978 case 12000: 1979 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1980 case 16000: 1981 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1982 case 22050: 1983 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1984 case 24000: 1985 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1986 case 32000: 1987 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1988 case 44100: 1989 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1990 case 48000: 1991 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1992 case 64000: 1993 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1994 case 88200: 1995 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1996 case 96000: 1997 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1998 case 128000: 1999 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2000 case 176400: 2001 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2002 case 192000: 2003 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2004 default: 2005 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2006 } 2007 } 2008 2009 /* HDMI audio codec callbacks */ 2010 static int vc4_hdmi_audio_prepare(struct drm_connector *connector, 2011 struct hdmi_codec_daifmt *daifmt, 2012 struct hdmi_codec_params *params) 2013 { 2014 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2015 struct drm_device *drm = vc4_hdmi->connector.dev; 2016 struct vc4_dev *vc4 = to_vc4_dev(drm); 2017 unsigned int sample_rate = params->sample_rate; 2018 unsigned int channels = params->channels; 2019 unsigned long flags; 2020 u32 audio_packet_config, channel_mask; 2021 u32 channel_map; 2022 u32 mai_audio_format; 2023 u32 mai_sample_rate; 2024 int ret = 0; 2025 int idx; 2026 2027 dev_dbg(&vc4_hdmi->pdev->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2028 sample_rate, params->sample_width, channels); 2029 2030 mutex_lock(&vc4_hdmi->mutex); 2031 2032 if (!drm_dev_enter(drm, &idx)) { 2033 ret = -ENODEV; 2034 goto out; 2035 } 2036 2037 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2038 ret = -EINVAL; 2039 goto out_dev_exit; 2040 } 2041 2042 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2043 2044 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2045 HDMI_WRITE(HDMI_MAI_CTL, 2046 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2047 VC4_HD_MAI_CTL_WHOLSMP | 2048 VC4_HD_MAI_CTL_CHALIGN | 2049 VC4_HD_MAI_CTL_ENABLE); 2050 2051 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2052 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2053 params->channels == 8) 2054 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2055 else 2056 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2057 HDMI_WRITE(HDMI_MAI_FMT, 2058 VC4_SET_FIELD(mai_sample_rate, 2059 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2060 VC4_SET_FIELD(mai_audio_format, 2061 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2062 2063 /* The B frame identifier should match the value used by alsa-lib (8) */ 2064 audio_packet_config = 2065 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2066 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2067 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2068 2069 channel_mask = GENMASK(channels - 1, 0); 2070 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2071 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2072 2073 /* Set the MAI threshold */ 2074 switch (vc4->gen) { 2075 case VC4_GEN_6_D: 2076 HDMI_WRITE(HDMI_MAI_THR, 2077 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) | 2078 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) | 2079 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) | 2080 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW)); 2081 break; 2082 case VC4_GEN_6_C: 2083 case VC4_GEN_5: 2084 HDMI_WRITE(HDMI_MAI_THR, 2085 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 2086 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 2087 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) | 2088 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW)); 2089 break; 2090 case VC4_GEN_4: 2091 HDMI_WRITE(HDMI_MAI_THR, 2092 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) | 2093 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) | 2094 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) | 2095 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW)); 2096 break; 2097 default: 2098 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen); 2099 break; 2100 } 2101 2102 HDMI_WRITE(HDMI_MAI_CONFIG, 2103 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2104 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2105 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2106 2107 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2108 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2109 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2110 2111 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2112 2113 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2114 2115 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, 2116 ¶ms->cea); 2117 if (ret) 2118 goto out_dev_exit; 2119 2120 out_dev_exit: 2121 drm_dev_exit(idx); 2122 out: 2123 mutex_unlock(&vc4_hdmi->mutex); 2124 2125 return ret; 2126 } 2127 2128 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2129 .name = "vc4-hdmi-cpu-dai-component", 2130 .legacy_dai_naming = 1, 2131 }; 2132 2133 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2134 { 2135 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2136 2137 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2138 2139 return 0; 2140 } 2141 2142 static const struct snd_soc_dai_ops vc4_snd_dai_ops = { 2143 .probe = vc4_hdmi_audio_cpu_dai_probe, 2144 }; 2145 2146 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2147 .name = "vc4-hdmi-cpu-dai", 2148 .ops = &vc4_snd_dai_ops, 2149 .playback = { 2150 .stream_name = "Playback", 2151 .channels_min = 1, 2152 .channels_max = 8, 2153 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2154 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2155 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2156 SNDRV_PCM_RATE_192000, 2157 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2158 }, 2159 }; 2160 2161 static const struct snd_dmaengine_pcm_config pcm_conf = { 2162 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2163 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2164 }; 2165 2166 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs = { 2167 .startup = vc4_hdmi_audio_startup, 2168 .prepare = vc4_hdmi_audio_prepare, 2169 .shutdown = vc4_hdmi_audio_shutdown, 2170 }; 2171 2172 static int vc4_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd) 2173 { 2174 struct vc4_hdmi *vc4_hdmi = snd_soc_card_get_drvdata(rtd->card); 2175 struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component; 2176 int ret; 2177 2178 ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT, 2179 &vc4_hdmi->hdmi_jack); 2180 if (ret) { 2181 dev_err(rtd->dev, "HDMI Jack creation failed: %d\n", ret); 2182 return ret; 2183 } 2184 2185 return snd_soc_component_set_jack(component, &vc4_hdmi->hdmi_jack, NULL); 2186 } 2187 2188 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2189 { 2190 const struct vc4_hdmi_register *mai_data = 2191 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2192 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2193 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2194 struct device *dev = &vc4_hdmi->pdev->dev; 2195 const __be32 *addr; 2196 int index, len; 2197 int ret; 2198 2199 /* 2200 * ASoC makes it a bit hard to retrieve a pointer to the 2201 * vc4_hdmi structure. Registering the card will overwrite our 2202 * device drvdata with a pointer to the snd_soc_card structure, 2203 * which can then be used to retrieve whatever drvdata we want 2204 * to associate. 2205 * 2206 * However, that doesn't fly in the case where we wouldn't 2207 * register an ASoC card (because of an old DT that is missing 2208 * the dmas properties for example), then the card isn't 2209 * registered and the device drvdata wouldn't be set. 2210 * 2211 * We can deal with both cases by making sure a snd_soc_card 2212 * pointer and a vc4_hdmi structure are pointing to the same 2213 * memory address, so we can treat them indistinctly without any 2214 * issue. 2215 */ 2216 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2217 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2218 2219 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2220 dev_warn(dev, 2221 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2222 return 0; 2223 } 2224 2225 if (mai_data->reg != VC4_HD) { 2226 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2227 return -EINVAL; 2228 } 2229 2230 /* 2231 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2232 * the bus address specified in the DT, because the physical address 2233 * (the one returned by platform_get_resource()) is not appropriate 2234 * for DMA transfers. 2235 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2236 */ 2237 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2238 /* Before BCM2711, we don't have a named register range */ 2239 if (index < 0) 2240 index = 1; 2241 2242 addr = of_get_address(dev->of_node, index, NULL, NULL); 2243 if (!addr) 2244 return -EINVAL; 2245 2246 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2247 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2248 vc4_hdmi->audio.dma_data.maxburst = 2; 2249 2250 /* 2251 * NOTE: Strictly speaking, we should probably use a DRM-managed 2252 * registration there to avoid removing all the audio components 2253 * by the time the driver doesn't have any user anymore. 2254 * 2255 * However, the ASoC core uses a number of devm_kzalloc calls 2256 * when registering, even when using non-device-managed 2257 * functions (such as in snd_soc_register_component()). 2258 * 2259 * If we call snd_soc_unregister_component() in a DRM-managed 2260 * action, the device-managed actions have already been executed 2261 * and thus we would access memory that has been freed. 2262 * 2263 * Using device-managed hooks here probably leaves us open to a 2264 * bunch of issues if userspace still has a handle on the ALSA 2265 * device when the device is removed. However, this is mitigated 2266 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2267 * path to prevent the access to the device resources if it 2268 * isn't there anymore. 2269 * 2270 * Then, the vc4_hdmi structure is DRM-managed and thus only 2271 * freed whenever the last user has closed the DRM device file. 2272 * It should thus outlive ALSA in most situations. 2273 */ 2274 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2275 if (ret) { 2276 dev_err(dev, "Could not register PCM component: %d\n", ret); 2277 return ret; 2278 } 2279 2280 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2281 &vc4_hdmi_audio_cpu_dai_drv, 1); 2282 if (ret) { 2283 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2284 return ret; 2285 } 2286 2287 ret = drm_connector_hdmi_audio_init(&vc4_hdmi->connector, dev, 2288 &vc4_hdmi_audio_funcs, 8, 0, false, 2289 -1); 2290 if (ret) 2291 return ret; 2292 2293 dai_link->cpus = &vc4_hdmi->audio.cpu; 2294 dai_link->codecs = &vc4_hdmi->audio.codec; 2295 dai_link->platforms = &vc4_hdmi->audio.platform; 2296 2297 dai_link->num_cpus = 1; 2298 dai_link->num_codecs = 1; 2299 dai_link->num_platforms = 1; 2300 2301 dai_link->name = "MAI"; 2302 dai_link->stream_name = "MAI PCM"; 2303 dai_link->codecs->dai_name = "i2s-hifi"; 2304 dai_link->cpus->dai_name = dev_name(dev); 2305 dai_link->codecs->name = dev_name(&vc4_hdmi->connector.hdmi_audio.codec_pdev->dev); 2306 dai_link->platforms->name = dev_name(dev); 2307 dai_link->init = vc4_hdmi_codec_init; 2308 2309 card->dai_link = dai_link; 2310 card->num_links = 1; 2311 card->name = vc4_hdmi->variant->card_name; 2312 card->driver_name = "vc4-hdmi"; 2313 card->dev = dev; 2314 card->owner = THIS_MODULE; 2315 2316 /* 2317 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2318 * stores a pointer to the snd card object in dev->driver_data. This 2319 * means we cannot use it for something else. The hdmi back-pointer is 2320 * now stored in card->drvdata and should be retrieved with 2321 * snd_soc_card_get_drvdata() if needed. 2322 */ 2323 snd_soc_card_set_drvdata(card, vc4_hdmi); 2324 ret = devm_snd_soc_register_card(dev, card); 2325 if (ret) 2326 dev_err_probe(dev, ret, "Could not register sound card\n"); 2327 2328 return ret; 2329 2330 } 2331 2332 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2333 { 2334 struct vc4_hdmi *vc4_hdmi = priv; 2335 struct drm_connector *connector = &vc4_hdmi->connector; 2336 struct drm_device *dev = connector->dev; 2337 2338 if (dev && dev->registered) 2339 drm_connector_helper_hpd_irq_event(connector); 2340 2341 return IRQ_HANDLED; 2342 } 2343 2344 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2345 { 2346 struct drm_connector *connector = &vc4_hdmi->connector; 2347 struct platform_device *pdev = vc4_hdmi->pdev; 2348 int ret; 2349 2350 if (vc4_hdmi->variant->external_irq_controller) { 2351 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2352 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2353 2354 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2355 NULL, 2356 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2357 "vc4 hdmi hpd connected", vc4_hdmi); 2358 if (ret) 2359 return ret; 2360 2361 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2362 NULL, 2363 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2364 "vc4 hdmi hpd disconnected", vc4_hdmi); 2365 if (ret) 2366 return ret; 2367 2368 connector->polled = DRM_CONNECTOR_POLL_HPD; 2369 } 2370 2371 return 0; 2372 } 2373 2374 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2375 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2376 { 2377 struct vc4_hdmi *vc4_hdmi = priv; 2378 2379 if (vc4_hdmi->cec_rx_msg.len) 2380 drm_connector_hdmi_cec_received_msg(&vc4_hdmi->connector, 2381 &vc4_hdmi->cec_rx_msg); 2382 2383 return IRQ_HANDLED; 2384 } 2385 2386 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2387 { 2388 struct vc4_hdmi *vc4_hdmi = priv; 2389 2390 if (vc4_hdmi->cec_tx_ok) { 2391 drm_connector_hdmi_cec_transmit_done(&vc4_hdmi->connector, 2392 CEC_TX_STATUS_OK, 2393 0, 0, 0, 0); 2394 } else { 2395 /* 2396 * This CEC implementation makes 1 retry, so if we 2397 * get a NACK, then that means it made 2 attempts. 2398 */ 2399 drm_connector_hdmi_cec_transmit_done(&vc4_hdmi->connector, 2400 CEC_TX_STATUS_NACK, 2401 0, 2, 0, 0); 2402 } 2403 return IRQ_HANDLED; 2404 } 2405 2406 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2407 { 2408 struct vc4_hdmi *vc4_hdmi = priv; 2409 irqreturn_t ret; 2410 2411 if (vc4_hdmi->cec_irq_was_rx) 2412 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2413 else 2414 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2415 2416 return ret; 2417 } 2418 2419 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2420 { 2421 struct drm_device *dev = vc4_hdmi->connector.dev; 2422 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2423 unsigned int i; 2424 2425 lockdep_assert_held(&vc4_hdmi->hw_lock); 2426 2427 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2428 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2429 2430 if (msg->len > 16) { 2431 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2432 return; 2433 } 2434 2435 for (i = 0; i < msg->len; i += 4) { 2436 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2437 2438 msg->msg[i] = val & 0xff; 2439 msg->msg[i + 1] = (val >> 8) & 0xff; 2440 msg->msg[i + 2] = (val >> 16) & 0xff; 2441 msg->msg[i + 3] = (val >> 24) & 0xff; 2442 } 2443 } 2444 2445 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2446 { 2447 u32 cntrl1; 2448 2449 /* 2450 * We don't need to protect the register access using 2451 * drm_dev_enter() there because the interrupt handler lifetime 2452 * is tied to the device itself, and not to the DRM device. 2453 * 2454 * So when the device will be gone, one of the first thing we 2455 * will be doing will be to unregister the interrupt handler, 2456 * and then unregister the DRM device. drm_dev_enter() would 2457 * thus always succeed if we are here. 2458 */ 2459 2460 lockdep_assert_held(&vc4_hdmi->hw_lock); 2461 2462 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2463 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2464 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2465 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2466 2467 return IRQ_WAKE_THREAD; 2468 } 2469 2470 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2471 { 2472 struct vc4_hdmi *vc4_hdmi = priv; 2473 irqreturn_t ret; 2474 2475 spin_lock(&vc4_hdmi->hw_lock); 2476 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2477 spin_unlock(&vc4_hdmi->hw_lock); 2478 2479 return ret; 2480 } 2481 2482 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2483 { 2484 u32 cntrl1; 2485 2486 lockdep_assert_held(&vc4_hdmi->hw_lock); 2487 2488 /* 2489 * We don't need to protect the register access using 2490 * drm_dev_enter() there because the interrupt handler lifetime 2491 * is tied to the device itself, and not to the DRM device. 2492 * 2493 * So when the device will be gone, one of the first thing we 2494 * will be doing will be to unregister the interrupt handler, 2495 * and then unregister the DRM device. drm_dev_enter() would 2496 * thus always succeed if we are here. 2497 */ 2498 2499 vc4_hdmi->cec_rx_msg.len = 0; 2500 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2501 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2502 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2503 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2504 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2505 2506 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2507 2508 return IRQ_WAKE_THREAD; 2509 } 2510 2511 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2512 { 2513 struct vc4_hdmi *vc4_hdmi = priv; 2514 irqreturn_t ret; 2515 2516 spin_lock(&vc4_hdmi->hw_lock); 2517 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2518 spin_unlock(&vc4_hdmi->hw_lock); 2519 2520 return ret; 2521 } 2522 2523 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2524 { 2525 struct vc4_hdmi *vc4_hdmi = priv; 2526 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2527 irqreturn_t ret; 2528 u32 cntrl5; 2529 2530 /* 2531 * We don't need to protect the register access using 2532 * drm_dev_enter() there because the interrupt handler lifetime 2533 * is tied to the device itself, and not to the DRM device. 2534 * 2535 * So when the device will be gone, one of the first thing we 2536 * will be doing will be to unregister the interrupt handler, 2537 * and then unregister the DRM device. drm_dev_enter() would 2538 * thus always succeed if we are here. 2539 */ 2540 2541 if (!(stat & VC4_HDMI_CPU_CEC)) 2542 return IRQ_NONE; 2543 2544 spin_lock(&vc4_hdmi->hw_lock); 2545 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2546 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2547 if (vc4_hdmi->cec_irq_was_rx) 2548 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2549 else 2550 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2551 2552 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2553 spin_unlock(&vc4_hdmi->hw_lock); 2554 2555 return ret; 2556 } 2557 2558 static int vc4_hdmi_cec_enable(struct drm_connector *connector) 2559 { 2560 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2561 struct drm_device *drm = vc4_hdmi->connector.dev; 2562 /* clock period in microseconds */ 2563 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2564 unsigned long flags; 2565 u32 val; 2566 int ret; 2567 int idx; 2568 2569 if (!drm_dev_enter(drm, &idx)) 2570 /* 2571 * We can't return an error code, because the CEC 2572 * framework will emit WARN_ON messages at unbind 2573 * otherwise. 2574 */ 2575 return 0; 2576 2577 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2578 if (ret) { 2579 drm_dev_exit(idx); 2580 return ret; 2581 } 2582 2583 mutex_lock(&vc4_hdmi->mutex); 2584 2585 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2586 2587 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2588 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2589 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2590 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2591 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2592 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2593 2594 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2595 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2596 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2597 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2598 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2599 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2600 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2601 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2602 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2603 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2604 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2605 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2606 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2607 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2608 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2609 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2610 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2611 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2612 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2613 2614 if (!vc4_hdmi->variant->external_irq_controller) 2615 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2616 2617 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2618 2619 mutex_unlock(&vc4_hdmi->mutex); 2620 drm_dev_exit(idx); 2621 2622 return 0; 2623 } 2624 2625 static int vc4_hdmi_cec_disable(struct drm_connector *connector) 2626 { 2627 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2628 struct drm_device *drm = vc4_hdmi->connector.dev; 2629 unsigned long flags; 2630 int idx; 2631 2632 if (!drm_dev_enter(drm, &idx)) 2633 /* 2634 * We can't return an error code, because the CEC 2635 * framework will emit WARN_ON messages at unbind 2636 * otherwise. 2637 */ 2638 return 0; 2639 2640 mutex_lock(&vc4_hdmi->mutex); 2641 2642 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2643 2644 if (!vc4_hdmi->variant->external_irq_controller) 2645 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2646 2647 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2648 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2649 2650 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2651 2652 mutex_unlock(&vc4_hdmi->mutex); 2653 2654 pm_runtime_put(&vc4_hdmi->pdev->dev); 2655 2656 drm_dev_exit(idx); 2657 2658 return 0; 2659 } 2660 2661 static int vc4_hdmi_cec_adap_enable(struct drm_connector *connector, bool enable) 2662 { 2663 if (enable) 2664 return vc4_hdmi_cec_enable(connector); 2665 else 2666 return vc4_hdmi_cec_disable(connector); 2667 } 2668 2669 static int vc4_hdmi_cec_adap_log_addr(struct drm_connector *connector, u8 log_addr) 2670 { 2671 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2672 struct drm_device *drm = vc4_hdmi->connector.dev; 2673 unsigned long flags; 2674 int idx; 2675 2676 if (!drm_dev_enter(drm, &idx)) 2677 /* 2678 * We can't return an error code, because the CEC 2679 * framework will emit WARN_ON messages at unbind 2680 * otherwise. 2681 */ 2682 return 0; 2683 2684 mutex_lock(&vc4_hdmi->mutex); 2685 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2686 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2687 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2688 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2689 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2690 mutex_unlock(&vc4_hdmi->mutex); 2691 2692 drm_dev_exit(idx); 2693 2694 return 0; 2695 } 2696 2697 static int vc4_hdmi_cec_adap_transmit(struct drm_connector *connector, u8 attempts, 2698 u32 signal_free_time, struct cec_msg *msg) 2699 { 2700 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2701 struct drm_device *dev = vc4_hdmi->connector.dev; 2702 unsigned long flags; 2703 u32 val; 2704 unsigned int i; 2705 int idx; 2706 2707 if (!drm_dev_enter(dev, &idx)) 2708 return -ENODEV; 2709 2710 if (msg->len > 16) { 2711 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2712 drm_dev_exit(idx); 2713 return -ENOMEM; 2714 } 2715 2716 mutex_lock(&vc4_hdmi->mutex); 2717 2718 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2719 2720 for (i = 0; i < msg->len; i += 4) 2721 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2722 (msg->msg[i]) | 2723 (msg->msg[i + 1] << 8) | 2724 (msg->msg[i + 2] << 16) | 2725 (msg->msg[i + 3] << 24)); 2726 2727 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2728 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2729 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2730 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2731 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2732 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2733 2734 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2735 2736 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2737 mutex_unlock(&vc4_hdmi->mutex); 2738 drm_dev_exit(idx); 2739 2740 return 0; 2741 } 2742 2743 static int vc4_hdmi_cec_init(struct drm_connector *connector) 2744 { 2745 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2746 struct platform_device *pdev = vc4_hdmi->pdev; 2747 struct device *dev = &pdev->dev; 2748 int ret; 2749 2750 if (vc4_hdmi->variant->external_irq_controller) { 2751 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 2752 vc4_cec_irq_handler_rx_bare, 2753 vc4_cec_irq_handler_rx_thread, 0, 2754 "vc4 hdmi cec rx", vc4_hdmi); 2755 if (ret) 2756 return ret; 2757 2758 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 2759 vc4_cec_irq_handler_tx_bare, 2760 vc4_cec_irq_handler_tx_thread, 0, 2761 "vc4 hdmi cec tx", vc4_hdmi); 2762 if (ret) 2763 return ret; 2764 } else { 2765 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 2766 vc4_cec_irq_handler, 2767 vc4_cec_irq_handler_thread, 0, 2768 "vc4 hdmi cec", vc4_hdmi); 2769 if (ret) 2770 return ret; 2771 } 2772 2773 return 0; 2774 } 2775 2776 static const struct drm_connector_hdmi_cec_funcs vc4_hdmi_cec_funcs = { 2777 .init = vc4_hdmi_cec_init, 2778 .enable = vc4_hdmi_cec_adap_enable, 2779 .log_addr = vc4_hdmi_cec_adap_log_addr, 2780 .transmit = vc4_hdmi_cec_adap_transmit, 2781 }; 2782 2783 static int vc4_hdmi_cec_register(struct vc4_hdmi *vc4_hdmi) 2784 { 2785 struct platform_device *pdev = vc4_hdmi->pdev; 2786 struct device *dev = &pdev->dev; 2787 2788 if (!of_property_present(dev->of_node, "interrupts")) { 2789 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2790 return 0; 2791 } 2792 2793 /* 2794 * NOTE: the CEC adapter will be unregistered by drmm cleanup from 2795 * drm_managed_release(), which is called from drm_dev_release() 2796 * during device unbind. 2797 * 2798 * However, the CEC framework already cleans up the CEC adapter 2799 * only when the last user has closed its file descriptor, so we 2800 * don't need to handle it in DRM. 2801 * 2802 * There's still a problematic sequence: if we unregister our 2803 * CEC adapter, but the userspace keeps a handle on the CEC 2804 * adapter but not the DRM device for some reason. In such a 2805 * case, our vc4_hdmi structure will be freed, but the 2806 * cec_adapter structure will have a dangling pointer to what 2807 * used to be our HDMI controller. If we get a CEC call at that 2808 * moment, we could end up with a use-after-free. Fortunately, 2809 * the CEC framework already handles this too, by calling 2810 * cec_is_registered() in cec_ioctl() and cec_poll(). 2811 */ 2812 return drmm_connector_hdmi_cec_register(&vc4_hdmi->connector, 2813 &vc4_hdmi_cec_funcs, 2814 vc4_hdmi->variant->card_name, 2815 1, 2816 &pdev->dev); 2817 } 2818 #else 2819 static int vc4_hdmi_cec_register(struct vc4_hdmi *vc4_hdmi) 2820 { 2821 return 0; 2822 } 2823 #endif 2824 2825 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 2826 { 2827 struct debugfs_reg32 *regs = ptr; 2828 2829 kfree(regs); 2830 } 2831 2832 static int vc4_hdmi_build_regset(struct drm_device *drm, 2833 struct vc4_hdmi *vc4_hdmi, 2834 struct debugfs_regset32 *regset, 2835 enum vc4_hdmi_regs reg) 2836 { 2837 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2838 struct debugfs_reg32 *regs, *new_regs; 2839 unsigned int count = 0; 2840 unsigned int i; 2841 int ret; 2842 2843 regs = kcalloc(variant->num_registers, sizeof(*regs), 2844 GFP_KERNEL); 2845 if (!regs) 2846 return -ENOMEM; 2847 2848 for (i = 0; i < variant->num_registers; i++) { 2849 const struct vc4_hdmi_register *field = &variant->registers[i]; 2850 2851 if (field->reg != reg) 2852 continue; 2853 2854 regs[count].name = field->name; 2855 regs[count].offset = field->offset; 2856 count++; 2857 } 2858 2859 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2860 if (!new_regs) 2861 return -ENOMEM; 2862 2863 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2864 regset->regs = new_regs; 2865 regset->nregs = count; 2866 2867 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 2868 if (ret) 2869 return ret; 2870 2871 return 0; 2872 } 2873 2874 static int vc4_hdmi_init_resources(struct drm_device *drm, 2875 struct vc4_hdmi *vc4_hdmi) 2876 { 2877 struct platform_device *pdev = vc4_hdmi->pdev; 2878 struct device *dev = &pdev->dev; 2879 int ret; 2880 2881 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2882 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2883 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2884 2885 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2886 if (IS_ERR(vc4_hdmi->hd_regs)) 2887 return PTR_ERR(vc4_hdmi->hd_regs); 2888 2889 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2890 if (ret) 2891 return ret; 2892 2893 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2894 if (ret) 2895 return ret; 2896 2897 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2898 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2899 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2900 if (ret != -EPROBE_DEFER) 2901 drm_err(drm, "Failed to get pixel clock\n"); 2902 return ret; 2903 } 2904 2905 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2906 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2907 drm_err(drm, "Failed to get HDMI state machine clock\n"); 2908 return PTR_ERR(vc4_hdmi->hsm_clock); 2909 } 2910 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2911 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2912 2913 return 0; 2914 } 2915 2916 static int vc5_hdmi_init_resources(struct drm_device *drm, 2917 struct vc4_hdmi *vc4_hdmi) 2918 { 2919 struct platform_device *pdev = vc4_hdmi->pdev; 2920 struct device *dev = &pdev->dev; 2921 struct resource *res; 2922 int ret; 2923 2924 vc4_hdmi->hdmicore_regs = devm_platform_ioremap_resource_byname(pdev, 2925 "hdmi"); 2926 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2927 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2928 2929 /* This is shared between both HDMI controllers. Cannot 2930 * claim for both instances. Lets not convert to using 2931 * devm_platform_ioremap_resource_byname() like 2932 * the rest 2933 */ 2934 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2935 if (!res) 2936 return -ENODEV; 2937 2938 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2939 if (!vc4_hdmi->hd_regs) 2940 return -ENOMEM; 2941 2942 vc4_hdmi->cec_regs = devm_platform_ioremap_resource_byname(pdev, 2943 "cec"); 2944 if (IS_ERR(vc4_hdmi->cec_regs)) 2945 return PTR_ERR(vc4_hdmi->cec_regs); 2946 2947 vc4_hdmi->csc_regs = devm_platform_ioremap_resource_byname(pdev, 2948 "csc"); 2949 if (IS_ERR(vc4_hdmi->csc_regs)) 2950 return PTR_ERR(vc4_hdmi->csc_regs); 2951 2952 vc4_hdmi->dvp_regs = devm_platform_ioremap_resource_byname(pdev, 2953 "dvp"); 2954 if (IS_ERR(vc4_hdmi->dvp_regs)) 2955 return PTR_ERR(vc4_hdmi->dvp_regs); 2956 2957 vc4_hdmi->phy_regs = devm_platform_ioremap_resource_byname(pdev, 2958 "phy"); 2959 2960 if (IS_ERR(vc4_hdmi->phy_regs)) 2961 return PTR_ERR(vc4_hdmi->phy_regs); 2962 2963 vc4_hdmi->ram_regs = devm_platform_ioremap_resource_byname(pdev, 2964 "packet"); 2965 if (IS_ERR(vc4_hdmi->ram_regs)) 2966 return PTR_ERR(vc4_hdmi->ram_regs); 2967 2968 vc4_hdmi->rm_regs = devm_platform_ioremap_resource_byname(pdev, "rm"); 2969 if (IS_ERR(vc4_hdmi->rm_regs)) 2970 return PTR_ERR(vc4_hdmi->rm_regs); 2971 2972 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2973 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2974 drm_err(drm, "Failed to get HDMI state machine clock\n"); 2975 return PTR_ERR(vc4_hdmi->hsm_clock); 2976 } 2977 2978 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2979 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2980 drm_err(drm, "Failed to get pixel bvb clock\n"); 2981 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2982 } 2983 2984 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2985 if (IS_ERR(vc4_hdmi->audio_clock)) { 2986 drm_err(drm, "Failed to get audio clock\n"); 2987 return PTR_ERR(vc4_hdmi->audio_clock); 2988 } 2989 2990 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2991 if (IS_ERR(vc4_hdmi->cec_clock)) { 2992 drm_err(drm, "Failed to get CEC clock\n"); 2993 return PTR_ERR(vc4_hdmi->cec_clock); 2994 } 2995 2996 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2997 if (IS_ERR(vc4_hdmi->reset)) { 2998 drm_err(drm, "Failed to get HDMI reset line\n"); 2999 return PTR_ERR(vc4_hdmi->reset); 3000 } 3001 3002 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3003 if (ret) 3004 return ret; 3005 3006 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3007 if (ret) 3008 return ret; 3009 3010 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3011 if (ret) 3012 return ret; 3013 3014 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3015 if (ret) 3016 return ret; 3017 3018 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3019 if (ret) 3020 return ret; 3021 3022 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3023 if (ret) 3024 return ret; 3025 3026 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3027 if (ret) 3028 return ret; 3029 3030 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3031 if (ret) 3032 return ret; 3033 3034 return 0; 3035 } 3036 3037 static int vc4_hdmi_runtime_suspend(struct device *dev) 3038 { 3039 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3040 3041 clk_disable_unprepare(vc4_hdmi->audio_clock); 3042 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3043 3044 return 0; 3045 } 3046 3047 static int vc4_hdmi_runtime_resume(struct device *dev) 3048 { 3049 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3050 unsigned long __maybe_unused flags; 3051 u32 __maybe_unused value; 3052 unsigned long rate; 3053 int ret; 3054 3055 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3056 if (ret) 3057 return ret; 3058 3059 /* 3060 * Whenever the RaspberryPi boots without an HDMI monitor 3061 * plugged in, the firmware won't have initialized the HSM clock 3062 * rate and it will be reported as 0. 3063 * 3064 * If we try to access a register of the controller in such a 3065 * case, it will lead to a silent CPU stall. Let's make sure we 3066 * prevent such a case. 3067 */ 3068 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3069 if (!rate) { 3070 ret = -EINVAL; 3071 goto err_disable_clk; 3072 } 3073 3074 ret = clk_prepare_enable(vc4_hdmi->audio_clock); 3075 if (ret) 3076 goto err_disable_clk; 3077 3078 if (vc4_hdmi->variant->reset) 3079 vc4_hdmi->variant->reset(vc4_hdmi); 3080 3081 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3082 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3083 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3084 /* Set the logical address to Unregistered */ 3085 value |= VC4_HDMI_CEC_ADDR_MASK; 3086 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3087 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3088 3089 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3090 3091 if (!vc4_hdmi->variant->external_irq_controller) { 3092 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3093 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3094 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3095 } 3096 #endif 3097 3098 return 0; 3099 3100 err_disable_clk: 3101 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3102 return ret; 3103 } 3104 3105 static void vc4_hdmi_put_ddc_device(void *ptr) 3106 { 3107 struct vc4_hdmi *vc4_hdmi = ptr; 3108 3109 put_device(&vc4_hdmi->ddc->dev); 3110 } 3111 3112 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3113 { 3114 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3115 struct platform_device *pdev = to_platform_device(dev); 3116 struct drm_device *drm = dev_get_drvdata(master); 3117 struct vc4_hdmi *vc4_hdmi; 3118 struct drm_encoder *encoder; 3119 struct device_node *ddc_node; 3120 int ret; 3121 3122 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3123 if (!vc4_hdmi) 3124 return -ENOMEM; 3125 3126 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3127 if (ret) 3128 return ret; 3129 3130 spin_lock_init(&vc4_hdmi->hw_lock); 3131 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3132 3133 dev_set_drvdata(dev, vc4_hdmi); 3134 encoder = &vc4_hdmi->encoder.base; 3135 vc4_hdmi->encoder.type = variant->encoder_type; 3136 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3137 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3138 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3139 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3140 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3141 vc4_hdmi->pdev = pdev; 3142 vc4_hdmi->variant = variant; 3143 3144 /* 3145 * Since we don't know the state of the controller and its 3146 * display (if any), let's assume it's always enabled. 3147 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3148 * sure it's disabled, and avoid any inconsistency. 3149 */ 3150 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3151 vc4_hdmi->scdc_enabled = true; 3152 3153 ret = variant->init_resources(drm, vc4_hdmi); 3154 if (ret) 3155 return ret; 3156 3157 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3158 if (!ddc_node) { 3159 drm_err(drm, "Failed to find ddc node in device tree\n"); 3160 return -ENODEV; 3161 } 3162 3163 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3164 of_node_put(ddc_node); 3165 if (!vc4_hdmi->ddc) { 3166 drm_err(drm, "Failed to get ddc i2c adapter by node\n"); 3167 return -EPROBE_DEFER; 3168 } 3169 3170 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3171 if (ret) 3172 return ret; 3173 3174 /* Only use the GPIO HPD pin if present in the DT, otherwise 3175 * we'll use the HDMI core's register. 3176 */ 3177 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3178 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3179 return PTR_ERR(vc4_hdmi->hpd_gpio); 3180 } 3181 3182 vc4_hdmi->disable_wifi_frequencies = 3183 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3184 3185 ret = devm_pm_runtime_enable(dev); 3186 if (ret) 3187 return ret; 3188 3189 /* 3190 * We need to have the device powered up at this point to call 3191 * our reset hook and for the CEC init. 3192 */ 3193 ret = pm_runtime_resume_and_get(dev); 3194 if (ret) 3195 return ret; 3196 3197 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3198 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") || 3199 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") || 3200 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) && 3201 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3202 clk_prepare_enable(vc4_hdmi->pixel_clock); 3203 clk_prepare_enable(vc4_hdmi->hsm_clock); 3204 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3205 } 3206 3207 ret = drmm_encoder_init(drm, encoder, 3208 &vc4_hdmi_encoder_funcs, 3209 DRM_MODE_ENCODER_TMDS, 3210 NULL); 3211 if (ret) 3212 goto err_put_runtime_pm; 3213 3214 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3215 3216 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3217 if (ret) 3218 goto err_put_runtime_pm; 3219 3220 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3221 if (ret) 3222 goto err_put_runtime_pm; 3223 3224 ret = vc4_hdmi_cec_register(vc4_hdmi); 3225 if (ret) 3226 goto err_put_runtime_pm; 3227 3228 ret = vc4_hdmi_audio_init(vc4_hdmi); 3229 if (ret) 3230 goto err_put_runtime_pm; 3231 3232 pm_runtime_put_sync(dev); 3233 3234 return 0; 3235 3236 err_put_runtime_pm: 3237 pm_runtime_put_sync(dev); 3238 3239 return ret; 3240 } 3241 3242 static const struct component_ops vc4_hdmi_ops = { 3243 .bind = vc4_hdmi_bind, 3244 }; 3245 3246 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3247 { 3248 return component_add(&pdev->dev, &vc4_hdmi_ops); 3249 } 3250 3251 static void vc4_hdmi_dev_remove(struct platform_device *pdev) 3252 { 3253 component_del(&pdev->dev, &vc4_hdmi_ops); 3254 } 3255 3256 static const struct vc4_hdmi_variant bcm2835_variant = { 3257 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3258 .debugfs_name = "hdmi_regs", 3259 .card_name = "vc4-hdmi", 3260 .max_pixel_clock = 162000000, 3261 .registers = vc4_hdmi_fields, 3262 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3263 3264 .init_resources = vc4_hdmi_init_resources, 3265 .csc_setup = vc4_hdmi_csc_setup, 3266 .reset = vc4_hdmi_reset, 3267 .set_timings = vc4_hdmi_set_timings, 3268 .phy_init = vc4_hdmi_phy_init, 3269 .phy_disable = vc4_hdmi_phy_disable, 3270 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3271 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3272 .channel_map = vc4_hdmi_channel_map, 3273 .supports_hdr = false, 3274 }; 3275 3276 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3277 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3278 .debugfs_name = "hdmi0_regs", 3279 .card_name = "vc4-hdmi-0", 3280 .max_pixel_clock = 600000000, 3281 .registers = vc5_hdmi_hdmi0_fields, 3282 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3283 .phy_lane_mapping = { 3284 PHY_LANE_0, 3285 PHY_LANE_1, 3286 PHY_LANE_2, 3287 PHY_LANE_CK, 3288 }, 3289 .unsupported_odd_h_timings = true, 3290 .external_irq_controller = true, 3291 3292 .init_resources = vc5_hdmi_init_resources, 3293 .csc_setup = vc5_hdmi_csc_setup, 3294 .reset = vc5_hdmi_reset, 3295 .set_timings = vc5_hdmi_set_timings, 3296 .phy_init = vc5_hdmi_phy_init, 3297 .phy_disable = vc5_hdmi_phy_disable, 3298 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3299 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3300 .channel_map = vc5_hdmi_channel_map, 3301 .supports_hdr = true, 3302 .hp_detect = vc5_hdmi_hp_detect, 3303 }; 3304 3305 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3306 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3307 .debugfs_name = "hdmi1_regs", 3308 .card_name = "vc4-hdmi-1", 3309 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3310 .registers = vc5_hdmi_hdmi1_fields, 3311 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3312 .phy_lane_mapping = { 3313 PHY_LANE_1, 3314 PHY_LANE_0, 3315 PHY_LANE_CK, 3316 PHY_LANE_2, 3317 }, 3318 .unsupported_odd_h_timings = true, 3319 .external_irq_controller = true, 3320 3321 .init_resources = vc5_hdmi_init_resources, 3322 .csc_setup = vc5_hdmi_csc_setup, 3323 .reset = vc5_hdmi_reset, 3324 .set_timings = vc5_hdmi_set_timings, 3325 .phy_init = vc5_hdmi_phy_init, 3326 .phy_disable = vc5_hdmi_phy_disable, 3327 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3328 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3329 .channel_map = vc5_hdmi_channel_map, 3330 .supports_hdr = true, 3331 .hp_detect = vc5_hdmi_hp_detect, 3332 }; 3333 3334 static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = { 3335 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3336 .debugfs_name = "hdmi0_regs", 3337 .card_name = "vc4-hdmi-0", 3338 .max_pixel_clock = 600000000, 3339 .registers = vc6_hdmi_hdmi0_fields, 3340 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi0_fields), 3341 .phy_lane_mapping = { 3342 PHY_LANE_0, 3343 PHY_LANE_1, 3344 PHY_LANE_2, 3345 PHY_LANE_CK, 3346 }, 3347 .unsupported_odd_h_timings = false, 3348 .external_irq_controller = true, 3349 3350 .init_resources = vc5_hdmi_init_resources, 3351 .csc_setup = vc5_hdmi_csc_setup, 3352 .reset = vc5_hdmi_reset, 3353 .set_timings = vc5_hdmi_set_timings, 3354 .phy_init = vc6_hdmi_phy_init, 3355 .phy_disable = vc6_hdmi_phy_disable, 3356 .channel_map = vc5_hdmi_channel_map, 3357 .supports_hdr = true, 3358 .hp_detect = vc5_hdmi_hp_detect, 3359 }; 3360 3361 static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = { 3362 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3363 .debugfs_name = "hdmi1_regs", 3364 .card_name = "vc4-hdmi-1", 3365 .max_pixel_clock = 600000000, 3366 .registers = vc6_hdmi_hdmi1_fields, 3367 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi1_fields), 3368 .phy_lane_mapping = { 3369 PHY_LANE_0, 3370 PHY_LANE_1, 3371 PHY_LANE_2, 3372 PHY_LANE_CK, 3373 }, 3374 .unsupported_odd_h_timings = false, 3375 .external_irq_controller = true, 3376 3377 .init_resources = vc5_hdmi_init_resources, 3378 .csc_setup = vc5_hdmi_csc_setup, 3379 .reset = vc5_hdmi_reset, 3380 .set_timings = vc5_hdmi_set_timings, 3381 .phy_init = vc6_hdmi_phy_init, 3382 .phy_disable = vc6_hdmi_phy_disable, 3383 .channel_map = vc5_hdmi_channel_map, 3384 .supports_hdr = true, 3385 .hp_detect = vc5_hdmi_hp_detect, 3386 }; 3387 3388 static const struct of_device_id vc4_hdmi_dt_match[] = { 3389 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3390 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3391 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3392 { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant }, 3393 { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant }, 3394 {} 3395 }; 3396 3397 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3398 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3399 vc4_hdmi_runtime_resume, 3400 NULL) 3401 }; 3402 3403 struct platform_driver vc4_hdmi_driver = { 3404 .probe = vc4_hdmi_dev_probe, 3405 .remove = vc4_hdmi_dev_remove, 3406 .driver = { 3407 .name = "vc4_hdmi", 3408 .of_match_table = vc4_hdmi_dt_match, 3409 .pm = &vc4_hdmi_pm_ops, 3410 }, 3411 }; 3412