xref: /linux/drivers/gpu/drm/vc4/vc4_hdmi.c (revision d6869352cb3c3cf3450637a52349e2e87c1354aa)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2015 Broadcom
4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5  * Copyright (C) 2013 Red Hat
6  * Author: Rob Clark <robdclark@gmail.com>
7  */
8 
9 /**
10  * DOC: VC4 Falcon HDMI module
11  *
12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
13  * the unit operates off of the HSM clock from CPRMAN.  It also
14  * internally uses the PLLH_PIX clock for the PHY.
15  *
16  * HDMI infoframes are kept within a small packet ram, where each
17  * packet can be individually enabled for including in a frame.
18  *
19  * HDMI audio is implemented entirely within the HDMI IP block.  A
20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
21  * and transfers them over an internal MAI (multi-channel audio
22  * interconnect) bus to the encoder side for insertion into the video
23  * blank regions.
24  *
25  * The driver's HDMI encoder does not yet support power management.
26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27  * continuously running, and only the HDMI logic and packet ram are
28  * powered off/on at disable/enable time.
29  *
30  * The driver does not yet support CEC control, though the HDMI
31  * encoder block has CEC support.
32  */
33 
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <linux/clk.h>
38 #include <linux/component.h>
39 #include <linux/i2c.h>
40 #include <linux/of_address.h>
41 #include <linux/of_gpio.h>
42 #include <linux/of_platform.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/rational.h>
45 #include <sound/dmaengine_pcm.h>
46 #include <sound/pcm_drm_eld.h>
47 #include <sound/pcm_params.h>
48 #include <sound/soc.h>
49 #include "media/cec.h"
50 #include "vc4_drv.h"
51 #include "vc4_regs.h"
52 
53 #define HSM_CLOCK_FREQ 163682864
54 #define CEC_CLOCK_FREQ 40000
55 #define CEC_CLOCK_DIV  (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
56 
57 /* HDMI audio information */
58 struct vc4_hdmi_audio {
59 	struct snd_soc_card card;
60 	struct snd_soc_dai_link link;
61 	int samplerate;
62 	int channels;
63 	struct snd_dmaengine_dai_dma_data dma_data;
64 	struct snd_pcm_substream *substream;
65 };
66 
67 /* General HDMI hardware state. */
68 struct vc4_hdmi {
69 	struct platform_device *pdev;
70 
71 	struct drm_encoder *encoder;
72 	struct drm_connector *connector;
73 
74 	struct vc4_hdmi_audio audio;
75 
76 	struct i2c_adapter *ddc;
77 	void __iomem *hdmicore_regs;
78 	void __iomem *hd_regs;
79 	int hpd_gpio;
80 	bool hpd_active_low;
81 
82 	struct cec_adapter *cec_adap;
83 	struct cec_msg cec_rx_msg;
84 	bool cec_tx_ok;
85 	bool cec_irq_was_rx;
86 
87 	struct clk *pixel_clock;
88 	struct clk *hsm_clock;
89 
90 	struct debugfs_regset32 hdmi_regset;
91 	struct debugfs_regset32 hd_regset;
92 };
93 
94 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
95 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
96 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
97 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
98 
99 /* VC4 HDMI encoder KMS struct */
100 struct vc4_hdmi_encoder {
101 	struct vc4_encoder base;
102 	bool hdmi_monitor;
103 	bool limited_rgb_range;
104 };
105 
106 static inline struct vc4_hdmi_encoder *
107 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
108 {
109 	return container_of(encoder, struct vc4_hdmi_encoder, base.base);
110 }
111 
112 /* VC4 HDMI connector KMS struct */
113 struct vc4_hdmi_connector {
114 	struct drm_connector base;
115 
116 	/* Since the connector is attached to just the one encoder,
117 	 * this is the reference to it so we can do the best_encoder()
118 	 * hook.
119 	 */
120 	struct drm_encoder *encoder;
121 };
122 
123 static inline struct vc4_hdmi_connector *
124 to_vc4_hdmi_connector(struct drm_connector *connector)
125 {
126 	return container_of(connector, struct vc4_hdmi_connector, base);
127 }
128 
129 static const struct debugfs_reg32 hdmi_regs[] = {
130 	VC4_REG32(VC4_HDMI_CORE_REV),
131 	VC4_REG32(VC4_HDMI_SW_RESET_CONTROL),
132 	VC4_REG32(VC4_HDMI_HOTPLUG_INT),
133 	VC4_REG32(VC4_HDMI_HOTPLUG),
134 	VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP),
135 	VC4_REG32(VC4_HDMI_MAI_CONFIG),
136 	VC4_REG32(VC4_HDMI_MAI_FORMAT),
137 	VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG),
138 	VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG),
139 	VC4_REG32(VC4_HDMI_HORZA),
140 	VC4_REG32(VC4_HDMI_HORZB),
141 	VC4_REG32(VC4_HDMI_FIFO_CTL),
142 	VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL),
143 	VC4_REG32(VC4_HDMI_VERTA0),
144 	VC4_REG32(VC4_HDMI_VERTA1),
145 	VC4_REG32(VC4_HDMI_VERTB0),
146 	VC4_REG32(VC4_HDMI_VERTB1),
147 	VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL),
148 	VC4_REG32(VC4_HDMI_TX_PHY_CTL0),
149 
150 	VC4_REG32(VC4_HDMI_CEC_CNTRL_1),
151 	VC4_REG32(VC4_HDMI_CEC_CNTRL_2),
152 	VC4_REG32(VC4_HDMI_CEC_CNTRL_3),
153 	VC4_REG32(VC4_HDMI_CEC_CNTRL_4),
154 	VC4_REG32(VC4_HDMI_CEC_CNTRL_5),
155 	VC4_REG32(VC4_HDMI_CPU_STATUS),
156 	VC4_REG32(VC4_HDMI_CPU_MASK_STATUS),
157 
158 	VC4_REG32(VC4_HDMI_CEC_RX_DATA_1),
159 	VC4_REG32(VC4_HDMI_CEC_RX_DATA_2),
160 	VC4_REG32(VC4_HDMI_CEC_RX_DATA_3),
161 	VC4_REG32(VC4_HDMI_CEC_RX_DATA_4),
162 	VC4_REG32(VC4_HDMI_CEC_TX_DATA_1),
163 	VC4_REG32(VC4_HDMI_CEC_TX_DATA_2),
164 	VC4_REG32(VC4_HDMI_CEC_TX_DATA_3),
165 	VC4_REG32(VC4_HDMI_CEC_TX_DATA_4),
166 };
167 
168 static const struct debugfs_reg32 hd_regs[] = {
169 	VC4_REG32(VC4_HD_M_CTL),
170 	VC4_REG32(VC4_HD_MAI_CTL),
171 	VC4_REG32(VC4_HD_MAI_THR),
172 	VC4_REG32(VC4_HD_MAI_FMT),
173 	VC4_REG32(VC4_HD_MAI_SMP),
174 	VC4_REG32(VC4_HD_VID_CTL),
175 	VC4_REG32(VC4_HD_CSC_CTL),
176 	VC4_REG32(VC4_HD_FRAME_COUNT),
177 };
178 
179 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
180 {
181 	struct drm_info_node *node = (struct drm_info_node *)m->private;
182 	struct drm_device *dev = node->minor->dev;
183 	struct vc4_dev *vc4 = to_vc4_dev(dev);
184 	struct vc4_hdmi *hdmi = vc4->hdmi;
185 	struct drm_printer p = drm_seq_file_printer(m);
186 
187 	drm_print_regset32(&p, &hdmi->hdmi_regset);
188 	drm_print_regset32(&p, &hdmi->hd_regset);
189 
190 	return 0;
191 }
192 
193 static enum drm_connector_status
194 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
195 {
196 	struct drm_device *dev = connector->dev;
197 	struct vc4_dev *vc4 = to_vc4_dev(dev);
198 
199 	if (vc4->hdmi->hpd_gpio) {
200 		if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
201 		    vc4->hdmi->hpd_active_low)
202 			return connector_status_connected;
203 		cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
204 		return connector_status_disconnected;
205 	}
206 
207 	if (drm_probe_ddc(vc4->hdmi->ddc))
208 		return connector_status_connected;
209 
210 	if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
211 		return connector_status_connected;
212 	cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
213 	return connector_status_disconnected;
214 }
215 
216 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
217 {
218 	drm_connector_unregister(connector);
219 	drm_connector_cleanup(connector);
220 }
221 
222 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
223 {
224 	struct vc4_hdmi_connector *vc4_connector =
225 		to_vc4_hdmi_connector(connector);
226 	struct drm_encoder *encoder = vc4_connector->encoder;
227 	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
228 	struct drm_device *dev = connector->dev;
229 	struct vc4_dev *vc4 = to_vc4_dev(dev);
230 	int ret = 0;
231 	struct edid *edid;
232 
233 	edid = drm_get_edid(connector, vc4->hdmi->ddc);
234 	cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
235 	if (!edid)
236 		return -ENODEV;
237 
238 	vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
239 
240 	drm_connector_update_edid_property(connector, edid);
241 	ret = drm_add_edid_modes(connector, edid);
242 	kfree(edid);
243 
244 	return ret;
245 }
246 
247 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
248 	.detect = vc4_hdmi_connector_detect,
249 	.fill_modes = drm_helper_probe_single_connector_modes,
250 	.destroy = vc4_hdmi_connector_destroy,
251 	.reset = drm_atomic_helper_connector_reset,
252 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
253 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
254 };
255 
256 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
257 	.get_modes = vc4_hdmi_connector_get_modes,
258 };
259 
260 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
261 						     struct drm_encoder *encoder)
262 {
263 	struct drm_connector *connector;
264 	struct vc4_hdmi_connector *hdmi_connector;
265 	int ret;
266 
267 	hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
268 				      GFP_KERNEL);
269 	if (!hdmi_connector)
270 		return ERR_PTR(-ENOMEM);
271 	connector = &hdmi_connector->base;
272 
273 	hdmi_connector->encoder = encoder;
274 
275 	drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
276 			   DRM_MODE_CONNECTOR_HDMIA);
277 	drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
278 
279 	/* Create and attach TV margin props to this connector. */
280 	ret = drm_mode_create_tv_margin_properties(dev);
281 	if (ret)
282 		return ERR_PTR(ret);
283 
284 	drm_connector_attach_tv_margin_properties(connector);
285 
286 	connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
287 			     DRM_CONNECTOR_POLL_DISCONNECT);
288 
289 	connector->interlace_allowed = 1;
290 	connector->doublescan_allowed = 0;
291 
292 	drm_connector_attach_encoder(connector, encoder);
293 
294 	return connector;
295 }
296 
297 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
298 {
299 	drm_encoder_cleanup(encoder);
300 }
301 
302 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
303 	.destroy = vc4_hdmi_encoder_destroy,
304 };
305 
306 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
307 				enum hdmi_infoframe_type type)
308 {
309 	struct drm_device *dev = encoder->dev;
310 	struct vc4_dev *vc4 = to_vc4_dev(dev);
311 	u32 packet_id = type - 0x80;
312 
313 	HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
314 		   HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
315 
316 	return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
317 			  BIT(packet_id)), 100);
318 }
319 
320 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
321 				     union hdmi_infoframe *frame)
322 {
323 	struct drm_device *dev = encoder->dev;
324 	struct vc4_dev *vc4 = to_vc4_dev(dev);
325 	u32 packet_id = frame->any.type - 0x80;
326 	u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
327 	uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
328 	ssize_t len, i;
329 	int ret;
330 
331 	WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
332 		    VC4_HDMI_RAM_PACKET_ENABLE),
333 		  "Packet RAM has to be on to store the packet.");
334 
335 	len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
336 	if (len < 0)
337 		return;
338 
339 	ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
340 	if (ret) {
341 		DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
342 		return;
343 	}
344 
345 	for (i = 0; i < len; i += 7) {
346 		HDMI_WRITE(packet_reg,
347 			   buffer[i + 0] << 0 |
348 			   buffer[i + 1] << 8 |
349 			   buffer[i + 2] << 16);
350 		packet_reg += 4;
351 
352 		HDMI_WRITE(packet_reg,
353 			   buffer[i + 3] << 0 |
354 			   buffer[i + 4] << 8 |
355 			   buffer[i + 5] << 16 |
356 			   buffer[i + 6] << 24);
357 		packet_reg += 4;
358 	}
359 
360 	HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
361 		   HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
362 	ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
363 			BIT(packet_id)), 100);
364 	if (ret)
365 		DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
366 }
367 
368 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
369 {
370 	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
371 	struct vc4_dev *vc4 = encoder->dev->dev_private;
372 	struct vc4_hdmi *hdmi = vc4->hdmi;
373 	struct drm_connector_state *cstate = hdmi->connector->state;
374 	struct drm_crtc *crtc = encoder->crtc;
375 	const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
376 	union hdmi_infoframe frame;
377 	int ret;
378 
379 	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
380 						       hdmi->connector, mode);
381 	if (ret < 0) {
382 		DRM_ERROR("couldn't fill AVI infoframe\n");
383 		return;
384 	}
385 
386 	drm_hdmi_avi_infoframe_quant_range(&frame.avi,
387 					   hdmi->connector, mode,
388 					   vc4_encoder->limited_rgb_range ?
389 					   HDMI_QUANTIZATION_RANGE_LIMITED :
390 					   HDMI_QUANTIZATION_RANGE_FULL);
391 
392 	frame.avi.right_bar = cstate->tv.margins.right;
393 	frame.avi.left_bar = cstate->tv.margins.left;
394 	frame.avi.top_bar = cstate->tv.margins.top;
395 	frame.avi.bottom_bar = cstate->tv.margins.bottom;
396 
397 	vc4_hdmi_write_infoframe(encoder, &frame);
398 }
399 
400 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
401 {
402 	union hdmi_infoframe frame;
403 	int ret;
404 
405 	ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
406 	if (ret < 0) {
407 		DRM_ERROR("couldn't fill SPD infoframe\n");
408 		return;
409 	}
410 
411 	frame.spd.sdi = HDMI_SPD_SDI_PC;
412 
413 	vc4_hdmi_write_infoframe(encoder, &frame);
414 }
415 
416 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
417 {
418 	struct drm_device *drm = encoder->dev;
419 	struct vc4_dev *vc4 = drm->dev_private;
420 	struct vc4_hdmi *hdmi = vc4->hdmi;
421 	union hdmi_infoframe frame;
422 	int ret;
423 
424 	ret = hdmi_audio_infoframe_init(&frame.audio);
425 
426 	frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
427 	frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
428 	frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
429 	frame.audio.channels = hdmi->audio.channels;
430 
431 	vc4_hdmi_write_infoframe(encoder, &frame);
432 }
433 
434 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
435 {
436 	vc4_hdmi_set_avi_infoframe(encoder);
437 	vc4_hdmi_set_spd_infoframe(encoder);
438 }
439 
440 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
441 {
442 	struct drm_device *dev = encoder->dev;
443 	struct vc4_dev *vc4 = to_vc4_dev(dev);
444 	struct vc4_hdmi *hdmi = vc4->hdmi;
445 	int ret;
446 
447 	HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
448 
449 	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
450 	HD_WRITE(VC4_HD_VID_CTL,
451 		 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
452 
453 	clk_disable_unprepare(hdmi->pixel_clock);
454 
455 	ret = pm_runtime_put(&hdmi->pdev->dev);
456 	if (ret < 0)
457 		DRM_ERROR("Failed to release power domain: %d\n", ret);
458 }
459 
460 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
461 {
462 	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
463 	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
464 	struct drm_device *dev = encoder->dev;
465 	struct vc4_dev *vc4 = to_vc4_dev(dev);
466 	struct vc4_hdmi *hdmi = vc4->hdmi;
467 	bool debug_dump_regs = false;
468 	bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
469 	bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
470 	bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
471 	u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
472 	u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
473 				   VC4_HDMI_VERTA_VSP) |
474 		     VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
475 				   VC4_HDMI_VERTA_VFP) |
476 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
477 	u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
478 		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
479 				   VC4_HDMI_VERTB_VBP));
480 	u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
481 			  VC4_SET_FIELD(mode->crtc_vtotal -
482 					mode->crtc_vsync_end -
483 					interlaced,
484 					VC4_HDMI_VERTB_VBP));
485 	u32 csc_ctl;
486 	int ret;
487 
488 	ret = pm_runtime_get_sync(&hdmi->pdev->dev);
489 	if (ret < 0) {
490 		DRM_ERROR("Failed to retain power domain: %d\n", ret);
491 		return;
492 	}
493 
494 	ret = clk_set_rate(hdmi->pixel_clock,
495 			   mode->clock * 1000 *
496 			   ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
497 	if (ret) {
498 		DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
499 		return;
500 	}
501 
502 	ret = clk_prepare_enable(hdmi->pixel_clock);
503 	if (ret) {
504 		DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
505 		return;
506 	}
507 
508 	HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
509 		   VC4_HDMI_SW_RESET_HDMI |
510 		   VC4_HDMI_SW_RESET_FORMAT_DETECT);
511 
512 	HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
513 
514 	/* PHY should be in reset, like
515 	 * vc4_hdmi_encoder_disable() does.
516 	 */
517 	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
518 
519 	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
520 
521 	if (debug_dump_regs) {
522 		struct drm_printer p = drm_info_printer(&hdmi->pdev->dev);
523 
524 		dev_info(&hdmi->pdev->dev, "HDMI regs before:\n");
525 		drm_print_regset32(&p, &hdmi->hdmi_regset);
526 		drm_print_regset32(&p, &hdmi->hd_regset);
527 	}
528 
529 	HD_WRITE(VC4_HD_VID_CTL, 0);
530 
531 	HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
532 		   HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
533 		   VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
534 		   VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
535 
536 	HDMI_WRITE(VC4_HDMI_HORZA,
537 		   (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
538 		   (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
539 		   VC4_SET_FIELD(mode->hdisplay * pixel_rep,
540 				 VC4_HDMI_HORZA_HAP));
541 
542 	HDMI_WRITE(VC4_HDMI_HORZB,
543 		   VC4_SET_FIELD((mode->htotal -
544 				  mode->hsync_end) * pixel_rep,
545 				 VC4_HDMI_HORZB_HBP) |
546 		   VC4_SET_FIELD((mode->hsync_end -
547 				  mode->hsync_start) * pixel_rep,
548 				 VC4_HDMI_HORZB_HSP) |
549 		   VC4_SET_FIELD((mode->hsync_start -
550 				  mode->hdisplay) * pixel_rep,
551 				 VC4_HDMI_HORZB_HFP));
552 
553 	HDMI_WRITE(VC4_HDMI_VERTA0, verta);
554 	HDMI_WRITE(VC4_HDMI_VERTA1, verta);
555 
556 	HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
557 	HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
558 
559 	HD_WRITE(VC4_HD_VID_CTL,
560 		 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
561 		 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
562 
563 	csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
564 				VC4_HD_CSC_CTL_ORDER);
565 
566 	if (vc4_encoder->hdmi_monitor &&
567 	    drm_default_rgb_quant_range(mode) ==
568 	    HDMI_QUANTIZATION_RANGE_LIMITED) {
569 		/* CEA VICs other than #1 requre limited range RGB
570 		 * output unless overridden by an AVI infoframe.
571 		 * Apply a colorspace conversion to squash 0-255 down
572 		 * to 16-235.  The matrix here is:
573 		 *
574 		 * [ 0      0      0.8594 16]
575 		 * [ 0      0.8594 0      16]
576 		 * [ 0.8594 0      0      16]
577 		 * [ 0      0      0       1]
578 		 */
579 		csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
580 		csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
581 		csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
582 					 VC4_HD_CSC_CTL_MODE);
583 
584 		HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
585 		HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
586 		HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
587 		HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
588 		HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
589 		HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
590 		vc4_encoder->limited_rgb_range = true;
591 	} else {
592 		vc4_encoder->limited_rgb_range = false;
593 	}
594 
595 	/* The RGB order applies even when CSC is disabled. */
596 	HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
597 
598 	HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
599 
600 	if (debug_dump_regs) {
601 		struct drm_printer p = drm_info_printer(&hdmi->pdev->dev);
602 
603 		dev_info(&hdmi->pdev->dev, "HDMI regs after:\n");
604 		drm_print_regset32(&p, &hdmi->hdmi_regset);
605 		drm_print_regset32(&p, &hdmi->hd_regset);
606 	}
607 
608 	HD_WRITE(VC4_HD_VID_CTL,
609 		 HD_READ(VC4_HD_VID_CTL) |
610 		 VC4_HD_VID_CTL_ENABLE |
611 		 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
612 		 VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
613 
614 	if (vc4_encoder->hdmi_monitor) {
615 		HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
616 			   HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
617 			   VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
618 
619 		ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
620 			       VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
621 		WARN_ONCE(ret, "Timeout waiting for "
622 			  "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
623 	} else {
624 		HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
625 			   HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
626 			   ~(VC4_HDMI_RAM_PACKET_ENABLE));
627 		HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
628 			   HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
629 			   ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
630 
631 		ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
632 				 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
633 		WARN_ONCE(ret, "Timeout waiting for "
634 			  "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
635 	}
636 
637 	if (vc4_encoder->hdmi_monitor) {
638 		u32 drift;
639 
640 		WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
641 			  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
642 		HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
643 			   HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
644 			   VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
645 
646 		HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
647 			   VC4_HDMI_RAM_PACKET_ENABLE);
648 
649 		vc4_hdmi_set_infoframes(encoder);
650 
651 		drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
652 		drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
653 
654 		HDMI_WRITE(VC4_HDMI_FIFO_CTL,
655 			   drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
656 		HDMI_WRITE(VC4_HDMI_FIFO_CTL,
657 			   drift | VC4_HDMI_FIFO_CTL_RECENTER);
658 		usleep_range(1000, 1100);
659 		HDMI_WRITE(VC4_HDMI_FIFO_CTL,
660 			   drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
661 		HDMI_WRITE(VC4_HDMI_FIFO_CTL,
662 			   drift | VC4_HDMI_FIFO_CTL_RECENTER);
663 
664 		ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
665 			       VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
666 		WARN_ONCE(ret, "Timeout waiting for "
667 			  "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
668 	}
669 }
670 
671 static enum drm_mode_status
672 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc,
673 			    const struct drm_display_mode *mode)
674 {
675 	/* HSM clock must be 108% of the pixel clock.  Additionally,
676 	 * the AXI clock needs to be at least 25% of pixel clock, but
677 	 * HSM ends up being the limiting factor.
678 	 */
679 	if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100))
680 		return MODE_CLOCK_HIGH;
681 
682 	return MODE_OK;
683 }
684 
685 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
686 	.mode_valid = vc4_hdmi_encoder_mode_valid,
687 	.disable = vc4_hdmi_encoder_disable,
688 	.enable = vc4_hdmi_encoder_enable,
689 };
690 
691 /* HDMI audio codec callbacks */
692 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
693 {
694 	struct drm_device *drm = hdmi->encoder->dev;
695 	struct vc4_dev *vc4 = to_vc4_dev(drm);
696 	u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
697 	unsigned long n, m;
698 
699 	rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
700 				    VC4_HD_MAI_SMP_N_MASK >>
701 				    VC4_HD_MAI_SMP_N_SHIFT,
702 				    (VC4_HD_MAI_SMP_M_MASK >>
703 				     VC4_HD_MAI_SMP_M_SHIFT) + 1,
704 				    &n, &m);
705 
706 	HD_WRITE(VC4_HD_MAI_SMP,
707 		 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
708 		 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
709 }
710 
711 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
712 {
713 	struct drm_encoder *encoder = hdmi->encoder;
714 	struct drm_crtc *crtc = encoder->crtc;
715 	struct drm_device *drm = encoder->dev;
716 	struct vc4_dev *vc4 = to_vc4_dev(drm);
717 	const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
718 	u32 samplerate = hdmi->audio.samplerate;
719 	u32 n, cts;
720 	u64 tmp;
721 
722 	n = 128 * samplerate / 1000;
723 	tmp = (u64)(mode->clock * 1000) * n;
724 	do_div(tmp, 128 * samplerate);
725 	cts = tmp;
726 
727 	HDMI_WRITE(VC4_HDMI_CRP_CFG,
728 		   VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
729 		   VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
730 
731 	/*
732 	 * We could get slightly more accurate clocks in some cases by
733 	 * providing a CTS_1 value.  The two CTS values are alternated
734 	 * between based on the period fields
735 	 */
736 	HDMI_WRITE(VC4_HDMI_CTS_0, cts);
737 	HDMI_WRITE(VC4_HDMI_CTS_1, cts);
738 }
739 
740 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
741 {
742 	struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
743 
744 	return snd_soc_card_get_drvdata(card);
745 }
746 
747 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
748 				  struct snd_soc_dai *dai)
749 {
750 	struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
751 	struct drm_encoder *encoder = hdmi->encoder;
752 	struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
753 	int ret;
754 
755 	if (hdmi->audio.substream && hdmi->audio.substream != substream)
756 		return -EINVAL;
757 
758 	hdmi->audio.substream = substream;
759 
760 	/*
761 	 * If the HDMI encoder hasn't probed, or the encoder is
762 	 * currently in DVI mode, treat the codec dai as missing.
763 	 */
764 	if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
765 				VC4_HDMI_RAM_PACKET_ENABLE))
766 		return -ENODEV;
767 
768 	ret = snd_pcm_hw_constraint_eld(substream->runtime,
769 					hdmi->connector->eld);
770 	if (ret)
771 		return ret;
772 
773 	return 0;
774 }
775 
776 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
777 {
778 	return 0;
779 }
780 
781 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
782 {
783 	struct drm_encoder *encoder = hdmi->encoder;
784 	struct drm_device *drm = encoder->dev;
785 	struct device *dev = &hdmi->pdev->dev;
786 	struct vc4_dev *vc4 = to_vc4_dev(drm);
787 	int ret;
788 
789 	ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
790 	if (ret)
791 		dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
792 
793 	HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
794 	HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
795 	HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
796 }
797 
798 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
799 				    struct snd_soc_dai *dai)
800 {
801 	struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
802 
803 	if (substream != hdmi->audio.substream)
804 		return;
805 
806 	vc4_hdmi_audio_reset(hdmi);
807 
808 	hdmi->audio.substream = NULL;
809 }
810 
811 /* HDMI audio codec callbacks */
812 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
813 				    struct snd_pcm_hw_params *params,
814 				    struct snd_soc_dai *dai)
815 {
816 	struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
817 	struct drm_encoder *encoder = hdmi->encoder;
818 	struct drm_device *drm = encoder->dev;
819 	struct device *dev = &hdmi->pdev->dev;
820 	struct vc4_dev *vc4 = to_vc4_dev(drm);
821 	u32 audio_packet_config, channel_mask;
822 	u32 channel_map, i;
823 
824 	if (substream != hdmi->audio.substream)
825 		return -EINVAL;
826 
827 	dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
828 		params_rate(params), params_width(params),
829 		params_channels(params));
830 
831 	hdmi->audio.channels = params_channels(params);
832 	hdmi->audio.samplerate = params_rate(params);
833 
834 	HD_WRITE(VC4_HD_MAI_CTL,
835 		 VC4_HD_MAI_CTL_RESET |
836 		 VC4_HD_MAI_CTL_FLUSH |
837 		 VC4_HD_MAI_CTL_DLATE |
838 		 VC4_HD_MAI_CTL_ERRORE |
839 		 VC4_HD_MAI_CTL_ERRORF);
840 
841 	vc4_hdmi_audio_set_mai_clock(hdmi);
842 
843 	audio_packet_config =
844 		VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
845 		VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
846 		VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
847 
848 	channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
849 	audio_packet_config |= VC4_SET_FIELD(channel_mask,
850 					     VC4_HDMI_AUDIO_PACKET_CEA_MASK);
851 
852 	/* Set the MAI threshold.  This logic mimics the firmware's. */
853 	if (hdmi->audio.samplerate > 96000) {
854 		HD_WRITE(VC4_HD_MAI_THR,
855 			 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
856 			 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
857 	} else if (hdmi->audio.samplerate > 48000) {
858 		HD_WRITE(VC4_HD_MAI_THR,
859 			 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
860 			 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
861 	} else {
862 		HD_WRITE(VC4_HD_MAI_THR,
863 			 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
864 			 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
865 			 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
866 			 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
867 	}
868 
869 	HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
870 		   VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
871 		   VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
872 
873 	channel_map = 0;
874 	for (i = 0; i < 8; i++) {
875 		if (channel_mask & BIT(i))
876 			channel_map |= i << (3 * i);
877 	}
878 
879 	HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
880 	HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
881 	vc4_hdmi_set_n_cts(hdmi);
882 
883 	return 0;
884 }
885 
886 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
887 				  struct snd_soc_dai *dai)
888 {
889 	struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
890 	struct drm_encoder *encoder = hdmi->encoder;
891 	struct drm_device *drm = encoder->dev;
892 	struct vc4_dev *vc4 = to_vc4_dev(drm);
893 
894 	switch (cmd) {
895 	case SNDRV_PCM_TRIGGER_START:
896 		vc4_hdmi_set_audio_infoframe(encoder);
897 		HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
898 			   HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
899 			   ~VC4_HDMI_TX_PHY_RNG_PWRDN);
900 		HD_WRITE(VC4_HD_MAI_CTL,
901 			 VC4_SET_FIELD(hdmi->audio.channels,
902 				       VC4_HD_MAI_CTL_CHNUM) |
903 			 VC4_HD_MAI_CTL_ENABLE);
904 		break;
905 	case SNDRV_PCM_TRIGGER_STOP:
906 		HD_WRITE(VC4_HD_MAI_CTL,
907 			 VC4_HD_MAI_CTL_DLATE |
908 			 VC4_HD_MAI_CTL_ERRORE |
909 			 VC4_HD_MAI_CTL_ERRORF);
910 		HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
911 			   HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
912 			   VC4_HDMI_TX_PHY_RNG_PWRDN);
913 		break;
914 	default:
915 		break;
916 	}
917 
918 	return 0;
919 }
920 
921 static inline struct vc4_hdmi *
922 snd_component_to_hdmi(struct snd_soc_component *component)
923 {
924 	struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
925 
926 	return snd_soc_card_get_drvdata(card);
927 }
928 
929 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
930 				       struct snd_ctl_elem_info *uinfo)
931 {
932 	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
933 	struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
934 
935 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
936 	uinfo->count = sizeof(hdmi->connector->eld);
937 
938 	return 0;
939 }
940 
941 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
942 				      struct snd_ctl_elem_value *ucontrol)
943 {
944 	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
945 	struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
946 
947 	memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
948 	       sizeof(hdmi->connector->eld));
949 
950 	return 0;
951 }
952 
953 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
954 	{
955 		.access = SNDRV_CTL_ELEM_ACCESS_READ |
956 			  SNDRV_CTL_ELEM_ACCESS_VOLATILE,
957 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
958 		.name = "ELD",
959 		.info = vc4_hdmi_audio_eld_ctl_info,
960 		.get = vc4_hdmi_audio_eld_ctl_get,
961 	},
962 };
963 
964 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
965 	SND_SOC_DAPM_OUTPUT("TX"),
966 };
967 
968 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
969 	{ "TX", NULL, "Playback" },
970 };
971 
972 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
973 	.controls		= vc4_hdmi_audio_controls,
974 	.num_controls		= ARRAY_SIZE(vc4_hdmi_audio_controls),
975 	.dapm_widgets		= vc4_hdmi_audio_widgets,
976 	.num_dapm_widgets	= ARRAY_SIZE(vc4_hdmi_audio_widgets),
977 	.dapm_routes		= vc4_hdmi_audio_routes,
978 	.num_dapm_routes	= ARRAY_SIZE(vc4_hdmi_audio_routes),
979 	.idle_bias_on		= 1,
980 	.use_pmdown_time	= 1,
981 	.endianness		= 1,
982 	.non_legacy_dai_naming	= 1,
983 };
984 
985 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
986 	.startup = vc4_hdmi_audio_startup,
987 	.shutdown = vc4_hdmi_audio_shutdown,
988 	.hw_params = vc4_hdmi_audio_hw_params,
989 	.set_fmt = vc4_hdmi_audio_set_fmt,
990 	.trigger = vc4_hdmi_audio_trigger,
991 };
992 
993 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
994 	.name = "vc4-hdmi-hifi",
995 	.playback = {
996 		.stream_name = "Playback",
997 		.channels_min = 2,
998 		.channels_max = 8,
999 		.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1000 			 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1001 			 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1002 			 SNDRV_PCM_RATE_192000,
1003 		.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1004 	},
1005 };
1006 
1007 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1008 	.name = "vc4-hdmi-cpu-dai-component",
1009 };
1010 
1011 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1012 {
1013 	struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1014 
1015 	snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1016 
1017 	return 0;
1018 }
1019 
1020 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1021 	.name = "vc4-hdmi-cpu-dai",
1022 	.probe  = vc4_hdmi_audio_cpu_dai_probe,
1023 	.playback = {
1024 		.stream_name = "Playback",
1025 		.channels_min = 1,
1026 		.channels_max = 8,
1027 		.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1028 			 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1029 			 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1030 			 SNDRV_PCM_RATE_192000,
1031 		.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1032 	},
1033 	.ops = &vc4_hdmi_audio_dai_ops,
1034 };
1035 
1036 static const struct snd_dmaengine_pcm_config pcm_conf = {
1037 	.chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1038 	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1039 };
1040 
1041 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1042 {
1043 	struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1044 	struct snd_soc_card *card = &hdmi->audio.card;
1045 	struct device *dev = &hdmi->pdev->dev;
1046 	const __be32 *addr;
1047 	int ret;
1048 
1049 	if (!of_find_property(dev->of_node, "dmas", NULL)) {
1050 		dev_warn(dev,
1051 			 "'dmas' DT property is missing, no HDMI audio\n");
1052 		return 0;
1053 	}
1054 
1055 	/*
1056 	 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1057 	 * the bus address specified in the DT, because the physical address
1058 	 * (the one returned by platform_get_resource()) is not appropriate
1059 	 * for DMA transfers.
1060 	 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1061 	 */
1062 	addr = of_get_address(dev->of_node, 1, NULL, NULL);
1063 	hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1064 	hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1065 	hdmi->audio.dma_data.maxburst = 2;
1066 
1067 	ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1068 	if (ret) {
1069 		dev_err(dev, "Could not register PCM component: %d\n", ret);
1070 		return ret;
1071 	}
1072 
1073 	ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1074 					      &vc4_hdmi_audio_cpu_dai_drv, 1);
1075 	if (ret) {
1076 		dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1077 		return ret;
1078 	}
1079 
1080 	/* register component and codec dai */
1081 	ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1082 				     &vc4_hdmi_audio_codec_dai_drv, 1);
1083 	if (ret) {
1084 		dev_err(dev, "Could not register component: %d\n", ret);
1085 		return ret;
1086 	}
1087 
1088 	dai_link->name = "MAI";
1089 	dai_link->stream_name = "MAI PCM";
1090 	dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1091 	dai_link->cpu_dai_name = dev_name(dev);
1092 	dai_link->codec_name = dev_name(dev);
1093 	dai_link->platform_name = dev_name(dev);
1094 
1095 	card->dai_link = dai_link;
1096 	card->num_links = 1;
1097 	card->name = "vc4-hdmi";
1098 	card->dev = dev;
1099 
1100 	/*
1101 	 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1102 	 * stores a pointer to the snd card object in dev->driver_data. This
1103 	 * means we cannot use it for something else. The hdmi back-pointer is
1104 	 * now stored in card->drvdata and should be retrieved with
1105 	 * snd_soc_card_get_drvdata() if needed.
1106 	 */
1107 	snd_soc_card_set_drvdata(card, hdmi);
1108 	ret = devm_snd_soc_register_card(dev, card);
1109 	if (ret)
1110 		dev_err(dev, "Could not register sound card: %d\n", ret);
1111 
1112 	return ret;
1113 
1114 }
1115 
1116 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1117 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1118 {
1119 	struct vc4_dev *vc4 = priv;
1120 	struct vc4_hdmi *hdmi = vc4->hdmi;
1121 
1122 	if (hdmi->cec_irq_was_rx) {
1123 		if (hdmi->cec_rx_msg.len)
1124 			cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
1125 	} else if (hdmi->cec_tx_ok) {
1126 		cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
1127 				  0, 0, 0, 0);
1128 	} else {
1129 		/*
1130 		 * This CEC implementation makes 1 retry, so if we
1131 		 * get a NACK, then that means it made 2 attempts.
1132 		 */
1133 		cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
1134 				  0, 2, 0, 0);
1135 	}
1136 	return IRQ_HANDLED;
1137 }
1138 
1139 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
1140 {
1141 	struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
1142 	unsigned int i;
1143 
1144 	msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1145 					VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1146 	for (i = 0; i < msg->len; i += 4) {
1147 		u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
1148 
1149 		msg->msg[i] = val & 0xff;
1150 		msg->msg[i + 1] = (val >> 8) & 0xff;
1151 		msg->msg[i + 2] = (val >> 16) & 0xff;
1152 		msg->msg[i + 3] = (val >> 24) & 0xff;
1153 	}
1154 }
1155 
1156 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1157 {
1158 	struct vc4_dev *vc4 = priv;
1159 	struct vc4_hdmi *hdmi = vc4->hdmi;
1160 	u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
1161 	u32 cntrl1, cntrl5;
1162 
1163 	if (!(stat & VC4_HDMI_CPU_CEC))
1164 		return IRQ_NONE;
1165 	hdmi->cec_rx_msg.len = 0;
1166 	cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1167 	cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1168 	hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1169 	if (hdmi->cec_irq_was_rx) {
1170 		vc4_cec_read_msg(vc4, cntrl1);
1171 		cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1172 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1173 		cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1174 	} else {
1175 		hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1176 		cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1177 	}
1178 	HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1179 	HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1180 
1181 	return IRQ_WAKE_THREAD;
1182 }
1183 
1184 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1185 {
1186 	struct vc4_dev *vc4 = cec_get_drvdata(adap);
1187 	/* clock period in microseconds */
1188 	const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1189 	u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1190 
1191 	val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1192 		 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1193 		 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1194 	val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1195 	       ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1196 
1197 	if (enable) {
1198 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1199 			   VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1200 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
1201 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
1202 			 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1203 			 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1204 			 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1205 			 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1206 			 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1207 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
1208 			 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1209 			 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1210 			 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1211 			 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1212 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
1213 			 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1214 			 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1215 			 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1216 			 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1217 
1218 		HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1219 	} else {
1220 		HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1221 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1222 			   VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1223 	}
1224 	return 0;
1225 }
1226 
1227 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1228 {
1229 	struct vc4_dev *vc4 = cec_get_drvdata(adap);
1230 
1231 	HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
1232 		   (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1233 		   (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1234 	return 0;
1235 }
1236 
1237 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1238 				      u32 signal_free_time, struct cec_msg *msg)
1239 {
1240 	struct vc4_dev *vc4 = cec_get_drvdata(adap);
1241 	u32 val;
1242 	unsigned int i;
1243 
1244 	for (i = 0; i < msg->len; i += 4)
1245 		HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
1246 			   (msg->msg[i]) |
1247 			   (msg->msg[i + 1] << 8) |
1248 			   (msg->msg[i + 2] << 16) |
1249 			   (msg->msg[i + 3] << 24));
1250 
1251 	val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1252 	val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1253 	HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1254 	val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1255 	val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1256 	val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1257 
1258 	HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1259 	return 0;
1260 }
1261 
1262 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1263 	.adap_enable = vc4_hdmi_cec_adap_enable,
1264 	.adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1265 	.adap_transmit = vc4_hdmi_cec_adap_transmit,
1266 };
1267 #endif
1268 
1269 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1270 {
1271 	struct platform_device *pdev = to_platform_device(dev);
1272 	struct drm_device *drm = dev_get_drvdata(master);
1273 	struct vc4_dev *vc4 = drm->dev_private;
1274 	struct vc4_hdmi *hdmi;
1275 	struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1276 	struct device_node *ddc_node;
1277 	u32 value;
1278 	int ret;
1279 
1280 	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1281 	if (!hdmi)
1282 		return -ENOMEM;
1283 
1284 	vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1285 					GFP_KERNEL);
1286 	if (!vc4_hdmi_encoder)
1287 		return -ENOMEM;
1288 	vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1289 	hdmi->encoder = &vc4_hdmi_encoder->base.base;
1290 
1291 	hdmi->pdev = pdev;
1292 	hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1293 	if (IS_ERR(hdmi->hdmicore_regs))
1294 		return PTR_ERR(hdmi->hdmicore_regs);
1295 
1296 	hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1297 	if (IS_ERR(hdmi->hd_regs))
1298 		return PTR_ERR(hdmi->hd_regs);
1299 
1300 	hdmi->hdmi_regset.base = hdmi->hdmicore_regs;
1301 	hdmi->hdmi_regset.regs = hdmi_regs;
1302 	hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs);
1303 	hdmi->hd_regset.base = hdmi->hd_regs;
1304 	hdmi->hd_regset.regs = hd_regs;
1305 	hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs);
1306 
1307 	hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1308 	if (IS_ERR(hdmi->pixel_clock)) {
1309 		DRM_ERROR("Failed to get pixel clock\n");
1310 		return PTR_ERR(hdmi->pixel_clock);
1311 	}
1312 	hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1313 	if (IS_ERR(hdmi->hsm_clock)) {
1314 		DRM_ERROR("Failed to get HDMI state machine clock\n");
1315 		return PTR_ERR(hdmi->hsm_clock);
1316 	}
1317 
1318 	ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1319 	if (!ddc_node) {
1320 		DRM_ERROR("Failed to find ddc node in device tree\n");
1321 		return -ENODEV;
1322 	}
1323 
1324 	hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1325 	of_node_put(ddc_node);
1326 	if (!hdmi->ddc) {
1327 		DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1328 		return -EPROBE_DEFER;
1329 	}
1330 
1331 	/* This is the rate that is set by the firmware.  The number
1332 	 * needs to be a bit higher than the pixel clock rate
1333 	 * (generally 148.5Mhz).
1334 	 */
1335 	ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
1336 	if (ret) {
1337 		DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1338 		goto err_put_i2c;
1339 	}
1340 
1341 	ret = clk_prepare_enable(hdmi->hsm_clock);
1342 	if (ret) {
1343 		DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1344 			  ret);
1345 		goto err_put_i2c;
1346 	}
1347 
1348 	/* Only use the GPIO HPD pin if present in the DT, otherwise
1349 	 * we'll use the HDMI core's register.
1350 	 */
1351 	if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1352 		enum of_gpio_flags hpd_gpio_flags;
1353 
1354 		hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1355 							 "hpd-gpios", 0,
1356 							 &hpd_gpio_flags);
1357 		if (hdmi->hpd_gpio < 0) {
1358 			ret = hdmi->hpd_gpio;
1359 			goto err_unprepare_hsm;
1360 		}
1361 
1362 		hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1363 	}
1364 
1365 	vc4->hdmi = hdmi;
1366 
1367 	/* HDMI core must be enabled. */
1368 	if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1369 		HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1370 		udelay(1);
1371 		HD_WRITE(VC4_HD_M_CTL, 0);
1372 
1373 		HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1374 	}
1375 	pm_runtime_enable(dev);
1376 
1377 	drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
1378 			 DRM_MODE_ENCODER_TMDS, NULL);
1379 	drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1380 
1381 	hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
1382 	if (IS_ERR(hdmi->connector)) {
1383 		ret = PTR_ERR(hdmi->connector);
1384 		goto err_destroy_encoder;
1385 	}
1386 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1387 	hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1388 					      vc4, "vc4",
1389 					      CEC_CAP_TRANSMIT |
1390 					      CEC_CAP_LOG_ADDRS |
1391 					      CEC_CAP_PASSTHROUGH |
1392 					      CEC_CAP_RC, 1);
1393 	ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
1394 	if (ret < 0)
1395 		goto err_destroy_conn;
1396 	HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
1397 	value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1398 	value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1399 	/*
1400 	 * Set the logical address to Unregistered and set the clock
1401 	 * divider: the hsm_clock rate and this divider setting will
1402 	 * give a 40 kHz CEC clock.
1403 	 */
1404 	value |= VC4_HDMI_CEC_ADDR_MASK |
1405 		 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1406 	HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
1407 	ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1408 					vc4_cec_irq_handler,
1409 					vc4_cec_irq_handler_thread, 0,
1410 					"vc4 hdmi cec", vc4);
1411 	if (ret)
1412 		goto err_delete_cec_adap;
1413 	ret = cec_register_adapter(hdmi->cec_adap, dev);
1414 	if (ret < 0)
1415 		goto err_delete_cec_adap;
1416 #endif
1417 
1418 	ret = vc4_hdmi_audio_init(hdmi);
1419 	if (ret)
1420 		goto err_destroy_encoder;
1421 
1422 	vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi);
1423 
1424 	return 0;
1425 
1426 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1427 err_delete_cec_adap:
1428 	cec_delete_adapter(hdmi->cec_adap);
1429 err_destroy_conn:
1430 	vc4_hdmi_connector_destroy(hdmi->connector);
1431 #endif
1432 err_destroy_encoder:
1433 	vc4_hdmi_encoder_destroy(hdmi->encoder);
1434 err_unprepare_hsm:
1435 	clk_disable_unprepare(hdmi->hsm_clock);
1436 	pm_runtime_disable(dev);
1437 err_put_i2c:
1438 	put_device(&hdmi->ddc->dev);
1439 
1440 	return ret;
1441 }
1442 
1443 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1444 			    void *data)
1445 {
1446 	struct drm_device *drm = dev_get_drvdata(master);
1447 	struct vc4_dev *vc4 = drm->dev_private;
1448 	struct vc4_hdmi *hdmi = vc4->hdmi;
1449 
1450 	cec_unregister_adapter(hdmi->cec_adap);
1451 	vc4_hdmi_connector_destroy(hdmi->connector);
1452 	vc4_hdmi_encoder_destroy(hdmi->encoder);
1453 
1454 	clk_disable_unprepare(hdmi->hsm_clock);
1455 	pm_runtime_disable(dev);
1456 
1457 	put_device(&hdmi->ddc->dev);
1458 
1459 	vc4->hdmi = NULL;
1460 }
1461 
1462 static const struct component_ops vc4_hdmi_ops = {
1463 	.bind   = vc4_hdmi_bind,
1464 	.unbind = vc4_hdmi_unbind,
1465 };
1466 
1467 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1468 {
1469 	return component_add(&pdev->dev, &vc4_hdmi_ops);
1470 }
1471 
1472 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1473 {
1474 	component_del(&pdev->dev, &vc4_hdmi_ops);
1475 	return 0;
1476 }
1477 
1478 static const struct of_device_id vc4_hdmi_dt_match[] = {
1479 	{ .compatible = "brcm,bcm2835-hdmi" },
1480 	{}
1481 };
1482 
1483 struct platform_driver vc4_hdmi_driver = {
1484 	.probe = vc4_hdmi_dev_probe,
1485 	.remove = vc4_hdmi_dev_remove,
1486 	.driver = {
1487 		.name = "vc4_hdmi",
1488 		.of_match_table = vc4_hdmi_dt_match,
1489 	},
1490 };
1491