1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/display/drm_scdc_helper.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_drv.h> 38 #include <drm/drm_probe_helper.h> 39 #include <drm/drm_simple_kms_helper.h> 40 #include <linux/clk.h> 41 #include <linux/component.h> 42 #include <linux/gpio/consumer.h> 43 #include <linux/i2c.h> 44 #include <linux/of_address.h> 45 #include <linux/of_platform.h> 46 #include <linux/pm_runtime.h> 47 #include <linux/rational.h> 48 #include <linux/reset.h> 49 #include <sound/dmaengine_pcm.h> 50 #include <sound/hdmi-codec.h> 51 #include <sound/pcm_drm_eld.h> 52 #include <sound/pcm_params.h> 53 #include <sound/soc.h> 54 #include "media/cec.h" 55 #include "vc4_drv.h" 56 #include "vc4_hdmi.h" 57 #include "vc4_hdmi_regs.h" 58 #include "vc4_regs.h" 59 60 #define VC5_HDMI_HORZA_HFP_SHIFT 16 61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 62 #define VC5_HDMI_HORZA_VPOS BIT(15) 63 #define VC5_HDMI_HORZA_HPOS BIT(14) 64 #define VC5_HDMI_HORZA_HAP_SHIFT 0 65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 66 67 #define VC5_HDMI_HORZB_HBP_SHIFT 16 68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 69 #define VC5_HDMI_HORZB_HSP_SHIFT 0 70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 71 72 #define VC5_HDMI_VERTA_VSP_SHIFT 24 73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 74 #define VC5_HDMI_VERTA_VFP_SHIFT 16 75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 76 #define VC5_HDMI_VERTA_VAL_SHIFT 0 77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 78 79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 81 82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 86 87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 88 89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 91 92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 94 95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 96 97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 99 100 # define VC4_HD_M_SW_RST BIT(2) 101 # define VC4_HD_M_ENABLE BIT(0) 102 103 #define HSM_MIN_CLOCK_FREQ 120000000 104 #define CEC_CLOCK_FREQ 40000 105 106 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 107 108 static const char * const output_format_str[] = { 109 [VC4_HDMI_OUTPUT_RGB] = "RGB", 110 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0", 111 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2", 112 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4", 113 }; 114 115 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt) 116 { 117 if (fmt >= ARRAY_SIZE(output_format_str)) 118 return "invalid"; 119 120 return output_format_str[fmt]; 121 } 122 123 static unsigned long long 124 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 125 unsigned int bpc, enum vc4_hdmi_output_format fmt); 126 127 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 128 { 129 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 130 131 lockdep_assert_held(&vc4_hdmi->mutex); 132 133 if (!display->is_hdmi) 134 return false; 135 136 if (!display->hdmi.scdc.supported || 137 !display->hdmi.scdc.scrambling.supported) 138 return false; 139 140 return true; 141 } 142 143 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 144 unsigned int bpc, 145 enum vc4_hdmi_output_format fmt) 146 { 147 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 148 149 return clock > HDMI_14_MAX_TMDS_CLK; 150 } 151 152 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 153 const struct drm_display_mode *mode) 154 { 155 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 156 157 return !display->is_hdmi || 158 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 159 } 160 161 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 162 { 163 struct drm_debugfs_entry *entry = m->private; 164 struct vc4_hdmi *vc4_hdmi = entry->file.data; 165 struct drm_device *drm = vc4_hdmi->connector.dev; 166 struct drm_printer p = drm_seq_file_printer(m); 167 int idx; 168 169 if (!drm_dev_enter(drm, &idx)) 170 return -ENODEV; 171 172 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 173 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 174 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 175 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 176 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 177 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 178 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 179 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 180 181 drm_dev_exit(idx); 182 183 return 0; 184 } 185 186 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 187 { 188 struct drm_device *drm = vc4_hdmi->connector.dev; 189 unsigned long flags; 190 int idx; 191 192 /* 193 * We can be called by our bind callback, when the 194 * connector->dev pointer might not be initialised yet. 195 */ 196 if (drm && !drm_dev_enter(drm, &idx)) 197 return; 198 199 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 200 201 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 202 udelay(1); 203 HDMI_WRITE(HDMI_M_CTL, 0); 204 205 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 206 207 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 208 VC4_HDMI_SW_RESET_HDMI | 209 VC4_HDMI_SW_RESET_FORMAT_DETECT); 210 211 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 212 213 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 214 215 if (drm) 216 drm_dev_exit(idx); 217 } 218 219 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 220 { 221 struct drm_device *drm = vc4_hdmi->connector.dev; 222 unsigned long flags; 223 int idx; 224 225 /* 226 * We can be called by our bind callback, when the 227 * connector->dev pointer might not be initialised yet. 228 */ 229 if (drm && !drm_dev_enter(drm, &idx)) 230 return; 231 232 reset_control_reset(vc4_hdmi->reset); 233 234 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 235 236 HDMI_WRITE(HDMI_DVP_CTL, 0); 237 238 HDMI_WRITE(HDMI_CLOCK_STOP, 239 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 240 241 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 242 243 if (drm) 244 drm_dev_exit(idx); 245 } 246 247 #ifdef CONFIG_DRM_VC4_HDMI_CEC 248 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 249 { 250 struct drm_device *drm = vc4_hdmi->connector.dev; 251 unsigned long cec_rate; 252 unsigned long flags; 253 u16 clk_cnt; 254 u32 value; 255 int idx; 256 257 /* 258 * This function is called by our runtime_resume implementation 259 * and thus at bind time, when we haven't registered our 260 * connector yet and thus don't have a pointer to the DRM 261 * device. 262 */ 263 if (drm && !drm_dev_enter(drm, &idx)) 264 return; 265 266 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 267 268 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 269 270 value = HDMI_READ(HDMI_CEC_CNTRL_1); 271 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 272 273 /* 274 * Set the clock divider: the hsm_clock rate and this divider 275 * setting will give a 40 kHz CEC clock. 276 */ 277 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 278 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 279 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 280 281 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 282 283 if (drm) 284 drm_dev_exit(idx); 285 } 286 #else 287 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 288 #endif 289 290 static int reset_pipe(struct drm_crtc *crtc, 291 struct drm_modeset_acquire_ctx *ctx) 292 { 293 struct drm_atomic_state *state; 294 struct drm_crtc_state *crtc_state; 295 int ret; 296 297 state = drm_atomic_state_alloc(crtc->dev); 298 if (!state) 299 return -ENOMEM; 300 301 state->acquire_ctx = ctx; 302 303 crtc_state = drm_atomic_get_crtc_state(state, crtc); 304 if (IS_ERR(crtc_state)) { 305 ret = PTR_ERR(crtc_state); 306 goto out; 307 } 308 309 crtc_state->connectors_changed = true; 310 311 ret = drm_atomic_commit(state); 312 out: 313 drm_atomic_state_put(state); 314 315 return ret; 316 } 317 318 static int vc4_hdmi_reset_link(struct drm_connector *connector, 319 struct drm_modeset_acquire_ctx *ctx) 320 { 321 struct drm_device *drm; 322 struct vc4_hdmi *vc4_hdmi; 323 struct drm_connector_state *conn_state; 324 struct drm_crtc_state *crtc_state; 325 struct drm_crtc *crtc; 326 bool scrambling_needed; 327 u8 config; 328 int ret; 329 330 if (!connector) 331 return 0; 332 333 drm = connector->dev; 334 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 335 if (ret) 336 return ret; 337 338 conn_state = connector->state; 339 crtc = conn_state->crtc; 340 if (!crtc) 341 return 0; 342 343 ret = drm_modeset_lock(&crtc->mutex, ctx); 344 if (ret) 345 return ret; 346 347 crtc_state = crtc->state; 348 if (!crtc_state->active) 349 return 0; 350 351 vc4_hdmi = connector_to_vc4_hdmi(connector); 352 mutex_lock(&vc4_hdmi->mutex); 353 354 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 355 mutex_unlock(&vc4_hdmi->mutex); 356 return 0; 357 } 358 359 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 360 vc4_hdmi->output_bpc, 361 vc4_hdmi->output_format); 362 if (!scrambling_needed) { 363 mutex_unlock(&vc4_hdmi->mutex); 364 return 0; 365 } 366 367 if (conn_state->commit && 368 !try_wait_for_completion(&conn_state->commit->hw_done)) { 369 mutex_unlock(&vc4_hdmi->mutex); 370 return 0; 371 } 372 373 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 374 if (ret < 0) { 375 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 376 mutex_unlock(&vc4_hdmi->mutex); 377 return 0; 378 } 379 380 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 381 mutex_unlock(&vc4_hdmi->mutex); 382 return 0; 383 } 384 385 mutex_unlock(&vc4_hdmi->mutex); 386 387 /* 388 * HDMI 2.0 says that one should not send scrambled data 389 * prior to configuring the sink scrambling, and that 390 * TMDS clock/data transmission should be suspended when 391 * changing the TMDS clock rate in the sink. So let's 392 * just do a full modeset here, even though some sinks 393 * would be perfectly happy if were to just reconfigure 394 * the SCDC settings on the fly. 395 */ 396 return reset_pipe(crtc, ctx); 397 } 398 399 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 400 struct drm_modeset_acquire_ctx *ctx, 401 enum drm_connector_status status) 402 { 403 struct drm_connector *connector = &vc4_hdmi->connector; 404 struct edid *edid; 405 int ret; 406 407 /* 408 * NOTE: This function should really be called with 409 * vc4_hdmi->mutex held, but doing so results in reentrancy 410 * issues since cec_s_phys_addr_from_edid might call 411 * .adap_enable, which leads to that funtion being called with 412 * our mutex held. 413 * 414 * A similar situation occurs with vc4_hdmi_reset_link() that 415 * will call into our KMS hooks if the scrambling was enabled. 416 * 417 * Concurrency isn't an issue at the moment since we don't share 418 * any state with any of the other frameworks so we can ignore 419 * the lock for now. 420 */ 421 422 if (status == connector_status_disconnected) { 423 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 424 return; 425 } 426 427 edid = drm_get_edid(connector, vc4_hdmi->ddc); 428 if (!edid) 429 return; 430 431 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 432 kfree(edid); 433 434 for (;;) { 435 ret = vc4_hdmi_reset_link(connector, ctx); 436 if (ret == -EDEADLK) { 437 drm_modeset_backoff(ctx); 438 continue; 439 } 440 441 break; 442 } 443 } 444 445 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 446 struct drm_modeset_acquire_ctx *ctx, 447 bool force) 448 { 449 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 450 enum drm_connector_status status = connector_status_disconnected; 451 452 /* 453 * NOTE: This function should really take vc4_hdmi->mutex, but 454 * doing so results in reentrancy issues since 455 * vc4_hdmi_handle_hotplug() can call into other functions that 456 * would take the mutex while it's held here. 457 * 458 * Concurrency isn't an issue at the moment since we don't share 459 * any state with any of the other frameworks so we can ignore 460 * the lock for now. 461 */ 462 463 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 464 465 if (vc4_hdmi->hpd_gpio) { 466 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 467 status = connector_status_connected; 468 } else { 469 if (vc4_hdmi->variant->hp_detect && 470 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 471 status = connector_status_connected; 472 } 473 474 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 475 pm_runtime_put(&vc4_hdmi->pdev->dev); 476 477 return status; 478 } 479 480 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 481 { 482 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 483 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 484 int ret = 0; 485 struct edid *edid; 486 487 /* 488 * NOTE: This function should really take vc4_hdmi->mutex, but 489 * doing so results in reentrancy issues since 490 * cec_s_phys_addr_from_edid might call .adap_enable, which 491 * leads to that funtion being called with our mutex held. 492 * 493 * Concurrency isn't an issue at the moment since we don't share 494 * any state with any of the other frameworks so we can ignore 495 * the lock for now. 496 */ 497 498 edid = drm_get_edid(connector, vc4_hdmi->ddc); 499 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 500 if (!edid) 501 return -ENODEV; 502 503 drm_connector_update_edid_property(connector, edid); 504 ret = drm_add_edid_modes(connector, edid); 505 kfree(edid); 506 507 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 508 struct drm_device *drm = connector->dev; 509 const struct drm_display_mode *mode; 510 511 list_for_each_entry(mode, &connector->probed_modes, head) { 512 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) { 513 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 514 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 515 } 516 } 517 } 518 519 return ret; 520 } 521 522 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 523 struct drm_atomic_state *state) 524 { 525 struct drm_connector_state *old_state = 526 drm_atomic_get_old_connector_state(state, connector); 527 struct drm_connector_state *new_state = 528 drm_atomic_get_new_connector_state(state, connector); 529 struct drm_crtc *crtc = new_state->crtc; 530 531 if (!crtc) 532 return 0; 533 534 if (old_state->colorspace != new_state->colorspace || 535 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 536 struct drm_crtc_state *crtc_state; 537 538 crtc_state = drm_atomic_get_crtc_state(state, crtc); 539 if (IS_ERR(crtc_state)) 540 return PTR_ERR(crtc_state); 541 542 crtc_state->mode_changed = true; 543 } 544 545 return 0; 546 } 547 548 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 549 { 550 struct vc4_hdmi_connector_state *old_state = 551 conn_state_to_vc4_hdmi_conn_state(connector->state); 552 struct vc4_hdmi_connector_state *new_state = 553 kzalloc(sizeof(*new_state), GFP_KERNEL); 554 555 if (connector->state) 556 __drm_atomic_helper_connector_destroy_state(connector->state); 557 558 kfree(old_state); 559 __drm_atomic_helper_connector_reset(connector, &new_state->base); 560 561 if (!new_state) 562 return; 563 564 new_state->base.max_bpc = 8; 565 new_state->base.max_requested_bpc = 8; 566 new_state->output_format = VC4_HDMI_OUTPUT_RGB; 567 drm_atomic_helper_connector_tv_margins_reset(connector); 568 } 569 570 static struct drm_connector_state * 571 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 572 { 573 struct drm_connector_state *conn_state = connector->state; 574 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 575 struct vc4_hdmi_connector_state *new_state; 576 577 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 578 if (!new_state) 579 return NULL; 580 581 new_state->tmds_char_rate = vc4_state->tmds_char_rate; 582 new_state->output_bpc = vc4_state->output_bpc; 583 new_state->output_format = vc4_state->output_format; 584 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 585 586 return &new_state->base; 587 } 588 589 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 590 .fill_modes = drm_helper_probe_single_connector_modes, 591 .reset = vc4_hdmi_connector_reset, 592 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 593 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 594 }; 595 596 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 597 .detect_ctx = vc4_hdmi_connector_detect_ctx, 598 .get_modes = vc4_hdmi_connector_get_modes, 599 .atomic_check = vc4_hdmi_connector_atomic_check, 600 }; 601 602 static int vc4_hdmi_connector_init(struct drm_device *dev, 603 struct vc4_hdmi *vc4_hdmi) 604 { 605 struct drm_connector *connector = &vc4_hdmi->connector; 606 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 607 int ret; 608 609 ret = drmm_connector_init(dev, connector, 610 &vc4_hdmi_connector_funcs, 611 DRM_MODE_CONNECTOR_HDMIA, 612 vc4_hdmi->ddc); 613 if (ret) 614 return ret; 615 616 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 617 618 /* 619 * Some of the properties below require access to state, like bpc. 620 * Allocate some default initial connector state with our reset helper. 621 */ 622 if (connector->funcs->reset) 623 connector->funcs->reset(connector); 624 625 /* Create and attach TV margin props to this connector. */ 626 ret = drm_mode_create_tv_margin_properties(dev); 627 if (ret) 628 return ret; 629 630 ret = drm_mode_create_hdmi_colorspace_property(connector); 631 if (ret) 632 return ret; 633 634 drm_connector_attach_colorspace_property(connector); 635 drm_connector_attach_tv_margin_properties(connector); 636 drm_connector_attach_max_bpc_property(connector, 8, 12); 637 638 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 639 DRM_CONNECTOR_POLL_DISCONNECT); 640 641 connector->interlace_allowed = 1; 642 connector->doublescan_allowed = 0; 643 connector->stereo_allowed = 1; 644 645 if (vc4_hdmi->variant->supports_hdr) 646 drm_connector_attach_hdr_output_metadata_property(connector); 647 648 drm_connector_attach_encoder(connector, encoder); 649 650 return 0; 651 } 652 653 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 654 enum hdmi_infoframe_type type, 655 bool poll) 656 { 657 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 658 struct drm_device *drm = vc4_hdmi->connector.dev; 659 u32 packet_id = type - 0x80; 660 unsigned long flags; 661 int ret = 0; 662 int idx; 663 664 if (!drm_dev_enter(drm, &idx)) 665 return -ENODEV; 666 667 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 668 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 669 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 670 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 671 672 if (poll) { 673 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 674 BIT(packet_id)), 100); 675 } 676 677 drm_dev_exit(idx); 678 return ret; 679 } 680 681 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 682 union hdmi_infoframe *frame) 683 { 684 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 685 struct drm_device *drm = vc4_hdmi->connector.dev; 686 u32 packet_id = frame->any.type - 0x80; 687 const struct vc4_hdmi_register *ram_packet_start = 688 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 689 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 690 u32 packet_reg_next = ram_packet_start->offset + 691 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 692 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 693 ram_packet_start->reg); 694 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 695 unsigned long flags; 696 ssize_t len, i; 697 int ret; 698 int idx; 699 700 if (!drm_dev_enter(drm, &idx)) 701 return; 702 703 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 704 VC4_HDMI_RAM_PACKET_ENABLE), 705 "Packet RAM has to be on to store the packet."); 706 707 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 708 if (len < 0) 709 goto out; 710 711 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 712 if (ret) { 713 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 714 goto out; 715 } 716 717 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 718 719 for (i = 0; i < len; i += 7) { 720 writel(buffer[i + 0] << 0 | 721 buffer[i + 1] << 8 | 722 buffer[i + 2] << 16, 723 base + packet_reg); 724 packet_reg += 4; 725 726 writel(buffer[i + 3] << 0 | 727 buffer[i + 4] << 8 | 728 buffer[i + 5] << 16 | 729 buffer[i + 6] << 24, 730 base + packet_reg); 731 packet_reg += 4; 732 } 733 734 /* 735 * clear remainder of packet ram as it's included in the 736 * infoframe and triggers a checksum error on hdmi analyser 737 */ 738 for (; packet_reg < packet_reg_next; packet_reg += 4) 739 writel(0, base + packet_reg); 740 741 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 742 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 743 744 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 745 746 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 747 BIT(packet_id)), 100); 748 if (ret) 749 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 750 751 out: 752 drm_dev_exit(idx); 753 } 754 755 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 756 enum vc4_hdmi_output_format fmt) 757 { 758 switch (fmt) { 759 case VC4_HDMI_OUTPUT_RGB: 760 frame->colorspace = HDMI_COLORSPACE_RGB; 761 break; 762 763 case VC4_HDMI_OUTPUT_YUV420: 764 frame->colorspace = HDMI_COLORSPACE_YUV420; 765 break; 766 767 case VC4_HDMI_OUTPUT_YUV422: 768 frame->colorspace = HDMI_COLORSPACE_YUV422; 769 break; 770 771 case VC4_HDMI_OUTPUT_YUV444: 772 frame->colorspace = HDMI_COLORSPACE_YUV444; 773 break; 774 775 default: 776 break; 777 } 778 } 779 780 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 781 { 782 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 783 struct drm_connector *connector = &vc4_hdmi->connector; 784 struct drm_connector_state *cstate = connector->state; 785 struct vc4_hdmi_connector_state *vc4_state = 786 conn_state_to_vc4_hdmi_conn_state(cstate); 787 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 788 union hdmi_infoframe frame; 789 int ret; 790 791 lockdep_assert_held(&vc4_hdmi->mutex); 792 793 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 794 connector, mode); 795 if (ret < 0) { 796 DRM_ERROR("couldn't fill AVI infoframe\n"); 797 return; 798 } 799 800 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 801 connector, mode, 802 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 803 HDMI_QUANTIZATION_RANGE_FULL : 804 HDMI_QUANTIZATION_RANGE_LIMITED); 805 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 806 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format); 807 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 808 809 vc4_hdmi_write_infoframe(encoder, &frame); 810 } 811 812 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 813 { 814 union hdmi_infoframe frame; 815 int ret; 816 817 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 818 if (ret < 0) { 819 DRM_ERROR("couldn't fill SPD infoframe\n"); 820 return; 821 } 822 823 frame.spd.sdi = HDMI_SPD_SDI_PC; 824 825 vc4_hdmi_write_infoframe(encoder, &frame); 826 } 827 828 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 829 { 830 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 831 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 832 union hdmi_infoframe frame; 833 834 memcpy(&frame.audio, audio, sizeof(*audio)); 835 836 if (vc4_hdmi->packet_ram_enabled) 837 vc4_hdmi_write_infoframe(encoder, &frame); 838 } 839 840 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 841 { 842 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 843 struct drm_connector *connector = &vc4_hdmi->connector; 844 struct drm_connector_state *conn_state = connector->state; 845 union hdmi_infoframe frame; 846 847 lockdep_assert_held(&vc4_hdmi->mutex); 848 849 if (!vc4_hdmi->variant->supports_hdr) 850 return; 851 852 if (!conn_state->hdr_output_metadata) 853 return; 854 855 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 856 return; 857 858 vc4_hdmi_write_infoframe(encoder, &frame); 859 } 860 861 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 862 { 863 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 864 865 lockdep_assert_held(&vc4_hdmi->mutex); 866 867 vc4_hdmi_set_avi_infoframe(encoder); 868 vc4_hdmi_set_spd_infoframe(encoder); 869 /* 870 * If audio was streaming, then we need to reenabled the audio 871 * infoframe here during encoder_enable. 872 */ 873 if (vc4_hdmi->audio.streaming) 874 vc4_hdmi_set_audio_infoframe(encoder); 875 876 vc4_hdmi_set_hdr_infoframe(encoder); 877 } 878 879 #define SCRAMBLING_POLLING_DELAY_MS 1000 880 881 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 882 { 883 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 884 struct drm_device *drm = vc4_hdmi->connector.dev; 885 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 886 unsigned long flags; 887 int idx; 888 889 lockdep_assert_held(&vc4_hdmi->mutex); 890 891 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 892 return; 893 894 if (!vc4_hdmi_mode_needs_scrambling(mode, 895 vc4_hdmi->output_bpc, 896 vc4_hdmi->output_format)) 897 return; 898 899 if (!drm_dev_enter(drm, &idx)) 900 return; 901 902 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 903 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 904 905 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 906 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 907 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 908 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 909 910 drm_dev_exit(idx); 911 912 vc4_hdmi->scdc_enabled = true; 913 914 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 915 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 916 } 917 918 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 919 { 920 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 921 struct drm_device *drm = vc4_hdmi->connector.dev; 922 unsigned long flags; 923 int idx; 924 925 lockdep_assert_held(&vc4_hdmi->mutex); 926 927 if (!vc4_hdmi->scdc_enabled) 928 return; 929 930 vc4_hdmi->scdc_enabled = false; 931 932 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 933 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 934 935 if (!drm_dev_enter(drm, &idx)) 936 return; 937 938 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 939 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 940 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 941 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 942 943 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 944 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 945 946 drm_dev_exit(idx); 947 } 948 949 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 950 { 951 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 952 struct vc4_hdmi, 953 scrambling_work); 954 955 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 956 return; 957 958 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 959 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 960 961 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 962 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 963 } 964 965 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 966 struct drm_atomic_state *state) 967 { 968 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 969 struct drm_device *drm = vc4_hdmi->connector.dev; 970 unsigned long flags; 971 int idx; 972 973 mutex_lock(&vc4_hdmi->mutex); 974 975 vc4_hdmi->packet_ram_enabled = false; 976 977 if (!drm_dev_enter(drm, &idx)) 978 goto out; 979 980 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 981 982 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 983 984 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 985 986 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 987 988 mdelay(1); 989 990 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 991 HDMI_WRITE(HDMI_VID_CTL, 992 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 993 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 994 995 vc4_hdmi_disable_scrambling(encoder); 996 997 drm_dev_exit(idx); 998 999 out: 1000 mutex_unlock(&vc4_hdmi->mutex); 1001 } 1002 1003 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 1004 struct drm_atomic_state *state) 1005 { 1006 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1007 struct drm_device *drm = vc4_hdmi->connector.dev; 1008 unsigned long flags; 1009 int ret; 1010 int idx; 1011 1012 mutex_lock(&vc4_hdmi->mutex); 1013 1014 if (!drm_dev_enter(drm, &idx)) 1015 goto out; 1016 1017 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1018 HDMI_WRITE(HDMI_VID_CTL, 1019 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 1020 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1021 1022 if (vc4_hdmi->variant->phy_disable) 1023 vc4_hdmi->variant->phy_disable(vc4_hdmi); 1024 1025 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 1026 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1027 1028 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 1029 if (ret < 0) 1030 DRM_ERROR("Failed to release power domain: %d\n", ret); 1031 1032 drm_dev_exit(idx); 1033 1034 out: 1035 mutex_unlock(&vc4_hdmi->mutex); 1036 } 1037 1038 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1039 struct drm_connector_state *state, 1040 const struct drm_display_mode *mode) 1041 { 1042 struct drm_device *drm = vc4_hdmi->connector.dev; 1043 unsigned long flags; 1044 u32 csc_ctl; 1045 int idx; 1046 1047 if (!drm_dev_enter(drm, &idx)) 1048 return; 1049 1050 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1051 1052 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 1053 VC4_HD_CSC_CTL_ORDER); 1054 1055 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 1056 /* CEA VICs other than #1 requre limited range RGB 1057 * output unless overridden by an AVI infoframe. 1058 * Apply a colorspace conversion to squash 0-255 down 1059 * to 16-235. The matrix here is: 1060 * 1061 * [ 0 0 0.8594 16] 1062 * [ 0 0.8594 0 16] 1063 * [ 0.8594 0 0 16] 1064 * [ 0 0 0 1] 1065 */ 1066 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 1067 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 1068 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1069 VC4_HD_CSC_CTL_MODE); 1070 1071 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 1072 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 1073 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 1074 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 1075 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 1076 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 1077 } 1078 1079 /* The RGB order applies even when CSC is disabled. */ 1080 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1081 1082 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1083 1084 drm_dev_exit(idx); 1085 } 1086 1087 /* 1088 * If we need to output Full Range RGB, then use the unity matrix 1089 * 1090 * [ 1 0 0 0] 1091 * [ 0 1 0 0] 1092 * [ 0 0 1 0] 1093 * 1094 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1095 */ 1096 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 1097 { 0x2000, 0x0000, 0x0000, 0x0000 }, 1098 { 0x0000, 0x2000, 0x0000, 0x0000 }, 1099 { 0x0000, 0x0000, 0x2000, 0x0000 }, 1100 }; 1101 1102 /* 1103 * CEA VICs other than #1 require limited range RGB output unless 1104 * overridden by an AVI infoframe. Apply a colorspace conversion to 1105 * squash 0-255 down to 16-235. The matrix here is: 1106 * 1107 * [ 0.8594 0 0 16] 1108 * [ 0 0.8594 0 16] 1109 * [ 0 0 0.8594 16] 1110 * 1111 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1112 */ 1113 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 1114 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 1115 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 1116 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 1117 }; 1118 1119 /* 1120 * Conversion between Full Range RGB and Full Range YUV422 using the 1121 * BT.709 Colorspace 1122 * 1123 * 1124 * [ 0.181906 0.611804 0.061758 16 ] 1125 * [ -0.100268 -0.337232 0.437500 128 ] 1126 * [ 0.437500 -0.397386 -0.040114 128 ] 1127 * 1128 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1129 */ 1130 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = { 1131 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1132 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1133 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1134 }; 1135 1136 /* 1137 * Conversion between Full Range RGB and Full Range YUV444 using the 1138 * BT.709 Colorspace 1139 * 1140 * [ -0.100268 -0.337232 0.437500 128 ] 1141 * [ 0.437500 -0.397386 -0.040114 128 ] 1142 * [ 0.181906 0.611804 0.061758 16 ] 1143 * 1144 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1145 */ 1146 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = { 1147 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1148 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1149 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1150 }; 1151 1152 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1153 const u16 coeffs[3][4]) 1154 { 1155 lockdep_assert_held(&vc4_hdmi->hw_lock); 1156 1157 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1158 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1159 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1160 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1161 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1162 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1163 } 1164 1165 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1166 struct drm_connector_state *state, 1167 const struct drm_display_mode *mode) 1168 { 1169 struct drm_device *drm = vc4_hdmi->connector.dev; 1170 struct vc4_hdmi_connector_state *vc4_state = 1171 conn_state_to_vc4_hdmi_conn_state(state); 1172 unsigned long flags; 1173 u32 if_cfg = 0; 1174 u32 if_xbar = 0x543210; 1175 u32 csc_chan_ctl = 0; 1176 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1177 VC5_MT_CP_CSC_CTL_MODE); 1178 int idx; 1179 1180 if (!drm_dev_enter(drm, &idx)) 1181 return; 1182 1183 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1184 1185 switch (vc4_state->output_format) { 1186 case VC4_HDMI_OUTPUT_YUV444: 1187 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709); 1188 break; 1189 1190 case VC4_HDMI_OUTPUT_YUV422: 1191 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1192 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1193 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1194 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1195 1196 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1197 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1198 1199 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1200 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1201 1202 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709); 1203 break; 1204 1205 case VC4_HDMI_OUTPUT_RGB: 1206 if_xbar = 0x354021; 1207 1208 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 1209 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 1210 else 1211 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 1212 break; 1213 1214 default: 1215 break; 1216 } 1217 1218 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1219 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1220 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1221 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1222 1223 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1224 1225 drm_dev_exit(idx); 1226 } 1227 1228 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1229 struct drm_connector_state *state, 1230 const struct drm_display_mode *mode) 1231 { 1232 struct drm_device *drm = vc4_hdmi->connector.dev; 1233 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1234 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1235 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1236 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1237 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1238 VC4_HDMI_VERTA_VSP) | 1239 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1240 VC4_HDMI_VERTA_VFP) | 1241 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1242 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1243 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1244 interlaced, 1245 VC4_HDMI_VERTB_VBP)); 1246 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1247 VC4_SET_FIELD(mode->crtc_vtotal - 1248 mode->crtc_vsync_end, 1249 VC4_HDMI_VERTB_VBP)); 1250 unsigned long flags; 1251 u32 reg; 1252 int idx; 1253 1254 if (!drm_dev_enter(drm, &idx)) 1255 return; 1256 1257 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1258 1259 HDMI_WRITE(HDMI_HORZA, 1260 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1261 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1262 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1263 VC4_HDMI_HORZA_HAP)); 1264 1265 HDMI_WRITE(HDMI_HORZB, 1266 VC4_SET_FIELD((mode->htotal - 1267 mode->hsync_end) * pixel_rep, 1268 VC4_HDMI_HORZB_HBP) | 1269 VC4_SET_FIELD((mode->hsync_end - 1270 mode->hsync_start) * pixel_rep, 1271 VC4_HDMI_HORZB_HSP) | 1272 VC4_SET_FIELD((mode->hsync_start - 1273 mode->hdisplay) * pixel_rep, 1274 VC4_HDMI_HORZB_HFP)); 1275 1276 HDMI_WRITE(HDMI_VERTA0, verta); 1277 HDMI_WRITE(HDMI_VERTA1, verta); 1278 1279 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1280 HDMI_WRITE(HDMI_VERTB1, vertb); 1281 1282 reg = HDMI_READ(HDMI_MISC_CONTROL); 1283 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1284 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1285 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1286 1287 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1288 1289 drm_dev_exit(idx); 1290 } 1291 1292 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1293 struct drm_connector_state *state, 1294 const struct drm_display_mode *mode) 1295 { 1296 struct drm_device *drm = vc4_hdmi->connector.dev; 1297 const struct vc4_hdmi_connector_state *vc4_state = 1298 conn_state_to_vc4_hdmi_conn_state(state); 1299 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1300 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1301 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1302 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1303 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1304 VC5_HDMI_VERTA_VSP) | 1305 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1306 VC5_HDMI_VERTA_VFP) | 1307 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1308 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1309 VC5_HDMI_VERTB_VSPO) | 1310 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1311 interlaced, 1312 VC4_HDMI_VERTB_VBP)); 1313 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1314 VC4_SET_FIELD(mode->crtc_vtotal - 1315 mode->crtc_vsync_end, 1316 VC4_HDMI_VERTB_VBP)); 1317 unsigned long flags; 1318 unsigned char gcp; 1319 bool gcp_en; 1320 u32 reg; 1321 int idx; 1322 1323 if (!drm_dev_enter(drm, &idx)) 1324 return; 1325 1326 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1327 1328 HDMI_WRITE(HDMI_HORZA, 1329 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1330 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1331 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1332 VC5_HDMI_HORZA_HAP) | 1333 VC4_SET_FIELD((mode->hsync_start - 1334 mode->hdisplay) * pixel_rep, 1335 VC5_HDMI_HORZA_HFP)); 1336 1337 HDMI_WRITE(HDMI_HORZB, 1338 VC4_SET_FIELD((mode->htotal - 1339 mode->hsync_end) * pixel_rep, 1340 VC5_HDMI_HORZB_HBP) | 1341 VC4_SET_FIELD((mode->hsync_end - 1342 mode->hsync_start) * pixel_rep, 1343 VC5_HDMI_HORZB_HSP)); 1344 1345 HDMI_WRITE(HDMI_VERTA0, verta); 1346 HDMI_WRITE(HDMI_VERTA1, verta); 1347 1348 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1349 HDMI_WRITE(HDMI_VERTB1, vertb); 1350 1351 switch (vc4_state->output_bpc) { 1352 case 12: 1353 gcp = 6; 1354 gcp_en = true; 1355 break; 1356 case 10: 1357 gcp = 5; 1358 gcp_en = true; 1359 break; 1360 case 8: 1361 default: 1362 gcp = 4; 1363 gcp_en = false; 1364 break; 1365 } 1366 1367 /* 1368 * YCC422 is always 36-bit and not considered deep colour so 1369 * doesn't signal in GCP. 1370 */ 1371 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) { 1372 gcp = 4; 1373 gcp_en = false; 1374 } 1375 1376 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1377 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1378 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1379 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1380 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1381 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1382 1383 reg = HDMI_READ(HDMI_GCP_WORD_1); 1384 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1385 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1386 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1387 1388 reg = HDMI_READ(HDMI_GCP_CONFIG); 1389 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1390 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 1391 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1392 1393 reg = HDMI_READ(HDMI_MISC_CONTROL); 1394 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1395 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1396 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1397 1398 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1399 1400 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1401 1402 drm_dev_exit(idx); 1403 } 1404 1405 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1406 { 1407 struct drm_device *drm = vc4_hdmi->connector.dev; 1408 unsigned long flags; 1409 u32 drift; 1410 int ret; 1411 int idx; 1412 1413 if (!drm_dev_enter(drm, &idx)) 1414 return; 1415 1416 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1417 1418 drift = HDMI_READ(HDMI_FIFO_CTL); 1419 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1420 1421 HDMI_WRITE(HDMI_FIFO_CTL, 1422 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1423 HDMI_WRITE(HDMI_FIFO_CTL, 1424 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1425 1426 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1427 1428 usleep_range(1000, 1100); 1429 1430 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1431 1432 HDMI_WRITE(HDMI_FIFO_CTL, 1433 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1434 HDMI_WRITE(HDMI_FIFO_CTL, 1435 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1436 1437 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1438 1439 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1440 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1441 WARN_ONCE(ret, "Timeout waiting for " 1442 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1443 1444 drm_dev_exit(idx); 1445 } 1446 1447 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1448 struct drm_atomic_state *state) 1449 { 1450 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1451 struct drm_device *drm = vc4_hdmi->connector.dev; 1452 struct drm_connector *connector = &vc4_hdmi->connector; 1453 struct drm_connector_state *conn_state = 1454 drm_atomic_get_new_connector_state(state, connector); 1455 struct vc4_hdmi_connector_state *vc4_conn_state = 1456 conn_state_to_vc4_hdmi_conn_state(conn_state); 1457 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1458 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate; 1459 unsigned long bvb_rate, hsm_rate; 1460 unsigned long flags; 1461 int ret; 1462 int idx; 1463 1464 mutex_lock(&vc4_hdmi->mutex); 1465 1466 if (!drm_dev_enter(drm, &idx)) 1467 goto out; 1468 1469 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1470 if (ret < 0) { 1471 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1472 goto err_dev_exit; 1473 } 1474 1475 /* 1476 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1477 * be faster than pixel clock, infinitesimally faster, tested in 1478 * simulation. Otherwise, exact value is unimportant for HDMI 1479 * operation." This conflicts with bcm2835's vc4 documentation, which 1480 * states HSM's clock has to be at least 108% of the pixel clock. 1481 * 1482 * Real life tests reveal that vc4's firmware statement holds up, and 1483 * users are able to use pixel clocks closer to HSM's, namely for 1484 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1485 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1486 * 162MHz. 1487 * 1488 * Additionally, the AXI clock needs to be at least 25% of 1489 * pixel clock, but HSM ends up being the limiting factor. 1490 */ 1491 hsm_rate = max_t(unsigned long, 1492 HSM_MIN_CLOCK_FREQ, 1493 (tmds_char_rate / 100) * 101); 1494 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1495 if (ret) { 1496 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1497 goto err_put_runtime_pm; 1498 } 1499 1500 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1501 if (ret) { 1502 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1503 goto err_put_runtime_pm; 1504 } 1505 1506 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1507 if (ret) { 1508 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1509 goto err_put_runtime_pm; 1510 } 1511 1512 1513 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1514 1515 if (tmds_char_rate > 297000000) 1516 bvb_rate = 300000000; 1517 else if (tmds_char_rate > 148500000) 1518 bvb_rate = 150000000; 1519 else 1520 bvb_rate = 75000000; 1521 1522 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1523 if (ret) { 1524 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1525 goto err_disable_pixel_clock; 1526 } 1527 1528 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1529 if (ret) { 1530 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1531 goto err_disable_pixel_clock; 1532 } 1533 1534 if (vc4_hdmi->variant->phy_init) 1535 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1536 1537 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1538 1539 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1540 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1541 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1542 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1543 1544 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1545 1546 if (vc4_hdmi->variant->set_timings) 1547 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1548 1549 drm_dev_exit(idx); 1550 1551 mutex_unlock(&vc4_hdmi->mutex); 1552 1553 return; 1554 1555 err_disable_pixel_clock: 1556 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1557 err_put_runtime_pm: 1558 pm_runtime_put(&vc4_hdmi->pdev->dev); 1559 err_dev_exit: 1560 drm_dev_exit(idx); 1561 out: 1562 mutex_unlock(&vc4_hdmi->mutex); 1563 return; 1564 } 1565 1566 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1567 struct drm_atomic_state *state) 1568 { 1569 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1570 struct drm_device *drm = vc4_hdmi->connector.dev; 1571 struct drm_connector *connector = &vc4_hdmi->connector; 1572 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1573 struct drm_connector_state *conn_state = 1574 drm_atomic_get_new_connector_state(state, connector); 1575 unsigned long flags; 1576 int idx; 1577 1578 mutex_lock(&vc4_hdmi->mutex); 1579 1580 if (!drm_dev_enter(drm, &idx)) 1581 goto out; 1582 1583 if (vc4_hdmi->variant->csc_setup) 1584 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1585 1586 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1587 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1588 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1589 1590 drm_dev_exit(idx); 1591 1592 out: 1593 mutex_unlock(&vc4_hdmi->mutex); 1594 } 1595 1596 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1597 struct drm_atomic_state *state) 1598 { 1599 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1600 struct drm_device *drm = vc4_hdmi->connector.dev; 1601 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1602 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1603 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1604 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1605 unsigned long flags; 1606 int ret; 1607 int idx; 1608 1609 mutex_lock(&vc4_hdmi->mutex); 1610 1611 if (!drm_dev_enter(drm, &idx)) 1612 goto out; 1613 1614 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1615 1616 HDMI_WRITE(HDMI_VID_CTL, 1617 VC4_HD_VID_CTL_ENABLE | 1618 VC4_HD_VID_CTL_CLRRGB | 1619 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1620 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1621 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1622 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1623 1624 HDMI_WRITE(HDMI_VID_CTL, 1625 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1626 1627 if (display->is_hdmi) { 1628 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1629 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1630 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1631 1632 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1633 1634 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1635 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1636 WARN_ONCE(ret, "Timeout waiting for " 1637 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1638 } else { 1639 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1640 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1641 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1642 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1643 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1644 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1645 1646 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1647 1648 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1649 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1650 WARN_ONCE(ret, "Timeout waiting for " 1651 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1652 } 1653 1654 if (display->is_hdmi) { 1655 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1656 1657 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1658 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1659 1660 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1661 VC4_HDMI_RAM_PACKET_ENABLE); 1662 1663 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1664 vc4_hdmi->packet_ram_enabled = true; 1665 1666 vc4_hdmi_set_infoframes(encoder); 1667 } 1668 1669 vc4_hdmi_recenter_fifo(vc4_hdmi); 1670 vc4_hdmi_enable_scrambling(encoder); 1671 1672 drm_dev_exit(idx); 1673 1674 out: 1675 mutex_unlock(&vc4_hdmi->mutex); 1676 } 1677 1678 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1679 struct drm_crtc_state *crtc_state, 1680 struct drm_connector_state *conn_state) 1681 { 1682 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1683 struct vc4_hdmi_connector_state *vc4_state = 1684 conn_state_to_vc4_hdmi_conn_state(conn_state); 1685 1686 mutex_lock(&vc4_hdmi->mutex); 1687 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1688 &crtc_state->adjusted_mode); 1689 vc4_hdmi->output_bpc = vc4_state->output_bpc; 1690 vc4_hdmi->output_format = vc4_state->output_format; 1691 mutex_unlock(&vc4_hdmi->mutex); 1692 } 1693 1694 static bool 1695 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi, 1696 const struct drm_display_info *info, 1697 const struct drm_display_mode *mode, 1698 unsigned int format, unsigned int bpc) 1699 { 1700 struct drm_device *dev = vc4_hdmi->connector.dev; 1701 u8 vic = drm_match_cea_mode(mode); 1702 1703 if (vic == 1 && bpc != 8) { 1704 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc); 1705 return false; 1706 } 1707 1708 if (!info->is_hdmi && 1709 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) { 1710 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n"); 1711 return false; 1712 } 1713 1714 switch (format) { 1715 case VC4_HDMI_OUTPUT_RGB: 1716 drm_dbg(dev, "RGB Format, checking the constraints.\n"); 1717 1718 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444)) 1719 return false; 1720 1721 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1722 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1723 return false; 1724 } 1725 1726 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1727 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1728 return false; 1729 } 1730 1731 drm_dbg(dev, "RGB format supported in that configuration.\n"); 1732 1733 return true; 1734 1735 case VC4_HDMI_OUTPUT_YUV422: 1736 drm_dbg(dev, "YUV422 format, checking the constraints.\n"); 1737 1738 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) { 1739 drm_dbg(dev, "Sink doesn't support YUV422.\n"); 1740 return false; 1741 } 1742 1743 if (bpc != 12) { 1744 drm_dbg(dev, "YUV422 only supports 12 bpc.\n"); 1745 return false; 1746 } 1747 1748 drm_dbg(dev, "YUV422 format supported in that configuration.\n"); 1749 1750 return true; 1751 1752 case VC4_HDMI_OUTPUT_YUV444: 1753 drm_dbg(dev, "YUV444 format, checking the constraints.\n"); 1754 1755 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) { 1756 drm_dbg(dev, "Sink doesn't support YUV444.\n"); 1757 return false; 1758 } 1759 1760 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1761 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1762 return false; 1763 } 1764 1765 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1766 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1767 return false; 1768 } 1769 1770 drm_dbg(dev, "YUV444 format supported in that configuration.\n"); 1771 1772 return true; 1773 } 1774 1775 return false; 1776 } 1777 1778 static enum drm_mode_status 1779 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, 1780 const struct drm_display_mode *mode, 1781 unsigned long long clock) 1782 { 1783 const struct drm_connector *connector = &vc4_hdmi->connector; 1784 const struct drm_display_info *info = &connector->display_info; 1785 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 1786 1787 if (clock > vc4_hdmi->variant->max_pixel_clock) 1788 return MODE_CLOCK_HIGH; 1789 1790 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 1791 return MODE_CLOCK_HIGH; 1792 1793 /* 4096x2160@60 is not reliable without overclocking core */ 1794 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 1795 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 1796 drm_mode_vrefresh(mode) >= 50) 1797 return MODE_CLOCK_HIGH; 1798 1799 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) 1800 return MODE_CLOCK_HIGH; 1801 1802 return MODE_OK; 1803 } 1804 1805 static unsigned long long 1806 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 1807 unsigned int bpc, 1808 enum vc4_hdmi_output_format fmt) 1809 { 1810 unsigned long long clock = mode->clock * 1000ULL; 1811 1812 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1813 clock = clock * 2; 1814 1815 if (fmt == VC4_HDMI_OUTPUT_YUV422) 1816 bpc = 8; 1817 1818 clock = clock * bpc; 1819 do_div(clock, 8); 1820 1821 return clock; 1822 } 1823 1824 static int 1825 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi, 1826 struct vc4_hdmi_connector_state *vc4_state, 1827 const struct drm_display_mode *mode, 1828 unsigned int bpc, unsigned int fmt) 1829 { 1830 unsigned long long clock; 1831 1832 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 1833 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK) 1834 return -EINVAL; 1835 1836 vc4_state->tmds_char_rate = clock; 1837 1838 return 0; 1839 } 1840 1841 static int 1842 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi, 1843 struct vc4_hdmi_connector_state *vc4_state, 1844 const struct drm_display_mode *mode, 1845 unsigned int bpc) 1846 { 1847 struct drm_device *dev = vc4_hdmi->connector.dev; 1848 const struct drm_connector *connector = &vc4_hdmi->connector; 1849 const struct drm_display_info *info = &connector->display_info; 1850 unsigned int format; 1851 1852 drm_dbg(dev, "Trying with an RGB output\n"); 1853 1854 format = VC4_HDMI_OUTPUT_RGB; 1855 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1856 int ret; 1857 1858 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1859 mode, bpc, format); 1860 if (!ret) { 1861 vc4_state->output_format = format; 1862 return 0; 1863 } 1864 } 1865 1866 drm_dbg(dev, "Failed, Trying with an YUV422 output\n"); 1867 1868 format = VC4_HDMI_OUTPUT_YUV422; 1869 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1870 int ret; 1871 1872 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1873 mode, bpc, format); 1874 if (!ret) { 1875 vc4_state->output_format = format; 1876 return 0; 1877 } 1878 } 1879 1880 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n"); 1881 1882 return -EINVAL; 1883 } 1884 1885 static int 1886 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi, 1887 struct vc4_hdmi_connector_state *vc4_state, 1888 const struct drm_display_mode *mode) 1889 { 1890 struct drm_device *dev = vc4_hdmi->connector.dev; 1891 struct drm_connector_state *conn_state = &vc4_state->base; 1892 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12); 1893 unsigned int bpc; 1894 int ret; 1895 1896 for (bpc = max_bpc; bpc >= 8; bpc -= 2) { 1897 drm_dbg(dev, "Trying with a %d bpc output\n", bpc); 1898 1899 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state, 1900 mode, bpc); 1901 if (ret) 1902 continue; 1903 1904 vc4_state->output_bpc = bpc; 1905 1906 drm_dbg(dev, 1907 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n", 1908 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 1909 vc4_state->output_bpc, 1910 vc4_hdmi_output_fmt_str(vc4_state->output_format), 1911 vc4_state->tmds_char_rate); 1912 1913 break; 1914 } 1915 1916 return ret; 1917 } 1918 1919 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1920 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1921 1922 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1923 struct drm_crtc_state *crtc_state, 1924 struct drm_connector_state *conn_state) 1925 { 1926 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1927 struct drm_connector *connector = &vc4_hdmi->connector; 1928 struct drm_connector_state *old_conn_state = 1929 drm_atomic_get_old_connector_state(conn_state->state, connector); 1930 struct vc4_hdmi_connector_state *old_vc4_state = 1931 conn_state_to_vc4_hdmi_conn_state(old_conn_state); 1932 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1933 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1934 unsigned long long tmds_char_rate = mode->clock * 1000; 1935 unsigned long long tmds_bit_rate; 1936 int ret; 1937 1938 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1939 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1940 /* Only try to fixup DBLCLK modes to get 480i and 576i 1941 * working. 1942 * A generic solution for all modes with odd horizontal 1943 * timing values seems impossible based on trying to 1944 * solve it for 1366x768 monitors. 1945 */ 1946 if ((mode->hsync_start - mode->hdisplay) & 1) 1947 mode->hsync_start--; 1948 if ((mode->hsync_end - mode->hsync_start) & 1) 1949 mode->hsync_end--; 1950 } 1951 1952 /* Now check whether we still have odd values remaining */ 1953 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1954 (mode->hsync_end % 2) || (mode->htotal % 2)) 1955 return -EINVAL; 1956 } 1957 1958 /* 1959 * The 1440p@60 pixel rate is in the same range than the first 1960 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1961 * bandwidth). Slightly lower the frequency to bring it out of 1962 * the WiFi range. 1963 */ 1964 tmds_bit_rate = tmds_char_rate * 10; 1965 if (vc4_hdmi->disable_wifi_frequencies && 1966 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1967 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1968 mode->clock = 238560; 1969 tmds_char_rate = mode->clock * 1000; 1970 } 1971 1972 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode); 1973 if (ret) 1974 return ret; 1975 1976 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */ 1977 if (vc4_state->output_bpc != old_vc4_state->output_bpc || 1978 vc4_state->output_format != old_vc4_state->output_format) 1979 crtc_state->mode_changed = true; 1980 1981 return 0; 1982 } 1983 1984 static enum drm_mode_status 1985 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1986 const struct drm_display_mode *mode) 1987 { 1988 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1989 1990 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1991 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1992 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1993 (mode->hsync_end % 2) || (mode->htotal % 2))) 1994 return MODE_H_ILLEGAL; 1995 1996 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000); 1997 } 1998 1999 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 2000 .atomic_check = vc4_hdmi_encoder_atomic_check, 2001 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 2002 .mode_valid = vc4_hdmi_encoder_mode_valid, 2003 }; 2004 2005 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 2006 { 2007 struct drm_device *drm = encoder->dev; 2008 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 2009 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2010 2011 drm_debugfs_add_file(drm, variant->debugfs_name, 2012 vc4_hdmi_debugfs_regs, vc4_hdmi); 2013 2014 return 0; 2015 } 2016 2017 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 2018 .late_register = vc4_hdmi_late_register, 2019 }; 2020 2021 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2022 { 2023 int i; 2024 u32 channel_map = 0; 2025 2026 for (i = 0; i < 8; i++) { 2027 if (channel_mask & BIT(i)) 2028 channel_map |= i << (3 * i); 2029 } 2030 return channel_map; 2031 } 2032 2033 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2034 { 2035 int i; 2036 u32 channel_map = 0; 2037 2038 for (i = 0; i < 8; i++) { 2039 if (channel_mask & BIT(i)) 2040 channel_map |= i << (4 * i); 2041 } 2042 return channel_map; 2043 } 2044 2045 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 2046 { 2047 struct drm_device *drm = vc4_hdmi->connector.dev; 2048 unsigned long flags; 2049 u32 hotplug; 2050 int idx; 2051 2052 if (!drm_dev_enter(drm, &idx)) 2053 return false; 2054 2055 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2056 hotplug = HDMI_READ(HDMI_HOTPLUG); 2057 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2058 2059 drm_dev_exit(idx); 2060 2061 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 2062 } 2063 2064 /* HDMI audio codec callbacks */ 2065 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 2066 unsigned int samplerate) 2067 { 2068 struct drm_device *drm = vc4_hdmi->connector.dev; 2069 u32 hsm_clock; 2070 unsigned long flags; 2071 unsigned long n, m; 2072 int idx; 2073 2074 if (!drm_dev_enter(drm, &idx)) 2075 return; 2076 2077 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 2078 rational_best_approximation(hsm_clock, samplerate, 2079 VC4_HD_MAI_SMP_N_MASK >> 2080 VC4_HD_MAI_SMP_N_SHIFT, 2081 (VC4_HD_MAI_SMP_M_MASK >> 2082 VC4_HD_MAI_SMP_M_SHIFT) + 1, 2083 &n, &m); 2084 2085 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2086 HDMI_WRITE(HDMI_MAI_SMP, 2087 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 2088 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 2089 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2090 2091 drm_dev_exit(idx); 2092 } 2093 2094 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 2095 { 2096 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 2097 u32 n, cts; 2098 u64 tmp; 2099 2100 lockdep_assert_held(&vc4_hdmi->mutex); 2101 lockdep_assert_held(&vc4_hdmi->hw_lock); 2102 2103 n = 128 * samplerate / 1000; 2104 tmp = (u64)(mode->clock * 1000) * n; 2105 do_div(tmp, 128 * samplerate); 2106 cts = tmp; 2107 2108 HDMI_WRITE(HDMI_CRP_CFG, 2109 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 2110 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 2111 2112 /* 2113 * We could get slightly more accurate clocks in some cases by 2114 * providing a CTS_1 value. The two CTS values are alternated 2115 * between based on the period fields 2116 */ 2117 HDMI_WRITE(HDMI_CTS_0, cts); 2118 HDMI_WRITE(HDMI_CTS_1, cts); 2119 } 2120 2121 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 2122 { 2123 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 2124 2125 return snd_soc_card_get_drvdata(card); 2126 } 2127 2128 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 2129 { 2130 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 2131 2132 lockdep_assert_held(&vc4_hdmi->mutex); 2133 2134 /* 2135 * If the encoder is currently in DVI mode, treat the codec DAI 2136 * as missing. 2137 */ 2138 if (!display->is_hdmi) 2139 return false; 2140 2141 return true; 2142 } 2143 2144 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 2145 { 2146 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2147 struct drm_device *drm = vc4_hdmi->connector.dev; 2148 unsigned long flags; 2149 int ret = 0; 2150 int idx; 2151 2152 mutex_lock(&vc4_hdmi->mutex); 2153 2154 if (!drm_dev_enter(drm, &idx)) { 2155 ret = -ENODEV; 2156 goto out; 2157 } 2158 2159 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2160 ret = -ENODEV; 2161 goto out_dev_exit; 2162 } 2163 2164 vc4_hdmi->audio.streaming = true; 2165 2166 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2167 HDMI_WRITE(HDMI_MAI_CTL, 2168 VC4_HD_MAI_CTL_RESET | 2169 VC4_HD_MAI_CTL_FLUSH | 2170 VC4_HD_MAI_CTL_DLATE | 2171 VC4_HD_MAI_CTL_ERRORE | 2172 VC4_HD_MAI_CTL_ERRORF); 2173 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2174 2175 if (vc4_hdmi->variant->phy_rng_enable) 2176 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 2177 2178 out_dev_exit: 2179 drm_dev_exit(idx); 2180 out: 2181 mutex_unlock(&vc4_hdmi->mutex); 2182 2183 return ret; 2184 } 2185 2186 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 2187 { 2188 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2189 struct device *dev = &vc4_hdmi->pdev->dev; 2190 unsigned long flags; 2191 int ret; 2192 2193 lockdep_assert_held(&vc4_hdmi->mutex); 2194 2195 vc4_hdmi->audio.streaming = false; 2196 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 2197 if (ret) 2198 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 2199 2200 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2201 2202 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 2203 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 2204 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 2205 2206 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2207 } 2208 2209 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 2210 { 2211 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2212 struct drm_device *drm = vc4_hdmi->connector.dev; 2213 unsigned long flags; 2214 int idx; 2215 2216 mutex_lock(&vc4_hdmi->mutex); 2217 2218 if (!drm_dev_enter(drm, &idx)) 2219 goto out; 2220 2221 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2222 2223 HDMI_WRITE(HDMI_MAI_CTL, 2224 VC4_HD_MAI_CTL_DLATE | 2225 VC4_HD_MAI_CTL_ERRORE | 2226 VC4_HD_MAI_CTL_ERRORF); 2227 2228 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2229 2230 if (vc4_hdmi->variant->phy_rng_disable) 2231 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 2232 2233 vc4_hdmi->audio.streaming = false; 2234 vc4_hdmi_audio_reset(vc4_hdmi); 2235 2236 drm_dev_exit(idx); 2237 2238 out: 2239 mutex_unlock(&vc4_hdmi->mutex); 2240 } 2241 2242 static int sample_rate_to_mai_fmt(int samplerate) 2243 { 2244 switch (samplerate) { 2245 case 8000: 2246 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2247 case 11025: 2248 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2249 case 12000: 2250 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2251 case 16000: 2252 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2253 case 22050: 2254 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2255 case 24000: 2256 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2257 case 32000: 2258 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2259 case 44100: 2260 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2261 case 48000: 2262 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2263 case 64000: 2264 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2265 case 88200: 2266 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2267 case 96000: 2268 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2269 case 128000: 2270 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2271 case 176400: 2272 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2273 case 192000: 2274 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2275 default: 2276 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2277 } 2278 } 2279 2280 /* HDMI audio codec callbacks */ 2281 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 2282 struct hdmi_codec_daifmt *daifmt, 2283 struct hdmi_codec_params *params) 2284 { 2285 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2286 struct drm_device *drm = vc4_hdmi->connector.dev; 2287 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2288 unsigned int sample_rate = params->sample_rate; 2289 unsigned int channels = params->channels; 2290 unsigned long flags; 2291 u32 audio_packet_config, channel_mask; 2292 u32 channel_map; 2293 u32 mai_audio_format; 2294 u32 mai_sample_rate; 2295 int ret = 0; 2296 int idx; 2297 2298 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2299 sample_rate, params->sample_width, channels); 2300 2301 mutex_lock(&vc4_hdmi->mutex); 2302 2303 if (!drm_dev_enter(drm, &idx)) { 2304 ret = -ENODEV; 2305 goto out; 2306 } 2307 2308 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2309 ret = -EINVAL; 2310 goto out_dev_exit; 2311 } 2312 2313 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2314 2315 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2316 HDMI_WRITE(HDMI_MAI_CTL, 2317 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2318 VC4_HD_MAI_CTL_WHOLSMP | 2319 VC4_HD_MAI_CTL_CHALIGN | 2320 VC4_HD_MAI_CTL_ENABLE); 2321 2322 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2323 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2324 params->channels == 8) 2325 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2326 else 2327 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2328 HDMI_WRITE(HDMI_MAI_FMT, 2329 VC4_SET_FIELD(mai_sample_rate, 2330 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2331 VC4_SET_FIELD(mai_audio_format, 2332 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2333 2334 /* The B frame identifier should match the value used by alsa-lib (8) */ 2335 audio_packet_config = 2336 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2337 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2338 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2339 2340 channel_mask = GENMASK(channels - 1, 0); 2341 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2342 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2343 2344 /* Set the MAI threshold */ 2345 HDMI_WRITE(HDMI_MAI_THR, 2346 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) | 2347 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) | 2348 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) | 2349 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW)); 2350 2351 HDMI_WRITE(HDMI_MAI_CONFIG, 2352 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2353 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2354 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2355 2356 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2357 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2358 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2359 2360 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2361 2362 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2363 2364 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 2365 vc4_hdmi_set_audio_infoframe(encoder); 2366 2367 out_dev_exit: 2368 drm_dev_exit(idx); 2369 out: 2370 mutex_unlock(&vc4_hdmi->mutex); 2371 2372 return ret; 2373 } 2374 2375 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2376 .name = "vc4-hdmi-cpu-dai-component", 2377 .legacy_dai_naming = 1, 2378 }; 2379 2380 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2381 { 2382 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2383 2384 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2385 2386 return 0; 2387 } 2388 2389 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2390 .name = "vc4-hdmi-cpu-dai", 2391 .probe = vc4_hdmi_audio_cpu_dai_probe, 2392 .playback = { 2393 .stream_name = "Playback", 2394 .channels_min = 1, 2395 .channels_max = 8, 2396 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2397 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2398 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2399 SNDRV_PCM_RATE_192000, 2400 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2401 }, 2402 }; 2403 2404 static const struct snd_dmaengine_pcm_config pcm_conf = { 2405 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2406 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2407 }; 2408 2409 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2410 uint8_t *buf, size_t len) 2411 { 2412 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2413 struct drm_connector *connector = &vc4_hdmi->connector; 2414 2415 mutex_lock(&vc4_hdmi->mutex); 2416 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2417 mutex_unlock(&vc4_hdmi->mutex); 2418 2419 return 0; 2420 } 2421 2422 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2423 .get_eld = vc4_hdmi_audio_get_eld, 2424 .prepare = vc4_hdmi_audio_prepare, 2425 .audio_shutdown = vc4_hdmi_audio_shutdown, 2426 .audio_startup = vc4_hdmi_audio_startup, 2427 }; 2428 2429 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2430 .ops = &vc4_hdmi_codec_ops, 2431 .max_i2s_channels = 8, 2432 .i2s = 1, 2433 }; 2434 2435 static void vc4_hdmi_audio_codec_release(void *ptr) 2436 { 2437 struct vc4_hdmi *vc4_hdmi = ptr; 2438 2439 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 2440 vc4_hdmi->audio.codec_pdev = NULL; 2441 } 2442 2443 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2444 { 2445 const struct vc4_hdmi_register *mai_data = 2446 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2447 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2448 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2449 struct device *dev = &vc4_hdmi->pdev->dev; 2450 struct platform_device *codec_pdev; 2451 const __be32 *addr; 2452 int index, len; 2453 int ret; 2454 2455 /* 2456 * ASoC makes it a bit hard to retrieve a pointer to the 2457 * vc4_hdmi structure. Registering the card will overwrite our 2458 * device drvdata with a pointer to the snd_soc_card structure, 2459 * which can then be used to retrieve whatever drvdata we want 2460 * to associate. 2461 * 2462 * However, that doesn't fly in the case where we wouldn't 2463 * register an ASoC card (because of an old DT that is missing 2464 * the dmas properties for example), then the card isn't 2465 * registered and the device drvdata wouldn't be set. 2466 * 2467 * We can deal with both cases by making sure a snd_soc_card 2468 * pointer and a vc4_hdmi structure are pointing to the same 2469 * memory address, so we can treat them indistinctly without any 2470 * issue. 2471 */ 2472 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2473 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2474 2475 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2476 dev_warn(dev, 2477 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2478 return 0; 2479 } 2480 2481 if (mai_data->reg != VC4_HD) { 2482 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2483 return -EINVAL; 2484 } 2485 2486 /* 2487 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2488 * the bus address specified in the DT, because the physical address 2489 * (the one returned by platform_get_resource()) is not appropriate 2490 * for DMA transfers. 2491 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2492 */ 2493 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2494 /* Before BCM2711, we don't have a named register range */ 2495 if (index < 0) 2496 index = 1; 2497 2498 addr = of_get_address(dev->of_node, index, NULL, NULL); 2499 2500 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2501 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2502 vc4_hdmi->audio.dma_data.maxburst = 2; 2503 2504 /* 2505 * NOTE: Strictly speaking, we should probably use a DRM-managed 2506 * registration there to avoid removing all the audio components 2507 * by the time the driver doesn't have any user anymore. 2508 * 2509 * However, the ASoC core uses a number of devm_kzalloc calls 2510 * when registering, even when using non-device-managed 2511 * functions (such as in snd_soc_register_component()). 2512 * 2513 * If we call snd_soc_unregister_component() in a DRM-managed 2514 * action, the device-managed actions have already been executed 2515 * and thus we would access memory that has been freed. 2516 * 2517 * Using device-managed hooks here probably leaves us open to a 2518 * bunch of issues if userspace still has a handle on the ALSA 2519 * device when the device is removed. However, this is mitigated 2520 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2521 * path to prevent the access to the device resources if it 2522 * isn't there anymore. 2523 * 2524 * Then, the vc4_hdmi structure is DRM-managed and thus only 2525 * freed whenever the last user has closed the DRM device file. 2526 * It should thus outlive ALSA in most situations. 2527 */ 2528 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2529 if (ret) { 2530 dev_err(dev, "Could not register PCM component: %d\n", ret); 2531 return ret; 2532 } 2533 2534 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2535 &vc4_hdmi_audio_cpu_dai_drv, 1); 2536 if (ret) { 2537 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2538 return ret; 2539 } 2540 2541 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2542 PLATFORM_DEVID_AUTO, 2543 &vc4_hdmi_codec_pdata, 2544 sizeof(vc4_hdmi_codec_pdata)); 2545 if (IS_ERR(codec_pdev)) { 2546 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2547 return PTR_ERR(codec_pdev); 2548 } 2549 vc4_hdmi->audio.codec_pdev = codec_pdev; 2550 2551 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi); 2552 if (ret) 2553 return ret; 2554 2555 dai_link->cpus = &vc4_hdmi->audio.cpu; 2556 dai_link->codecs = &vc4_hdmi->audio.codec; 2557 dai_link->platforms = &vc4_hdmi->audio.platform; 2558 2559 dai_link->num_cpus = 1; 2560 dai_link->num_codecs = 1; 2561 dai_link->num_platforms = 1; 2562 2563 dai_link->name = "MAI"; 2564 dai_link->stream_name = "MAI PCM"; 2565 dai_link->codecs->dai_name = "i2s-hifi"; 2566 dai_link->cpus->dai_name = dev_name(dev); 2567 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2568 dai_link->platforms->name = dev_name(dev); 2569 2570 card->dai_link = dai_link; 2571 card->num_links = 1; 2572 card->name = vc4_hdmi->variant->card_name; 2573 card->driver_name = "vc4-hdmi"; 2574 card->dev = dev; 2575 card->owner = THIS_MODULE; 2576 2577 /* 2578 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2579 * stores a pointer to the snd card object in dev->driver_data. This 2580 * means we cannot use it for something else. The hdmi back-pointer is 2581 * now stored in card->drvdata and should be retrieved with 2582 * snd_soc_card_get_drvdata() if needed. 2583 */ 2584 snd_soc_card_set_drvdata(card, vc4_hdmi); 2585 ret = devm_snd_soc_register_card(dev, card); 2586 if (ret) 2587 dev_err_probe(dev, ret, "Could not register sound card\n"); 2588 2589 return ret; 2590 2591 } 2592 2593 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2594 { 2595 struct vc4_hdmi *vc4_hdmi = priv; 2596 struct drm_connector *connector = &vc4_hdmi->connector; 2597 struct drm_device *dev = connector->dev; 2598 2599 if (dev && dev->registered) 2600 drm_connector_helper_hpd_irq_event(connector); 2601 2602 return IRQ_HANDLED; 2603 } 2604 2605 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2606 { 2607 struct drm_connector *connector = &vc4_hdmi->connector; 2608 struct platform_device *pdev = vc4_hdmi->pdev; 2609 int ret; 2610 2611 if (vc4_hdmi->variant->external_irq_controller) { 2612 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2613 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2614 2615 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2616 NULL, 2617 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2618 "vc4 hdmi hpd connected", vc4_hdmi); 2619 if (ret) 2620 return ret; 2621 2622 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2623 NULL, 2624 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2625 "vc4 hdmi hpd disconnected", vc4_hdmi); 2626 if (ret) 2627 return ret; 2628 2629 connector->polled = DRM_CONNECTOR_POLL_HPD; 2630 } 2631 2632 return 0; 2633 } 2634 2635 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2636 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2637 { 2638 struct vc4_hdmi *vc4_hdmi = priv; 2639 2640 if (vc4_hdmi->cec_rx_msg.len) 2641 cec_received_msg(vc4_hdmi->cec_adap, 2642 &vc4_hdmi->cec_rx_msg); 2643 2644 return IRQ_HANDLED; 2645 } 2646 2647 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2648 { 2649 struct vc4_hdmi *vc4_hdmi = priv; 2650 2651 if (vc4_hdmi->cec_tx_ok) { 2652 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2653 0, 0, 0, 0); 2654 } else { 2655 /* 2656 * This CEC implementation makes 1 retry, so if we 2657 * get a NACK, then that means it made 2 attempts. 2658 */ 2659 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2660 0, 2, 0, 0); 2661 } 2662 return IRQ_HANDLED; 2663 } 2664 2665 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2666 { 2667 struct vc4_hdmi *vc4_hdmi = priv; 2668 irqreturn_t ret; 2669 2670 if (vc4_hdmi->cec_irq_was_rx) 2671 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2672 else 2673 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2674 2675 return ret; 2676 } 2677 2678 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2679 { 2680 struct drm_device *dev = vc4_hdmi->connector.dev; 2681 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2682 unsigned int i; 2683 2684 lockdep_assert_held(&vc4_hdmi->hw_lock); 2685 2686 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2687 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2688 2689 if (msg->len > 16) { 2690 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2691 return; 2692 } 2693 2694 for (i = 0; i < msg->len; i += 4) { 2695 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2696 2697 msg->msg[i] = val & 0xff; 2698 msg->msg[i + 1] = (val >> 8) & 0xff; 2699 msg->msg[i + 2] = (val >> 16) & 0xff; 2700 msg->msg[i + 3] = (val >> 24) & 0xff; 2701 } 2702 } 2703 2704 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2705 { 2706 u32 cntrl1; 2707 2708 /* 2709 * We don't need to protect the register access using 2710 * drm_dev_enter() there because the interrupt handler lifetime 2711 * is tied to the device itself, and not to the DRM device. 2712 * 2713 * So when the device will be gone, one of the first thing we 2714 * will be doing will be to unregister the interrupt handler, 2715 * and then unregister the DRM device. drm_dev_enter() would 2716 * thus always succeed if we are here. 2717 */ 2718 2719 lockdep_assert_held(&vc4_hdmi->hw_lock); 2720 2721 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2722 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2723 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2724 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2725 2726 return IRQ_WAKE_THREAD; 2727 } 2728 2729 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2730 { 2731 struct vc4_hdmi *vc4_hdmi = priv; 2732 irqreturn_t ret; 2733 2734 spin_lock(&vc4_hdmi->hw_lock); 2735 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2736 spin_unlock(&vc4_hdmi->hw_lock); 2737 2738 return ret; 2739 } 2740 2741 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2742 { 2743 u32 cntrl1; 2744 2745 lockdep_assert_held(&vc4_hdmi->hw_lock); 2746 2747 /* 2748 * We don't need to protect the register access using 2749 * drm_dev_enter() there because the interrupt handler lifetime 2750 * is tied to the device itself, and not to the DRM device. 2751 * 2752 * So when the device will be gone, one of the first thing we 2753 * will be doing will be to unregister the interrupt handler, 2754 * and then unregister the DRM device. drm_dev_enter() would 2755 * thus always succeed if we are here. 2756 */ 2757 2758 vc4_hdmi->cec_rx_msg.len = 0; 2759 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2760 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2761 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2762 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2763 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2764 2765 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2766 2767 return IRQ_WAKE_THREAD; 2768 } 2769 2770 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2771 { 2772 struct vc4_hdmi *vc4_hdmi = priv; 2773 irqreturn_t ret; 2774 2775 spin_lock(&vc4_hdmi->hw_lock); 2776 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2777 spin_unlock(&vc4_hdmi->hw_lock); 2778 2779 return ret; 2780 } 2781 2782 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2783 { 2784 struct vc4_hdmi *vc4_hdmi = priv; 2785 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2786 irqreturn_t ret; 2787 u32 cntrl5; 2788 2789 /* 2790 * We don't need to protect the register access using 2791 * drm_dev_enter() there because the interrupt handler lifetime 2792 * is tied to the device itself, and not to the DRM device. 2793 * 2794 * So when the device will be gone, one of the first thing we 2795 * will be doing will be to unregister the interrupt handler, 2796 * and then unregister the DRM device. drm_dev_enter() would 2797 * thus always succeed if we are here. 2798 */ 2799 2800 if (!(stat & VC4_HDMI_CPU_CEC)) 2801 return IRQ_NONE; 2802 2803 spin_lock(&vc4_hdmi->hw_lock); 2804 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2805 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2806 if (vc4_hdmi->cec_irq_was_rx) 2807 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2808 else 2809 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2810 2811 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2812 spin_unlock(&vc4_hdmi->hw_lock); 2813 2814 return ret; 2815 } 2816 2817 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2818 { 2819 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2820 struct drm_device *drm = vc4_hdmi->connector.dev; 2821 /* clock period in microseconds */ 2822 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2823 unsigned long flags; 2824 u32 val; 2825 int ret; 2826 int idx; 2827 2828 if (!drm_dev_enter(drm, &idx)) 2829 /* 2830 * We can't return an error code, because the CEC 2831 * framework will emit WARN_ON messages at unbind 2832 * otherwise. 2833 */ 2834 return 0; 2835 2836 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2837 if (ret) { 2838 drm_dev_exit(idx); 2839 return ret; 2840 } 2841 2842 mutex_lock(&vc4_hdmi->mutex); 2843 2844 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2845 2846 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2847 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2848 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2849 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2850 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2851 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2852 2853 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2854 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2855 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2856 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2857 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2858 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2859 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2860 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2861 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2862 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2863 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2864 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2865 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2866 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2867 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2868 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2869 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2870 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2871 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2872 2873 if (!vc4_hdmi->variant->external_irq_controller) 2874 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2875 2876 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2877 2878 mutex_unlock(&vc4_hdmi->mutex); 2879 drm_dev_exit(idx); 2880 2881 return 0; 2882 } 2883 2884 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2885 { 2886 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2887 struct drm_device *drm = vc4_hdmi->connector.dev; 2888 unsigned long flags; 2889 int idx; 2890 2891 if (!drm_dev_enter(drm, &idx)) 2892 /* 2893 * We can't return an error code, because the CEC 2894 * framework will emit WARN_ON messages at unbind 2895 * otherwise. 2896 */ 2897 return 0; 2898 2899 mutex_lock(&vc4_hdmi->mutex); 2900 2901 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2902 2903 if (!vc4_hdmi->variant->external_irq_controller) 2904 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2905 2906 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2907 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2908 2909 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2910 2911 mutex_unlock(&vc4_hdmi->mutex); 2912 2913 pm_runtime_put(&vc4_hdmi->pdev->dev); 2914 2915 drm_dev_exit(idx); 2916 2917 return 0; 2918 } 2919 2920 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2921 { 2922 if (enable) 2923 return vc4_hdmi_cec_enable(adap); 2924 else 2925 return vc4_hdmi_cec_disable(adap); 2926 } 2927 2928 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2929 { 2930 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2931 struct drm_device *drm = vc4_hdmi->connector.dev; 2932 unsigned long flags; 2933 int idx; 2934 2935 if (!drm_dev_enter(drm, &idx)) 2936 /* 2937 * We can't return an error code, because the CEC 2938 * framework will emit WARN_ON messages at unbind 2939 * otherwise. 2940 */ 2941 return 0; 2942 2943 mutex_lock(&vc4_hdmi->mutex); 2944 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2945 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2946 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2947 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2948 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2949 mutex_unlock(&vc4_hdmi->mutex); 2950 2951 drm_dev_exit(idx); 2952 2953 return 0; 2954 } 2955 2956 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2957 u32 signal_free_time, struct cec_msg *msg) 2958 { 2959 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2960 struct drm_device *dev = vc4_hdmi->connector.dev; 2961 unsigned long flags; 2962 u32 val; 2963 unsigned int i; 2964 int idx; 2965 2966 if (!drm_dev_enter(dev, &idx)) 2967 return -ENODEV; 2968 2969 if (msg->len > 16) { 2970 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2971 drm_dev_exit(idx); 2972 return -ENOMEM; 2973 } 2974 2975 mutex_lock(&vc4_hdmi->mutex); 2976 2977 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2978 2979 for (i = 0; i < msg->len; i += 4) 2980 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2981 (msg->msg[i]) | 2982 (msg->msg[i + 1] << 8) | 2983 (msg->msg[i + 2] << 16) | 2984 (msg->msg[i + 3] << 24)); 2985 2986 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2987 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2988 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2989 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2990 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2991 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2992 2993 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2994 2995 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2996 mutex_unlock(&vc4_hdmi->mutex); 2997 drm_dev_exit(idx); 2998 2999 return 0; 3000 } 3001 3002 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 3003 .adap_enable = vc4_hdmi_cec_adap_enable, 3004 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 3005 .adap_transmit = vc4_hdmi_cec_adap_transmit, 3006 }; 3007 3008 static void vc4_hdmi_cec_release(void *ptr) 3009 { 3010 struct vc4_hdmi *vc4_hdmi = ptr; 3011 3012 cec_unregister_adapter(vc4_hdmi->cec_adap); 3013 vc4_hdmi->cec_adap = NULL; 3014 } 3015 3016 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3017 { 3018 struct cec_connector_info conn_info; 3019 struct platform_device *pdev = vc4_hdmi->pdev; 3020 struct device *dev = &pdev->dev; 3021 int ret; 3022 3023 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 3024 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 3025 return 0; 3026 } 3027 3028 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 3029 vc4_hdmi, "vc4", 3030 CEC_CAP_DEFAULTS | 3031 CEC_CAP_CONNECTOR_INFO, 1); 3032 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 3033 if (ret < 0) 3034 return ret; 3035 3036 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 3037 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 3038 3039 if (vc4_hdmi->variant->external_irq_controller) { 3040 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 3041 vc4_cec_irq_handler_rx_bare, 3042 vc4_cec_irq_handler_rx_thread, 0, 3043 "vc4 hdmi cec rx", vc4_hdmi); 3044 if (ret) 3045 goto err_delete_cec_adap; 3046 3047 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 3048 vc4_cec_irq_handler_tx_bare, 3049 vc4_cec_irq_handler_tx_thread, 0, 3050 "vc4 hdmi cec tx", vc4_hdmi); 3051 if (ret) 3052 goto err_delete_cec_adap; 3053 } else { 3054 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 3055 vc4_cec_irq_handler, 3056 vc4_cec_irq_handler_thread, 0, 3057 "vc4 hdmi cec", vc4_hdmi); 3058 if (ret) 3059 goto err_delete_cec_adap; 3060 } 3061 3062 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 3063 if (ret < 0) 3064 goto err_delete_cec_adap; 3065 3066 /* 3067 * NOTE: Strictly speaking, we should probably use a DRM-managed 3068 * registration there to avoid removing the CEC adapter by the 3069 * time the DRM driver doesn't have any user anymore. 3070 * 3071 * However, the CEC framework already cleans up the CEC adapter 3072 * only when the last user has closed its file descriptor, so we 3073 * don't need to handle it in DRM. 3074 * 3075 * By the time the device-managed hook is executed, we will give 3076 * up our reference to the CEC adapter and therefore don't 3077 * really care when it's actually freed. 3078 * 3079 * There's still a problematic sequence: if we unregister our 3080 * CEC adapter, but the userspace keeps a handle on the CEC 3081 * adapter but not the DRM device for some reason. In such a 3082 * case, our vc4_hdmi structure will be freed, but the 3083 * cec_adapter structure will have a dangling pointer to what 3084 * used to be our HDMI controller. If we get a CEC call at that 3085 * moment, we could end up with a use-after-free. Fortunately, 3086 * the CEC framework already handles this too, by calling 3087 * cec_is_registered() in cec_ioctl() and cec_poll(). 3088 */ 3089 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi); 3090 if (ret) 3091 return ret; 3092 3093 return 0; 3094 3095 err_delete_cec_adap: 3096 cec_delete_adapter(vc4_hdmi->cec_adap); 3097 3098 return ret; 3099 } 3100 #else 3101 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3102 { 3103 return 0; 3104 } 3105 #endif 3106 3107 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 3108 { 3109 struct debugfs_reg32 *regs = ptr; 3110 3111 kfree(regs); 3112 } 3113 3114 static int vc4_hdmi_build_regset(struct drm_device *drm, 3115 struct vc4_hdmi *vc4_hdmi, 3116 struct debugfs_regset32 *regset, 3117 enum vc4_hdmi_regs reg) 3118 { 3119 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 3120 struct debugfs_reg32 *regs, *new_regs; 3121 unsigned int count = 0; 3122 unsigned int i; 3123 int ret; 3124 3125 regs = kcalloc(variant->num_registers, sizeof(*regs), 3126 GFP_KERNEL); 3127 if (!regs) 3128 return -ENOMEM; 3129 3130 for (i = 0; i < variant->num_registers; i++) { 3131 const struct vc4_hdmi_register *field = &variant->registers[i]; 3132 3133 if (field->reg != reg) 3134 continue; 3135 3136 regs[count].name = field->name; 3137 regs[count].offset = field->offset; 3138 count++; 3139 } 3140 3141 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 3142 if (!new_regs) 3143 return -ENOMEM; 3144 3145 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 3146 regset->regs = new_regs; 3147 regset->nregs = count; 3148 3149 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 3150 if (ret) 3151 return ret; 3152 3153 return 0; 3154 } 3155 3156 static int vc4_hdmi_init_resources(struct drm_device *drm, 3157 struct vc4_hdmi *vc4_hdmi) 3158 { 3159 struct platform_device *pdev = vc4_hdmi->pdev; 3160 struct device *dev = &pdev->dev; 3161 int ret; 3162 3163 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 3164 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 3165 return PTR_ERR(vc4_hdmi->hdmicore_regs); 3166 3167 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 3168 if (IS_ERR(vc4_hdmi->hd_regs)) 3169 return PTR_ERR(vc4_hdmi->hd_regs); 3170 3171 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3172 if (ret) 3173 return ret; 3174 3175 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3176 if (ret) 3177 return ret; 3178 3179 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 3180 if (IS_ERR(vc4_hdmi->pixel_clock)) { 3181 ret = PTR_ERR(vc4_hdmi->pixel_clock); 3182 if (ret != -EPROBE_DEFER) 3183 DRM_ERROR("Failed to get pixel clock\n"); 3184 return ret; 3185 } 3186 3187 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3188 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3189 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3190 return PTR_ERR(vc4_hdmi->hsm_clock); 3191 } 3192 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 3193 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 3194 3195 return 0; 3196 } 3197 3198 static int vc5_hdmi_init_resources(struct drm_device *drm, 3199 struct vc4_hdmi *vc4_hdmi) 3200 { 3201 struct platform_device *pdev = vc4_hdmi->pdev; 3202 struct device *dev = &pdev->dev; 3203 struct resource *res; 3204 int ret; 3205 3206 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 3207 if (!res) 3208 return -ENODEV; 3209 3210 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 3211 resource_size(res)); 3212 if (!vc4_hdmi->hdmicore_regs) 3213 return -ENOMEM; 3214 3215 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 3216 if (!res) 3217 return -ENODEV; 3218 3219 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 3220 if (!vc4_hdmi->hd_regs) 3221 return -ENOMEM; 3222 3223 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 3224 if (!res) 3225 return -ENODEV; 3226 3227 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 3228 if (!vc4_hdmi->cec_regs) 3229 return -ENOMEM; 3230 3231 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 3232 if (!res) 3233 return -ENODEV; 3234 3235 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 3236 if (!vc4_hdmi->csc_regs) 3237 return -ENOMEM; 3238 3239 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 3240 if (!res) 3241 return -ENODEV; 3242 3243 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 3244 if (!vc4_hdmi->dvp_regs) 3245 return -ENOMEM; 3246 3247 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 3248 if (!res) 3249 return -ENODEV; 3250 3251 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 3252 if (!vc4_hdmi->phy_regs) 3253 return -ENOMEM; 3254 3255 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 3256 if (!res) 3257 return -ENODEV; 3258 3259 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 3260 if (!vc4_hdmi->ram_regs) 3261 return -ENOMEM; 3262 3263 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 3264 if (!res) 3265 return -ENODEV; 3266 3267 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 3268 if (!vc4_hdmi->rm_regs) 3269 return -ENOMEM; 3270 3271 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3272 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3273 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3274 return PTR_ERR(vc4_hdmi->hsm_clock); 3275 } 3276 3277 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3278 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3279 DRM_ERROR("Failed to get pixel bvb clock\n"); 3280 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3281 } 3282 3283 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3284 if (IS_ERR(vc4_hdmi->audio_clock)) { 3285 DRM_ERROR("Failed to get audio clock\n"); 3286 return PTR_ERR(vc4_hdmi->audio_clock); 3287 } 3288 3289 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3290 if (IS_ERR(vc4_hdmi->cec_clock)) { 3291 DRM_ERROR("Failed to get CEC clock\n"); 3292 return PTR_ERR(vc4_hdmi->cec_clock); 3293 } 3294 3295 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3296 if (IS_ERR(vc4_hdmi->reset)) { 3297 DRM_ERROR("Failed to get HDMI reset line\n"); 3298 return PTR_ERR(vc4_hdmi->reset); 3299 } 3300 3301 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3302 if (ret) 3303 return ret; 3304 3305 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3306 if (ret) 3307 return ret; 3308 3309 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3310 if (ret) 3311 return ret; 3312 3313 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3314 if (ret) 3315 return ret; 3316 3317 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3318 if (ret) 3319 return ret; 3320 3321 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3322 if (ret) 3323 return ret; 3324 3325 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3326 if (ret) 3327 return ret; 3328 3329 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3330 if (ret) 3331 return ret; 3332 3333 return 0; 3334 } 3335 3336 static int vc4_hdmi_runtime_suspend(struct device *dev) 3337 { 3338 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3339 3340 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3341 3342 return 0; 3343 } 3344 3345 static int vc4_hdmi_runtime_resume(struct device *dev) 3346 { 3347 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3348 unsigned long __maybe_unused flags; 3349 u32 __maybe_unused value; 3350 unsigned long rate; 3351 int ret; 3352 3353 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3354 if (ret) 3355 return ret; 3356 3357 /* 3358 * Whenever the RaspberryPi boots without an HDMI monitor 3359 * plugged in, the firmware won't have initialized the HSM clock 3360 * rate and it will be reported as 0. 3361 * 3362 * If we try to access a register of the controller in such a 3363 * case, it will lead to a silent CPU stall. Let's make sure we 3364 * prevent such a case. 3365 */ 3366 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3367 if (!rate) { 3368 ret = -EINVAL; 3369 goto err_disable_clk; 3370 } 3371 3372 if (vc4_hdmi->variant->reset) 3373 vc4_hdmi->variant->reset(vc4_hdmi); 3374 3375 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3376 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3377 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3378 /* Set the logical address to Unregistered */ 3379 value |= VC4_HDMI_CEC_ADDR_MASK; 3380 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3381 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3382 3383 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3384 3385 if (!vc4_hdmi->variant->external_irq_controller) { 3386 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3387 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3388 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3389 } 3390 #endif 3391 3392 return 0; 3393 3394 err_disable_clk: 3395 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3396 return ret; 3397 } 3398 3399 static void vc4_hdmi_put_ddc_device(void *ptr) 3400 { 3401 struct vc4_hdmi *vc4_hdmi = ptr; 3402 3403 put_device(&vc4_hdmi->ddc->dev); 3404 } 3405 3406 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3407 { 3408 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3409 struct platform_device *pdev = to_platform_device(dev); 3410 struct drm_device *drm = dev_get_drvdata(master); 3411 struct vc4_hdmi *vc4_hdmi; 3412 struct drm_encoder *encoder; 3413 struct device_node *ddc_node; 3414 int ret; 3415 3416 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3417 if (!vc4_hdmi) 3418 return -ENOMEM; 3419 3420 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3421 if (ret) 3422 return ret; 3423 3424 spin_lock_init(&vc4_hdmi->hw_lock); 3425 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3426 3427 dev_set_drvdata(dev, vc4_hdmi); 3428 encoder = &vc4_hdmi->encoder.base; 3429 vc4_hdmi->encoder.type = variant->encoder_type; 3430 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3431 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3432 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3433 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3434 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3435 vc4_hdmi->pdev = pdev; 3436 vc4_hdmi->variant = variant; 3437 3438 /* 3439 * Since we don't know the state of the controller and its 3440 * display (if any), let's assume it's always enabled. 3441 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3442 * sure it's disabled, and avoid any inconsistency. 3443 */ 3444 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3445 vc4_hdmi->scdc_enabled = true; 3446 3447 ret = variant->init_resources(drm, vc4_hdmi); 3448 if (ret) 3449 return ret; 3450 3451 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3452 if (!ddc_node) { 3453 DRM_ERROR("Failed to find ddc node in device tree\n"); 3454 return -ENODEV; 3455 } 3456 3457 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3458 of_node_put(ddc_node); 3459 if (!vc4_hdmi->ddc) { 3460 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 3461 return -EPROBE_DEFER; 3462 } 3463 3464 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3465 if (ret) 3466 return ret; 3467 3468 /* Only use the GPIO HPD pin if present in the DT, otherwise 3469 * we'll use the HDMI core's register. 3470 */ 3471 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3472 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3473 return PTR_ERR(vc4_hdmi->hpd_gpio); 3474 } 3475 3476 vc4_hdmi->disable_wifi_frequencies = 3477 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3478 3479 ret = devm_pm_runtime_enable(dev); 3480 if (ret) 3481 return ret; 3482 3483 /* 3484 * We need to have the device powered up at this point to call 3485 * our reset hook and for the CEC init. 3486 */ 3487 ret = pm_runtime_resume_and_get(dev); 3488 if (ret) 3489 return ret; 3490 3491 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3492 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 3493 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3494 clk_prepare_enable(vc4_hdmi->pixel_clock); 3495 clk_prepare_enable(vc4_hdmi->hsm_clock); 3496 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3497 } 3498 3499 ret = drmm_encoder_init(drm, encoder, 3500 &vc4_hdmi_encoder_funcs, 3501 DRM_MODE_ENCODER_TMDS, 3502 NULL); 3503 if (ret) 3504 goto err_put_runtime_pm; 3505 3506 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3507 3508 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3509 if (ret) 3510 goto err_put_runtime_pm; 3511 3512 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3513 if (ret) 3514 goto err_put_runtime_pm; 3515 3516 ret = vc4_hdmi_cec_init(vc4_hdmi); 3517 if (ret) 3518 goto err_put_runtime_pm; 3519 3520 ret = vc4_hdmi_audio_init(vc4_hdmi); 3521 if (ret) 3522 goto err_put_runtime_pm; 3523 3524 pm_runtime_put_sync(dev); 3525 3526 return 0; 3527 3528 err_put_runtime_pm: 3529 pm_runtime_put_sync(dev); 3530 3531 return ret; 3532 } 3533 3534 static const struct component_ops vc4_hdmi_ops = { 3535 .bind = vc4_hdmi_bind, 3536 }; 3537 3538 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3539 { 3540 return component_add(&pdev->dev, &vc4_hdmi_ops); 3541 } 3542 3543 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 3544 { 3545 component_del(&pdev->dev, &vc4_hdmi_ops); 3546 return 0; 3547 } 3548 3549 static const struct vc4_hdmi_variant bcm2835_variant = { 3550 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3551 .debugfs_name = "hdmi_regs", 3552 .card_name = "vc4-hdmi", 3553 .max_pixel_clock = 162000000, 3554 .registers = vc4_hdmi_fields, 3555 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3556 3557 .init_resources = vc4_hdmi_init_resources, 3558 .csc_setup = vc4_hdmi_csc_setup, 3559 .reset = vc4_hdmi_reset, 3560 .set_timings = vc4_hdmi_set_timings, 3561 .phy_init = vc4_hdmi_phy_init, 3562 .phy_disable = vc4_hdmi_phy_disable, 3563 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3564 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3565 .channel_map = vc4_hdmi_channel_map, 3566 .supports_hdr = false, 3567 }; 3568 3569 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3570 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3571 .debugfs_name = "hdmi0_regs", 3572 .card_name = "vc4-hdmi-0", 3573 .max_pixel_clock = 600000000, 3574 .registers = vc5_hdmi_hdmi0_fields, 3575 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3576 .phy_lane_mapping = { 3577 PHY_LANE_0, 3578 PHY_LANE_1, 3579 PHY_LANE_2, 3580 PHY_LANE_CK, 3581 }, 3582 .unsupported_odd_h_timings = true, 3583 .external_irq_controller = true, 3584 3585 .init_resources = vc5_hdmi_init_resources, 3586 .csc_setup = vc5_hdmi_csc_setup, 3587 .reset = vc5_hdmi_reset, 3588 .set_timings = vc5_hdmi_set_timings, 3589 .phy_init = vc5_hdmi_phy_init, 3590 .phy_disable = vc5_hdmi_phy_disable, 3591 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3592 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3593 .channel_map = vc5_hdmi_channel_map, 3594 .supports_hdr = true, 3595 .hp_detect = vc5_hdmi_hp_detect, 3596 }; 3597 3598 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3599 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3600 .debugfs_name = "hdmi1_regs", 3601 .card_name = "vc4-hdmi-1", 3602 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3603 .registers = vc5_hdmi_hdmi1_fields, 3604 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3605 .phy_lane_mapping = { 3606 PHY_LANE_1, 3607 PHY_LANE_0, 3608 PHY_LANE_CK, 3609 PHY_LANE_2, 3610 }, 3611 .unsupported_odd_h_timings = true, 3612 .external_irq_controller = true, 3613 3614 .init_resources = vc5_hdmi_init_resources, 3615 .csc_setup = vc5_hdmi_csc_setup, 3616 .reset = vc5_hdmi_reset, 3617 .set_timings = vc5_hdmi_set_timings, 3618 .phy_init = vc5_hdmi_phy_init, 3619 .phy_disable = vc5_hdmi_phy_disable, 3620 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3621 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3622 .channel_map = vc5_hdmi_channel_map, 3623 .supports_hdr = true, 3624 .hp_detect = vc5_hdmi_hp_detect, 3625 }; 3626 3627 static const struct of_device_id vc4_hdmi_dt_match[] = { 3628 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3629 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3630 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3631 {} 3632 }; 3633 3634 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3635 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3636 vc4_hdmi_runtime_resume, 3637 NULL) 3638 }; 3639 3640 struct platform_driver vc4_hdmi_driver = { 3641 .probe = vc4_hdmi_dev_probe, 3642 .remove = vc4_hdmi_dev_remove, 3643 .driver = { 3644 .name = "vc4_hdmi", 3645 .of_match_table = vc4_hdmi_dt_match, 3646 .pm = &vc4_hdmi_pm_ops, 3647 }, 3648 }; 3649