1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_audio_helper.h> 35 #include <drm/display/drm_hdmi_cec_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_hdmi_state_helper.h> 38 #include <drm/display/drm_scdc_helper.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_drv.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/drm_simple_kms_helper.h> 45 #include <linux/clk.h> 46 #include <linux/component.h> 47 #include <linux/gpio/consumer.h> 48 #include <linux/i2c.h> 49 #include <linux/of.h> 50 #include <linux/of_address.h> 51 #include <linux/pm_runtime.h> 52 #include <linux/rational.h> 53 #include <linux/reset.h> 54 #include <sound/dmaengine_pcm.h> 55 #include <sound/hdmi-codec.h> 56 #include <sound/jack.h> 57 #include <sound/pcm_drm_eld.h> 58 #include <sound/pcm_params.h> 59 #include <sound/soc.h> 60 #include "media/cec.h" 61 #include "vc4_drv.h" 62 #include "vc4_hdmi.h" 63 #include "vc4_hdmi_regs.h" 64 #include "vc4_regs.h" 65 66 #define VC5_HDMI_HORZA_HFP_SHIFT 16 67 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 68 #define VC5_HDMI_HORZA_VPOS BIT(15) 69 #define VC5_HDMI_HORZA_HPOS BIT(14) 70 #define VC5_HDMI_HORZA_HAP_SHIFT 0 71 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 72 73 #define VC5_HDMI_HORZB_HBP_SHIFT 16 74 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 75 #define VC5_HDMI_HORZB_HSP_SHIFT 0 76 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 77 78 #define VC5_HDMI_VERTA_VSP_SHIFT 24 79 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 80 #define VC5_HDMI_VERTA_VFP_SHIFT 16 81 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 82 #define VC5_HDMI_VERTA_VAL_SHIFT 0 83 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 84 85 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 86 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 87 88 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 89 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 90 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 91 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 92 93 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 94 95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 96 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 97 98 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 99 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 100 101 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 102 103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 105 106 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0) 107 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0) 108 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4) 109 110 # define VC4_HD_M_SW_RST BIT(2) 111 # define VC4_HD_M_ENABLE BIT(0) 112 113 #define HSM_MIN_CLOCK_FREQ 120000000 114 #define CEC_CLOCK_FREQ 40000 115 116 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 117 118 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 119 { 120 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 121 122 lockdep_assert_held(&vc4_hdmi->mutex); 123 124 if (!display->is_hdmi) 125 return false; 126 127 if (!display->hdmi.scdc.supported || 128 !display->hdmi.scdc.scrambling.supported) 129 return false; 130 131 return true; 132 } 133 134 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 135 unsigned int bpc, 136 enum hdmi_colorspace fmt) 137 { 138 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt); 139 140 return clock > HDMI_14_MAX_TMDS_CLK; 141 } 142 143 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 144 { 145 struct drm_debugfs_entry *entry = m->private; 146 struct vc4_hdmi *vc4_hdmi = entry->file.data; 147 struct drm_device *drm = vc4_hdmi->connector.dev; 148 struct drm_printer p = drm_seq_file_printer(m); 149 int idx; 150 151 if (!drm_dev_enter(drm, &idx)) 152 return -ENODEV; 153 154 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 155 156 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 157 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 158 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 159 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 160 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 161 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 162 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 163 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 164 165 pm_runtime_put(&vc4_hdmi->pdev->dev); 166 167 drm_dev_exit(idx); 168 169 return 0; 170 } 171 172 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 173 { 174 struct drm_device *drm = vc4_hdmi->connector.dev; 175 unsigned long flags; 176 int idx; 177 178 /* 179 * We can be called by our bind callback, when the 180 * connector->dev pointer might not be initialised yet. 181 */ 182 if (drm && !drm_dev_enter(drm, &idx)) 183 return; 184 185 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 186 187 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 188 udelay(1); 189 HDMI_WRITE(HDMI_M_CTL, 0); 190 191 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 192 193 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 194 VC4_HDMI_SW_RESET_HDMI | 195 VC4_HDMI_SW_RESET_FORMAT_DETECT); 196 197 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 198 199 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 200 201 if (drm) 202 drm_dev_exit(idx); 203 } 204 205 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 206 { 207 struct drm_device *drm = vc4_hdmi->connector.dev; 208 unsigned long flags; 209 int idx; 210 211 /* 212 * We can be called by our bind callback, when the 213 * connector->dev pointer might not be initialised yet. 214 */ 215 if (drm && !drm_dev_enter(drm, &idx)) 216 return; 217 218 reset_control_reset(vc4_hdmi->reset); 219 220 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 221 222 HDMI_WRITE(HDMI_DVP_CTL, 0); 223 224 HDMI_WRITE(HDMI_CLOCK_STOP, 225 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 226 227 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 228 229 if (drm) 230 drm_dev_exit(idx); 231 } 232 233 #ifdef CONFIG_DRM_VC4_HDMI_CEC 234 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 235 { 236 struct drm_device *drm = vc4_hdmi->connector.dev; 237 unsigned long cec_rate; 238 unsigned long flags; 239 u16 clk_cnt; 240 u32 value; 241 int idx; 242 243 /* 244 * This function is called by our runtime_resume implementation 245 * and thus at bind time, when we haven't registered our 246 * connector yet and thus don't have a pointer to the DRM 247 * device. 248 */ 249 if (drm && !drm_dev_enter(drm, &idx)) 250 return; 251 252 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 253 254 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 255 256 value = HDMI_READ(HDMI_CEC_CNTRL_1); 257 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 258 259 /* 260 * Set the clock divider: the hsm_clock rate and this divider 261 * setting will give a 40 kHz CEC clock. 262 */ 263 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 264 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 265 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 266 267 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 268 269 if (drm) 270 drm_dev_exit(idx); 271 } 272 #else 273 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 274 #endif 275 276 static int vc4_hdmi_reset_link(struct drm_connector *connector, 277 struct drm_modeset_acquire_ctx *ctx) 278 { 279 struct drm_device *drm; 280 struct vc4_hdmi *vc4_hdmi; 281 struct drm_connector_state *conn_state; 282 struct drm_crtc_state *crtc_state; 283 struct drm_crtc *crtc; 284 bool scrambling_needed; 285 u8 config; 286 int ret; 287 288 if (!connector) 289 return 0; 290 291 drm = connector->dev; 292 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 293 if (ret) 294 return ret; 295 296 conn_state = connector->state; 297 crtc = conn_state->crtc; 298 if (!crtc) 299 return 0; 300 301 ret = drm_modeset_lock(&crtc->mutex, ctx); 302 if (ret) 303 return ret; 304 305 crtc_state = crtc->state; 306 if (!crtc_state->active) 307 return 0; 308 309 vc4_hdmi = connector_to_vc4_hdmi(connector); 310 mutex_lock(&vc4_hdmi->mutex); 311 312 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 313 mutex_unlock(&vc4_hdmi->mutex); 314 return 0; 315 } 316 317 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 318 vc4_hdmi->output_bpc, 319 vc4_hdmi->output_format); 320 if (!scrambling_needed) { 321 mutex_unlock(&vc4_hdmi->mutex); 322 return 0; 323 } 324 325 if (conn_state->commit && 326 !try_wait_for_completion(&conn_state->commit->hw_done)) { 327 mutex_unlock(&vc4_hdmi->mutex); 328 return 0; 329 } 330 331 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 332 if (ret < 0) { 333 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 334 mutex_unlock(&vc4_hdmi->mutex); 335 return 0; 336 } 337 338 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 339 mutex_unlock(&vc4_hdmi->mutex); 340 return 0; 341 } 342 343 mutex_unlock(&vc4_hdmi->mutex); 344 345 /* 346 * HDMI 2.0 says that one should not send scrambled data 347 * prior to configuring the sink scrambling, and that 348 * TMDS clock/data transmission should be suspended when 349 * changing the TMDS clock rate in the sink. So let's 350 * just do a full modeset here, even though some sinks 351 * would be perfectly happy if were to just reconfigure 352 * the SCDC settings on the fly. 353 */ 354 return drm_atomic_helper_reset_crtc(crtc, ctx); 355 } 356 357 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 358 struct drm_modeset_acquire_ctx *ctx, 359 enum drm_connector_status status) 360 { 361 struct drm_connector *connector = &vc4_hdmi->connector; 362 int ret; 363 364 /* 365 * NOTE: This function should really be called with vc4_hdmi->mutex 366 * held, but doing so results in reentrancy issues since 367 * cec_s_phys_addr() might call .adap_enable, which leads to that 368 * funtion being called with our mutex held. 369 * 370 * A similar situation occurs with vc4_hdmi_reset_link() that 371 * will call into our KMS hooks if the scrambling was enabled. 372 * 373 * Concurrency isn't an issue at the moment since we don't share 374 * any state with any of the other frameworks so we can ignore 375 * the lock for now. 376 */ 377 378 drm_atomic_helper_connector_hdmi_hotplug(connector, status); 379 380 if (status != connector_status_connected) 381 return; 382 383 for (;;) { 384 ret = vc4_hdmi_reset_link(connector, ctx); 385 if (ret == -EDEADLK) { 386 drm_modeset_backoff(ctx); 387 continue; 388 } 389 390 break; 391 } 392 } 393 394 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 395 struct drm_modeset_acquire_ctx *ctx, 396 bool force) 397 { 398 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 399 enum drm_connector_status status = connector_status_disconnected; 400 int ret; 401 402 /* 403 * NOTE: This function should really take vc4_hdmi->mutex, but 404 * doing so results in reentrancy issues since 405 * vc4_hdmi_handle_hotplug() can call into other functions that 406 * would take the mutex while it's held here. 407 * 408 * Concurrency isn't an issue at the moment since we don't share 409 * any state with any of the other frameworks so we can ignore 410 * the lock for now. 411 */ 412 413 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 414 if (ret) { 415 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n", 416 ret); 417 return connector_status_unknown; 418 } 419 420 if (vc4_hdmi->hpd_gpio) { 421 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 422 status = connector_status_connected; 423 } else { 424 if (vc4_hdmi->variant->hp_detect && 425 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 426 status = connector_status_connected; 427 } 428 429 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 430 pm_runtime_put(&vc4_hdmi->pdev->dev); 431 432 return status; 433 } 434 435 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 436 { 437 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 438 int ret = 0; 439 440 ret = drm_edid_connector_add_modes(connector); 441 442 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 443 struct drm_device *drm = connector->dev; 444 const struct drm_display_mode *mode; 445 446 list_for_each_entry(mode, &connector->probed_modes, head) { 447 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) { 448 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 449 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 450 } 451 } 452 } 453 454 return ret; 455 } 456 457 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 458 struct drm_atomic_state *state) 459 { 460 struct drm_connector_state *old_state = 461 drm_atomic_get_old_connector_state(state, connector); 462 struct drm_connector_state *new_state = 463 drm_atomic_get_new_connector_state(state, connector); 464 struct drm_crtc *crtc = new_state->crtc; 465 466 if (!crtc) 467 return 0; 468 469 if (old_state->tv.margins.left != new_state->tv.margins.left || 470 old_state->tv.margins.right != new_state->tv.margins.right || 471 old_state->tv.margins.top != new_state->tv.margins.top || 472 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 473 struct drm_crtc_state *crtc_state; 474 int ret; 475 476 crtc_state = drm_atomic_get_crtc_state(state, crtc); 477 if (IS_ERR(crtc_state)) 478 return PTR_ERR(crtc_state); 479 480 /* 481 * Strictly speaking, we should be calling 482 * drm_atomic_helper_check_planes() after our call to 483 * drm_atomic_add_affected_planes(). However, the 484 * connector atomic_check is called as part of 485 * drm_atomic_helper_check_modeset() that already 486 * happens before a call to 487 * drm_atomic_helper_check_planes() in 488 * drm_atomic_helper_check(). 489 */ 490 ret = drm_atomic_add_affected_planes(state, crtc); 491 if (ret) 492 return ret; 493 } 494 495 if (old_state->colorspace != new_state->colorspace) { 496 struct drm_crtc_state *crtc_state; 497 498 crtc_state = drm_atomic_get_crtc_state(state, crtc); 499 if (IS_ERR(crtc_state)) 500 return PTR_ERR(crtc_state); 501 502 crtc_state->mode_changed = true; 503 } 504 505 return drm_atomic_helper_connector_hdmi_check(connector, state); 506 } 507 508 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 509 { 510 drm_atomic_helper_connector_reset(connector); 511 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); 512 drm_atomic_helper_connector_tv_margins_reset(connector); 513 } 514 515 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 516 .force = drm_atomic_helper_connector_hdmi_force, 517 .fill_modes = drm_helper_probe_single_connector_modes, 518 .reset = vc4_hdmi_connector_reset, 519 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 520 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 521 }; 522 523 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 524 .detect_ctx = vc4_hdmi_connector_detect_ctx, 525 .get_modes = vc4_hdmi_connector_get_modes, 526 .atomic_check = vc4_hdmi_connector_atomic_check, 527 .mode_valid = drm_hdmi_connector_mode_valid, 528 }; 529 530 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs; 531 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs; 532 533 static int vc4_hdmi_connector_init(struct drm_device *dev, 534 struct vc4_hdmi *vc4_hdmi) 535 { 536 struct drm_connector *connector = &vc4_hdmi->connector; 537 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 538 unsigned int max_bpc = 8; 539 int ret; 540 541 if (vc4_hdmi->variant->supports_hdr) 542 max_bpc = 12; 543 544 ret = drmm_connector_hdmi_init(dev, connector, 545 "Broadcom", "Videocore", 546 &vc4_hdmi_connector_funcs, 547 &vc4_hdmi_hdmi_connector_funcs, 548 DRM_MODE_CONNECTOR_HDMIA, 549 vc4_hdmi->ddc, 550 BIT(HDMI_COLORSPACE_RGB) | 551 BIT(HDMI_COLORSPACE_YUV422) | 552 BIT(HDMI_COLORSPACE_YUV444), 553 max_bpc); 554 if (ret) 555 return ret; 556 557 ret = drm_connector_hdmi_audio_init(connector, dev->dev, 558 &vc4_hdmi_audio_funcs, 559 8, 0, false, -1); 560 if (ret) 561 return ret; 562 563 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 564 565 /* 566 * Some of the properties below require access to state, like bpc. 567 * Allocate some default initial connector state with our reset helper. 568 */ 569 if (connector->funcs->reset) 570 connector->funcs->reset(connector); 571 572 /* Create and attach TV margin props to this connector. */ 573 ret = drm_mode_create_tv_margin_properties(dev); 574 if (ret) 575 return ret; 576 577 ret = drm_mode_create_hdmi_colorspace_property(connector, 0); 578 if (ret) 579 return ret; 580 581 drm_connector_attach_colorspace_property(connector); 582 drm_connector_attach_tv_margin_properties(connector); 583 584 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 585 DRM_CONNECTOR_POLL_DISCONNECT); 586 587 connector->interlace_allowed = 1; 588 connector->doublescan_allowed = 0; 589 connector->stereo_allowed = 1; 590 591 ret = drm_connector_attach_broadcast_rgb_property(connector); 592 if (ret) 593 return ret; 594 595 drm_connector_attach_encoder(connector, encoder); 596 597 return 0; 598 } 599 600 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi, 601 enum hdmi_infoframe_type type, 602 bool poll) 603 { 604 struct drm_device *drm = vc4_hdmi->connector.dev; 605 u32 packet_id = type - 0x80; 606 unsigned long flags; 607 int ret = 0; 608 int idx; 609 610 if (!drm_dev_enter(drm, &idx)) 611 return -ENODEV; 612 613 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 614 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 615 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 616 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 617 618 if (poll) { 619 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 620 BIT(packet_id)), 100); 621 } 622 623 drm_dev_exit(idx); 624 return ret; 625 } 626 627 static int vc4_hdmi_clear_infoframe(struct drm_connector *connector, 628 enum hdmi_infoframe_type type) 629 { 630 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 631 struct drm_device *drm = connector->dev; 632 int ret; 633 int idx; 634 635 if (!drm_dev_enter(drm, &idx)) 636 return 0; 637 638 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 639 VC4_HDMI_RAM_PACKET_ENABLE), 640 "Packet RAM has to be on to store the packet."); 641 642 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true); 643 if (ret) 644 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret); 645 646 drm_dev_exit(idx); 647 648 return ret; 649 } 650 651 static int vc4_hdmi_write_infoframe(struct drm_connector *connector, 652 enum hdmi_infoframe_type type, 653 const u8 *infoframe, size_t len) 654 { 655 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 656 struct drm_device *drm = connector->dev; 657 u32 packet_id = type - 0x80; 658 const struct vc4_hdmi_register *ram_packet_start = 659 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 660 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 661 u32 packet_reg_next = ram_packet_start->offset + 662 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 663 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 664 ram_packet_start->reg); 665 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 666 unsigned long flags; 667 ssize_t i; 668 int ret; 669 int idx; 670 671 if (!drm_dev_enter(drm, &idx)) 672 return 0; 673 674 if (len > sizeof(buffer)) { 675 ret = -ENOMEM; 676 goto out; 677 } 678 679 memcpy(buffer, infoframe, len); 680 681 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 682 VC4_HDMI_RAM_PACKET_ENABLE), 683 "Packet RAM has to be on to store the packet."); 684 685 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true); 686 if (ret) { 687 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret); 688 goto out; 689 } 690 691 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 692 693 for (i = 0; i < len; i += 7) { 694 writel(buffer[i + 0] << 0 | 695 buffer[i + 1] << 8 | 696 buffer[i + 2] << 16, 697 base + packet_reg); 698 packet_reg += 4; 699 700 writel(buffer[i + 3] << 0 | 701 buffer[i + 4] << 8 | 702 buffer[i + 5] << 16 | 703 buffer[i + 6] << 24, 704 base + packet_reg); 705 packet_reg += 4; 706 } 707 708 /* 709 * clear remainder of packet ram as it's included in the 710 * infoframe and triggers a checksum error on hdmi analyser 711 */ 712 for (; packet_reg < packet_reg_next; packet_reg += 4) 713 writel(0, base + packet_reg); 714 715 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 716 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 717 718 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 719 720 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 721 BIT(packet_id)), 100); 722 if (ret) 723 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret); 724 725 out: 726 drm_dev_exit(idx); 727 return ret; 728 } 729 730 static int vc4_hdmi_clear_avi_infoframe(struct drm_connector *connector) 731 { 732 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_AVI); 733 } 734 735 static int vc4_hdmi_clear_hdmi_infoframe(struct drm_connector *connector) 736 { 737 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_VENDOR); 738 } 739 740 static int vc4_hdmi_clear_audio_infoframe(struct drm_connector *connector) 741 { 742 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_AUDIO); 743 } 744 745 static int vc4_hdmi_clear_hdr_drm_infoframe(struct drm_connector *connector) 746 { 747 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_DRM); 748 } 749 750 static int vc4_hdmi_clear_spd_infoframe(struct drm_connector *connector) 751 { 752 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_SPD); 753 } 754 755 static int vc4_hdmi_write_avi_infoframe(struct drm_connector *connector, 756 const u8 *buffer, size_t len) 757 { 758 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_AVI, 759 buffer, len); 760 } 761 762 static int vc4_hdmi_write_hdmi_infoframe(struct drm_connector *connector, 763 const u8 *buffer, size_t len) 764 { 765 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_VENDOR, 766 buffer, len); 767 } 768 769 static int vc4_hdmi_write_audio_infoframe(struct drm_connector *connector, 770 const u8 *buffer, size_t len) 771 { 772 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_AUDIO, 773 buffer, len); 774 } 775 776 static int vc4_hdmi_write_hdr_drm_infoframe(struct drm_connector *connector, 777 const u8 *buffer, size_t len) 778 { 779 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_DRM, 780 buffer, len); 781 } 782 783 static int vc4_hdmi_write_spd_infoframe(struct drm_connector *connector, 784 const u8 *buffer, size_t len) 785 { 786 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_SPD, 787 buffer, len); 788 } 789 790 #define SCRAMBLING_POLLING_DELAY_MS 1000 791 792 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 793 { 794 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 795 struct drm_connector *connector = &vc4_hdmi->connector; 796 struct drm_device *drm = connector->dev; 797 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 798 unsigned long flags; 799 int idx; 800 801 lockdep_assert_held(&vc4_hdmi->mutex); 802 803 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 804 return; 805 806 if (!vc4_hdmi_mode_needs_scrambling(mode, 807 vc4_hdmi->output_bpc, 808 vc4_hdmi->output_format)) 809 return; 810 811 if (!drm_dev_enter(drm, &idx)) 812 return; 813 814 drm_scdc_set_high_tmds_clock_ratio(connector, true); 815 drm_scdc_set_scrambling(connector, true); 816 817 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 818 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 819 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 820 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 821 822 drm_dev_exit(idx); 823 824 vc4_hdmi->scdc_enabled = true; 825 826 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 827 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 828 } 829 830 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 831 { 832 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 833 struct drm_connector *connector = &vc4_hdmi->connector; 834 struct drm_device *drm = connector->dev; 835 unsigned long flags; 836 int idx; 837 838 lockdep_assert_held(&vc4_hdmi->mutex); 839 840 if (!vc4_hdmi->scdc_enabled) 841 return; 842 843 vc4_hdmi->scdc_enabled = false; 844 845 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 846 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 847 848 if (!drm_dev_enter(drm, &idx)) 849 return; 850 851 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 852 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 853 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 854 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 855 856 drm_scdc_set_scrambling(connector, false); 857 drm_scdc_set_high_tmds_clock_ratio(connector, false); 858 859 drm_dev_exit(idx); 860 } 861 862 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 863 { 864 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 865 struct vc4_hdmi, 866 scrambling_work); 867 struct drm_connector *connector = &vc4_hdmi->connector; 868 869 if (drm_scdc_get_scrambling_status(connector)) 870 return; 871 872 drm_scdc_set_high_tmds_clock_ratio(connector, true); 873 drm_scdc_set_scrambling(connector, true); 874 875 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 876 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 877 } 878 879 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 880 struct drm_atomic_state *state) 881 { 882 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 883 struct drm_device *drm = vc4_hdmi->connector.dev; 884 struct vc4_dev *vc4 = to_vc4_dev(drm); 885 unsigned long flags; 886 int idx; 887 888 mutex_lock(&vc4_hdmi->mutex); 889 890 vc4_hdmi->packet_ram_enabled = false; 891 892 if (!drm_dev_enter(drm, &idx)) 893 goto out; 894 895 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 896 897 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 898 899 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 900 901 if (vc4->gen >= VC4_GEN_6_C) 902 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 903 VC4_HD_VID_CTL_BLANKPIX); 904 905 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 906 907 mdelay(1); 908 909 /* 910 * TODO: This should work on BCM2712, but doesn't for some 911 * reason and result in a system lockup. 912 */ 913 if (vc4->gen < VC4_GEN_6_C) { 914 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 915 HDMI_WRITE(HDMI_VID_CTL, 916 HDMI_READ(HDMI_VID_CTL) & 917 ~VC4_HD_VID_CTL_ENABLE); 918 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 919 } 920 921 vc4_hdmi_disable_scrambling(encoder); 922 923 drm_dev_exit(idx); 924 925 out: 926 mutex_unlock(&vc4_hdmi->mutex); 927 } 928 929 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 930 struct drm_atomic_state *state) 931 { 932 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 933 struct drm_device *drm = vc4_hdmi->connector.dev; 934 unsigned long flags; 935 int idx; 936 937 mutex_lock(&vc4_hdmi->mutex); 938 939 if (!drm_dev_enter(drm, &idx)) 940 goto out; 941 942 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 943 HDMI_WRITE(HDMI_VID_CTL, 944 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 945 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 946 947 if (vc4_hdmi->variant->phy_disable) 948 vc4_hdmi->variant->phy_disable(vc4_hdmi); 949 950 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 951 clk_disable_unprepare(vc4_hdmi->pixel_clock); 952 953 pm_runtime_put(&vc4_hdmi->pdev->dev); 954 955 drm_dev_exit(idx); 956 957 out: 958 mutex_unlock(&vc4_hdmi->mutex); 959 } 960 961 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 962 struct drm_connector_state *state, 963 const struct drm_display_mode *mode) 964 { 965 struct drm_device *drm = vc4_hdmi->connector.dev; 966 unsigned long flags; 967 u32 csc_ctl; 968 int idx; 969 970 if (!drm_dev_enter(drm, &idx)) 971 return; 972 973 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 974 975 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 976 VC4_HD_CSC_CTL_ORDER); 977 978 if (state->hdmi.is_limited_range) { 979 /* CEA VICs other than #1 requre limited range RGB 980 * output unless overridden by an AVI infoframe. 981 * Apply a colorspace conversion to squash 0-255 down 982 * to 16-235. The matrix here is: 983 * 984 * [ 0 0 0.8594 16] 985 * [ 0 0.8594 0 16] 986 * [ 0.8594 0 0 16] 987 * [ 0 0 0 1] 988 */ 989 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 990 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 991 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 992 VC4_HD_CSC_CTL_MODE); 993 994 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 995 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 996 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 997 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 998 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 999 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 1000 } 1001 1002 /* The RGB order applies even when CSC is disabled. */ 1003 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1004 1005 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1006 1007 drm_dev_exit(idx); 1008 } 1009 1010 /* 1011 * Matrices for (internal) RGB to RGB output. 1012 * 1013 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1014 */ 1015 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = { 1016 { 1017 /* 1018 * Full range - unity 1019 * 1020 * [ 1 0 0 0] 1021 * [ 0 1 0 0] 1022 * [ 0 0 1 0] 1023 */ 1024 { 0x2000, 0x0000, 0x0000, 0x0000 }, 1025 { 0x0000, 0x2000, 0x0000, 0x0000 }, 1026 { 0x0000, 0x0000, 0x2000, 0x0000 }, 1027 }, 1028 { 1029 /* 1030 * Limited range 1031 * 1032 * CEA VICs other than #1 require limited range RGB 1033 * output unless overridden by an AVI infoframe. Apply a 1034 * colorspace conversion to squash 0-255 down to 16-235. 1035 * The matrix here is: 1036 * 1037 * [ 0.8594 0 0 16] 1038 * [ 0 0.8594 0 16] 1039 * [ 0 0 0.8594 16] 1040 */ 1041 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 1042 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 1043 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 1044 }, 1045 }; 1046 1047 /* 1048 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace 1049 * 1050 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1051 */ 1052 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = { 1053 { 1054 /* 1055 * Full Range 1056 * 1057 * [ 0.299000 0.587000 0.114000 0 ] 1058 * [ -0.168736 -0.331264 0.500000 128 ] 1059 * [ 0.500000 -0.418688 -0.081312 128 ] 1060 */ 1061 { 0x0991, 0x12c9, 0x03a6, 0x0000 }, 1062 { 0xfa9b, 0xf567, 0x1000, 0x2000 }, 1063 { 0x1000, 0xf29b, 0xfd67, 0x2000 }, 1064 }, 1065 { 1066 /* Limited Range 1067 * 1068 * [ 0.255785 0.502160 0.097523 16 ] 1069 * [ -0.147644 -0.289856 0.437500 128 ] 1070 * [ 0.437500 -0.366352 -0.071148 128 ] 1071 */ 1072 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1073 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1074 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1075 }, 1076 }; 1077 1078 /* 1079 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace 1080 * 1081 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1082 */ 1083 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = { 1084 { 1085 /* 1086 * Full Range 1087 * 1088 * [ 0.212600 0.715200 0.072200 0 ] 1089 * [ -0.114572 -0.385428 0.500000 128 ] 1090 * [ 0.500000 -0.454153 -0.045847 128 ] 1091 */ 1092 { 0x06ce, 0x16e3, 0x024f, 0x0000 }, 1093 { 0xfc56, 0xf3ac, 0x1000, 0x2000 }, 1094 { 0x1000, 0xf179, 0xfe89, 0x2000 }, 1095 }, 1096 { 1097 /* 1098 * Limited Range 1099 * 1100 * [ 0.181906 0.611804 0.061758 16 ] 1101 * [ -0.100268 -0.337232 0.437500 128 ] 1102 * [ 0.437500 -0.397386 -0.040114 128 ] 1103 */ 1104 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1105 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1106 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1107 }, 1108 }; 1109 1110 /* 1111 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace 1112 * 1113 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1114 */ 1115 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = { 1116 { 1117 /* 1118 * Full Range 1119 * 1120 * [ 0.262700 0.678000 0.059300 0 ] 1121 * [ -0.139630 -0.360370 0.500000 128 ] 1122 * [ 0.500000 -0.459786 -0.040214 128 ] 1123 */ 1124 { 0x0868, 0x15b2, 0x01e6, 0x0000 }, 1125 { 0xfb89, 0xf479, 0x1000, 0x2000 }, 1126 { 0x1000, 0xf14a, 0xfeb8, 0x2000 }, 1127 }, 1128 { 1129 /* Limited Range 1130 * 1131 * [ 0.224732 0.580008 0.050729 16 ] 1132 * [ -0.122176 -0.315324 0.437500 128 ] 1133 * [ 0.437500 -0.402312 -0.035188 128 ] 1134 */ 1135 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1136 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1137 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1138 }, 1139 }; 1140 1141 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1142 const u16 coeffs[3][4]) 1143 { 1144 lockdep_assert_held(&vc4_hdmi->hw_lock); 1145 1146 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1147 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1148 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1149 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1150 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1151 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1152 } 1153 1154 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi, 1155 const u16 coeffs[3][4]) 1156 { 1157 lockdep_assert_held(&vc4_hdmi->hw_lock); 1158 1159 /* YUV444 needs the CSC matrices using the channels in a different order */ 1160 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]); 1161 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]); 1162 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]); 1163 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]); 1164 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]); 1165 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]); 1166 } 1167 1168 static const u16 1169 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4] 1170 { 1171 switch (colorspace) { 1172 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC: 1173 case DRM_MODE_COLORIMETRY_XVYCC_601: 1174 case DRM_MODE_COLORIMETRY_SYCC_601: 1175 case DRM_MODE_COLORIMETRY_OPYCC_601: 1176 case DRM_MODE_COLORIMETRY_BT601_YCC: 1177 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited]; 1178 1179 default: 1180 case DRM_MODE_COLORIMETRY_NO_DATA: 1181 case DRM_MODE_COLORIMETRY_BT709_YCC: 1182 case DRM_MODE_COLORIMETRY_XVYCC_709: 1183 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED: 1184 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT: 1185 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited]; 1186 1187 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 1188 case DRM_MODE_COLORIMETRY_BT2020_YCC: 1189 case DRM_MODE_COLORIMETRY_BT2020_RGB: 1190 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 1191 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 1192 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited]; 1193 } 1194 } 1195 1196 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1197 struct drm_connector_state *state, 1198 const struct drm_display_mode *mode) 1199 { 1200 struct drm_device *drm = vc4_hdmi->connector.dev; 1201 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0; 1202 unsigned long flags; 1203 const u16 (*csc)[4]; 1204 u32 if_cfg = 0; 1205 u32 if_xbar = 0x543210; 1206 u32 csc_chan_ctl = 0; 1207 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1208 VC5_MT_CP_CSC_CTL_MODE); 1209 int idx; 1210 1211 if (!drm_dev_enter(drm, &idx)) 1212 return; 1213 1214 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1215 1216 switch (state->hdmi.output_format) { 1217 case HDMI_COLORSPACE_YUV444: 1218 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1219 1220 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc); 1221 break; 1222 1223 case HDMI_COLORSPACE_YUV422: 1224 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1225 1226 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1227 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1228 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1229 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1230 1231 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1232 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1233 1234 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1235 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1236 1237 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc); 1238 break; 1239 1240 case HDMI_COLORSPACE_RGB: 1241 if_xbar = 0x354021; 1242 1243 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]); 1244 break; 1245 1246 default: 1247 break; 1248 } 1249 1250 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1251 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1252 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1253 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1254 1255 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1256 1257 drm_dev_exit(idx); 1258 } 1259 1260 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1261 struct drm_connector_state *state, 1262 const struct drm_display_mode *mode) 1263 { 1264 struct drm_device *drm = vc4_hdmi->connector.dev; 1265 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1266 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1267 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1268 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1269 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1270 VC4_HDMI_VERTA_VSP) | 1271 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1272 VC4_HDMI_VERTA_VFP) | 1273 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1274 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1275 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1276 interlaced, 1277 VC4_HDMI_VERTB_VBP)); 1278 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1279 VC4_SET_FIELD(mode->crtc_vtotal - 1280 mode->crtc_vsync_end, 1281 VC4_HDMI_VERTB_VBP)); 1282 unsigned long flags; 1283 u32 reg; 1284 int idx; 1285 1286 if (!drm_dev_enter(drm, &idx)) 1287 return; 1288 1289 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1290 1291 HDMI_WRITE(HDMI_HORZA, 1292 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1293 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1294 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1295 VC4_HDMI_HORZA_HAP)); 1296 1297 HDMI_WRITE(HDMI_HORZB, 1298 VC4_SET_FIELD((mode->htotal - 1299 mode->hsync_end) * pixel_rep, 1300 VC4_HDMI_HORZB_HBP) | 1301 VC4_SET_FIELD((mode->hsync_end - 1302 mode->hsync_start) * pixel_rep, 1303 VC4_HDMI_HORZB_HSP) | 1304 VC4_SET_FIELD((mode->hsync_start - 1305 mode->hdisplay) * pixel_rep, 1306 VC4_HDMI_HORZB_HFP)); 1307 1308 HDMI_WRITE(HDMI_VERTA0, verta); 1309 HDMI_WRITE(HDMI_VERTA1, verta); 1310 1311 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1312 HDMI_WRITE(HDMI_VERTB1, vertb); 1313 1314 reg = HDMI_READ(HDMI_MISC_CONTROL); 1315 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1316 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1317 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1318 1319 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1320 1321 drm_dev_exit(idx); 1322 } 1323 1324 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1325 struct drm_connector_state *state, 1326 const struct drm_display_mode *mode) 1327 { 1328 struct drm_device *drm = vc4_hdmi->connector.dev; 1329 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1330 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1331 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1332 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1333 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1334 VC5_HDMI_VERTA_VSP) | 1335 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1336 VC5_HDMI_VERTA_VFP) | 1337 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1338 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1339 VC5_HDMI_VERTB_VSPO) | 1340 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1341 interlaced, 1342 VC4_HDMI_VERTB_VBP)); 1343 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1344 VC4_SET_FIELD(mode->crtc_vtotal - 1345 mode->crtc_vsync_end, 1346 VC4_HDMI_VERTB_VBP)); 1347 unsigned long flags; 1348 unsigned char gcp; 1349 u32 reg; 1350 int idx; 1351 1352 if (!drm_dev_enter(drm, &idx)) 1353 return; 1354 1355 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1356 1357 HDMI_WRITE(HDMI_HORZA, 1358 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1359 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1360 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1361 VC5_HDMI_HORZA_HAP) | 1362 VC4_SET_FIELD((mode->hsync_start - 1363 mode->hdisplay) * pixel_rep, 1364 VC5_HDMI_HORZA_HFP)); 1365 1366 HDMI_WRITE(HDMI_HORZB, 1367 VC4_SET_FIELD((mode->htotal - 1368 mode->hsync_end) * pixel_rep, 1369 VC5_HDMI_HORZB_HBP) | 1370 VC4_SET_FIELD((mode->hsync_end - 1371 mode->hsync_start) * pixel_rep, 1372 VC5_HDMI_HORZB_HSP)); 1373 1374 HDMI_WRITE(HDMI_VERTA0, verta); 1375 HDMI_WRITE(HDMI_VERTA1, verta); 1376 1377 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1378 HDMI_WRITE(HDMI_VERTB1, vertb); 1379 1380 switch (state->hdmi.output_bpc) { 1381 case 12: 1382 gcp = 6; 1383 break; 1384 case 10: 1385 gcp = 5; 1386 break; 1387 case 8: 1388 default: 1389 gcp = 0; 1390 break; 1391 } 1392 1393 /* 1394 * YCC422 is always 36-bit and not considered deep colour so 1395 * doesn't signal in GCP. 1396 */ 1397 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) { 1398 gcp = 0; 1399 } 1400 1401 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1402 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1403 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1404 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1405 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1406 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1407 1408 reg = HDMI_READ(HDMI_GCP_WORD_1); 1409 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1410 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1411 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK; 1412 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE; 1413 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1414 1415 reg = HDMI_READ(HDMI_GCP_CONFIG); 1416 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1417 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1418 1419 reg = HDMI_READ(HDMI_MISC_CONTROL); 1420 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1421 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1422 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1423 1424 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1425 1426 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1427 1428 drm_dev_exit(idx); 1429 } 1430 1431 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1432 { 1433 struct drm_device *drm = vc4_hdmi->connector.dev; 1434 unsigned long flags; 1435 u32 drift; 1436 int ret; 1437 int idx; 1438 1439 if (!drm_dev_enter(drm, &idx)) 1440 return; 1441 1442 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1443 1444 drift = HDMI_READ(HDMI_FIFO_CTL); 1445 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1446 1447 HDMI_WRITE(HDMI_FIFO_CTL, 1448 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1449 HDMI_WRITE(HDMI_FIFO_CTL, 1450 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1451 1452 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1453 1454 usleep_range(1000, 1100); 1455 1456 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1457 1458 HDMI_WRITE(HDMI_FIFO_CTL, 1459 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1460 HDMI_WRITE(HDMI_FIFO_CTL, 1461 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1462 1463 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1464 1465 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1466 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1467 WARN_ONCE(ret, "Timeout waiting for " 1468 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1469 1470 drm_dev_exit(idx); 1471 } 1472 1473 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1474 struct drm_atomic_state *state) 1475 { 1476 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1477 struct drm_device *drm = vc4_hdmi->connector.dev; 1478 struct drm_connector *connector = &vc4_hdmi->connector; 1479 struct drm_connector_state *conn_state = 1480 drm_atomic_get_new_connector_state(state, connector); 1481 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1482 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate; 1483 unsigned long bvb_rate, hsm_rate; 1484 unsigned long flags; 1485 int ret; 1486 int idx; 1487 1488 mutex_lock(&vc4_hdmi->mutex); 1489 1490 if (!drm_dev_enter(drm, &idx)) 1491 goto out; 1492 1493 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1494 if (ret < 0) { 1495 drm_err(drm, "Failed to retain power domain: %d\n", ret); 1496 goto err_dev_exit; 1497 } 1498 1499 /* 1500 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1501 * be faster than pixel clock, infinitesimally faster, tested in 1502 * simulation. Otherwise, exact value is unimportant for HDMI 1503 * operation." This conflicts with bcm2835's vc4 documentation, which 1504 * states HSM's clock has to be at least 108% of the pixel clock. 1505 * 1506 * Real life tests reveal that vc4's firmware statement holds up, and 1507 * users are able to use pixel clocks closer to HSM's, namely for 1508 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1509 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1510 * 162MHz. 1511 * 1512 * Additionally, the AXI clock needs to be at least 25% of 1513 * pixel clock, but HSM ends up being the limiting factor. 1514 */ 1515 hsm_rate = max_t(unsigned long, 1516 HSM_MIN_CLOCK_FREQ, 1517 div_u64(tmds_char_rate, 100) * 101); 1518 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1519 if (ret) { 1520 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret); 1521 goto err_put_runtime_pm; 1522 } 1523 1524 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1525 if (ret) { 1526 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret); 1527 goto err_put_runtime_pm; 1528 } 1529 1530 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1531 if (ret) { 1532 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret); 1533 goto err_put_runtime_pm; 1534 } 1535 1536 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1537 1538 if (tmds_char_rate > 297000000) 1539 bvb_rate = 300000000; 1540 else if (tmds_char_rate > 148500000) 1541 bvb_rate = 150000000; 1542 else 1543 bvb_rate = 75000000; 1544 1545 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1546 if (ret) { 1547 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret); 1548 goto err_disable_pixel_clock; 1549 } 1550 1551 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1552 if (ret) { 1553 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret); 1554 goto err_disable_pixel_clock; 1555 } 1556 1557 if (vc4_hdmi->variant->phy_init) 1558 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state); 1559 1560 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1561 1562 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1563 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1564 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1565 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1566 1567 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1568 1569 if (vc4_hdmi->variant->set_timings) 1570 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1571 1572 drm_dev_exit(idx); 1573 1574 mutex_unlock(&vc4_hdmi->mutex); 1575 1576 return; 1577 1578 err_disable_pixel_clock: 1579 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1580 err_put_runtime_pm: 1581 pm_runtime_put(&vc4_hdmi->pdev->dev); 1582 err_dev_exit: 1583 drm_dev_exit(idx); 1584 out: 1585 mutex_unlock(&vc4_hdmi->mutex); 1586 return; 1587 } 1588 1589 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1590 struct drm_atomic_state *state) 1591 { 1592 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1593 struct drm_device *drm = vc4_hdmi->connector.dev; 1594 struct drm_connector *connector = &vc4_hdmi->connector; 1595 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1596 struct drm_connector_state *conn_state = 1597 drm_atomic_get_new_connector_state(state, connector); 1598 unsigned long flags; 1599 int idx; 1600 1601 mutex_lock(&vc4_hdmi->mutex); 1602 1603 if (!drm_dev_enter(drm, &idx)) 1604 goto out; 1605 1606 if (vc4_hdmi->variant->csc_setup) 1607 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1608 1609 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1610 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1611 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1612 1613 drm_dev_exit(idx); 1614 1615 out: 1616 mutex_unlock(&vc4_hdmi->mutex); 1617 } 1618 1619 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1620 struct drm_atomic_state *state) 1621 { 1622 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1623 struct drm_connector *connector = &vc4_hdmi->connector; 1624 struct drm_device *drm = connector->dev; 1625 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1626 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1627 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1628 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1629 unsigned long flags; 1630 int ret; 1631 int idx; 1632 1633 mutex_lock(&vc4_hdmi->mutex); 1634 1635 if (!drm_dev_enter(drm, &idx)) 1636 goto out; 1637 1638 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1639 1640 HDMI_WRITE(HDMI_VID_CTL, 1641 (HDMI_READ(HDMI_VID_CTL) & 1642 ~(VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) | 1643 VC4_HD_VID_CTL_ENABLE | 1644 VC4_HD_VID_CTL_CLRRGB | 1645 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1646 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1647 VC4_HD_VID_CTL_BLANK_INSERT_EN | 1648 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1649 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1650 1651 HDMI_WRITE(HDMI_VID_CTL, 1652 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1653 1654 if (display->is_hdmi) { 1655 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1656 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1657 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1658 1659 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1660 1661 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1662 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1663 WARN_ONCE(ret, "Timeout waiting for " 1664 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1665 } else { 1666 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1667 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1668 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1669 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1670 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1671 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1672 1673 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1674 1675 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1676 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1677 WARN_ONCE(ret, "Timeout waiting for " 1678 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1679 } 1680 1681 if (display->is_hdmi) { 1682 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1683 1684 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1685 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1686 1687 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1688 VC4_HDMI_RAM_PACKET_ENABLE); 1689 1690 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1691 vc4_hdmi->packet_ram_enabled = true; 1692 1693 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 1694 } 1695 1696 vc4_hdmi_recenter_fifo(vc4_hdmi); 1697 vc4_hdmi_enable_scrambling(encoder); 1698 1699 drm_dev_exit(idx); 1700 1701 out: 1702 mutex_unlock(&vc4_hdmi->mutex); 1703 } 1704 1705 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1706 struct drm_crtc_state *crtc_state, 1707 struct drm_connector_state *conn_state) 1708 { 1709 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1710 1711 mutex_lock(&vc4_hdmi->mutex); 1712 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1713 &crtc_state->adjusted_mode); 1714 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc; 1715 vc4_hdmi->output_format = conn_state->hdmi.output_format; 1716 mutex_unlock(&vc4_hdmi->mutex); 1717 } 1718 1719 static enum drm_mode_status 1720 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector, 1721 const struct drm_display_mode *mode, 1722 unsigned long long clock) 1723 { 1724 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1725 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 1726 1727 if (clock > vc4_hdmi->variant->max_pixel_clock) 1728 return MODE_CLOCK_HIGH; 1729 1730 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 1731 return MODE_CLOCK_HIGH; 1732 1733 /* 4096x2160@60 is not reliable without overclocking core */ 1734 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 1735 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 1736 drm_mode_vrefresh(mode) >= 50) 1737 return MODE_CLOCK_HIGH; 1738 1739 return MODE_OK; 1740 } 1741 1742 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = { 1743 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid, 1744 .avi = { 1745 .clear_infoframe = vc4_hdmi_clear_avi_infoframe, 1746 .write_infoframe = vc4_hdmi_write_avi_infoframe, 1747 }, 1748 .hdmi = { 1749 .clear_infoframe = vc4_hdmi_clear_hdmi_infoframe, 1750 .write_infoframe = vc4_hdmi_write_hdmi_infoframe, 1751 }, 1752 .audio = { 1753 .clear_infoframe = vc4_hdmi_clear_audio_infoframe, 1754 .write_infoframe = vc4_hdmi_write_audio_infoframe, 1755 }, 1756 .hdr_drm = { 1757 .clear_infoframe = vc4_hdmi_clear_hdr_drm_infoframe, 1758 .write_infoframe = vc4_hdmi_write_hdr_drm_infoframe, 1759 }, 1760 .spd = { 1761 .clear_infoframe = vc4_hdmi_clear_spd_infoframe, 1762 .write_infoframe = vc4_hdmi_write_spd_infoframe, 1763 }, 1764 }; 1765 1766 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1767 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1768 1769 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1770 struct drm_crtc_state *crtc_state, 1771 struct drm_connector_state *conn_state) 1772 { 1773 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1774 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1775 unsigned long long tmds_char_rate = mode->clock * 1000; 1776 unsigned long long tmds_bit_rate; 1777 1778 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1779 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1780 /* Only try to fixup DBLCLK modes to get 480i and 576i 1781 * working. 1782 * A generic solution for all modes with odd horizontal 1783 * timing values seems impossible based on trying to 1784 * solve it for 1366x768 monitors. 1785 */ 1786 if ((mode->hsync_start - mode->hdisplay) & 1) 1787 mode->hsync_start--; 1788 if ((mode->hsync_end - mode->hsync_start) & 1) 1789 mode->hsync_end--; 1790 } 1791 1792 /* Now check whether we still have odd values remaining */ 1793 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1794 (mode->hsync_end % 2) || (mode->htotal % 2)) 1795 return -EINVAL; 1796 } 1797 1798 /* 1799 * The 1440p@60 pixel rate is in the same range than the first 1800 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1801 * bandwidth). Slightly lower the frequency to bring it out of 1802 * the WiFi range. 1803 */ 1804 tmds_bit_rate = tmds_char_rate * 10; 1805 if (vc4_hdmi->disable_wifi_frequencies && 1806 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1807 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1808 mode->clock = 238560; 1809 tmds_char_rate = mode->clock * 1000; 1810 } 1811 1812 return 0; 1813 } 1814 1815 static enum drm_mode_status 1816 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1817 const struct drm_display_mode *mode) 1818 { 1819 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1820 1821 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1822 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1823 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1824 (mode->hsync_end % 2) || (mode->htotal % 2))) 1825 return MODE_H_ILLEGAL; 1826 1827 return MODE_OK; 1828 } 1829 1830 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1831 .atomic_check = vc4_hdmi_encoder_atomic_check, 1832 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1833 .mode_valid = vc4_hdmi_encoder_mode_valid, 1834 }; 1835 1836 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 1837 { 1838 struct drm_device *drm = encoder->dev; 1839 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1840 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1841 1842 drm_debugfs_add_file(drm, variant->debugfs_name, 1843 vc4_hdmi_debugfs_regs, vc4_hdmi); 1844 1845 return 0; 1846 } 1847 1848 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 1849 .late_register = vc4_hdmi_late_register, 1850 }; 1851 1852 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1853 { 1854 int i; 1855 u32 channel_map = 0; 1856 1857 for (i = 0; i < 8; i++) { 1858 if (channel_mask & BIT(i)) 1859 channel_map |= i << (3 * i); 1860 } 1861 return channel_map; 1862 } 1863 1864 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1865 { 1866 int i; 1867 u32 channel_map = 0; 1868 1869 for (i = 0; i < 8; i++) { 1870 if (channel_mask & BIT(i)) 1871 channel_map |= i << (4 * i); 1872 } 1873 return channel_map; 1874 } 1875 1876 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1877 { 1878 struct drm_device *drm = vc4_hdmi->connector.dev; 1879 unsigned long flags; 1880 u32 hotplug; 1881 int idx; 1882 1883 if (!drm_dev_enter(drm, &idx)) 1884 return false; 1885 1886 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1887 hotplug = HDMI_READ(HDMI_HOTPLUG); 1888 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1889 1890 drm_dev_exit(idx); 1891 1892 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1893 } 1894 1895 /* HDMI audio codec callbacks */ 1896 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1897 unsigned int samplerate) 1898 { 1899 struct drm_device *drm = vc4_hdmi->connector.dev; 1900 u32 hsm_clock; 1901 unsigned long flags; 1902 unsigned long n, m; 1903 int idx; 1904 1905 if (!drm_dev_enter(drm, &idx)) 1906 return; 1907 1908 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1909 rational_best_approximation(hsm_clock, samplerate, 1910 VC4_HD_MAI_SMP_N_MASK >> 1911 VC4_HD_MAI_SMP_N_SHIFT, 1912 (VC4_HD_MAI_SMP_M_MASK >> 1913 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1914 &n, &m); 1915 1916 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1917 HDMI_WRITE(HDMI_MAI_SMP, 1918 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1919 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1920 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1921 1922 drm_dev_exit(idx); 1923 } 1924 1925 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1926 { 1927 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1928 u32 n, cts; 1929 u64 tmp; 1930 1931 lockdep_assert_held(&vc4_hdmi->mutex); 1932 lockdep_assert_held(&vc4_hdmi->hw_lock); 1933 1934 n = 128 * samplerate / 1000; 1935 tmp = (u64)(mode->clock * 1000) * n; 1936 do_div(tmp, 128 * samplerate); 1937 cts = tmp; 1938 1939 HDMI_WRITE(HDMI_CRP_CFG, 1940 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1941 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1942 1943 /* 1944 * We could get slightly more accurate clocks in some cases by 1945 * providing a CTS_1 value. The two CTS values are alternated 1946 * between based on the period fields 1947 */ 1948 HDMI_WRITE(HDMI_CTS_0, cts); 1949 HDMI_WRITE(HDMI_CTS_1, cts); 1950 } 1951 1952 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1953 { 1954 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1955 1956 return snd_soc_card_get_drvdata(card); 1957 } 1958 1959 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1960 { 1961 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1962 1963 lockdep_assert_held(&vc4_hdmi->mutex); 1964 1965 /* 1966 * If the encoder is currently in DVI mode, treat the codec DAI 1967 * as missing. 1968 */ 1969 if (!display->is_hdmi) 1970 return false; 1971 1972 return true; 1973 } 1974 1975 static int vc4_hdmi_audio_startup(struct drm_connector *connector) 1976 { 1977 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1978 struct drm_device *drm = vc4_hdmi->connector.dev; 1979 unsigned long flags; 1980 int ret = 0; 1981 int idx; 1982 1983 mutex_lock(&vc4_hdmi->mutex); 1984 1985 if (!drm_dev_enter(drm, &idx)) { 1986 ret = -ENODEV; 1987 goto out; 1988 } 1989 1990 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1991 ret = -ENOTSUPP; 1992 goto out_dev_exit; 1993 } 1994 1995 vc4_hdmi->audio.streaming = true; 1996 1997 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1998 HDMI_WRITE(HDMI_MAI_CTL, 1999 VC4_HD_MAI_CTL_RESET | 2000 VC4_HD_MAI_CTL_FLUSH | 2001 VC4_HD_MAI_CTL_DLATE | 2002 VC4_HD_MAI_CTL_ERRORE | 2003 VC4_HD_MAI_CTL_ERRORF); 2004 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2005 2006 if (vc4_hdmi->variant->phy_rng_enable) 2007 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 2008 2009 out_dev_exit: 2010 drm_dev_exit(idx); 2011 out: 2012 mutex_unlock(&vc4_hdmi->mutex); 2013 2014 return ret; 2015 } 2016 2017 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 2018 { 2019 struct device *dev = &vc4_hdmi->pdev->dev; 2020 unsigned long flags; 2021 int ret; 2022 2023 lockdep_assert_held(&vc4_hdmi->mutex); 2024 2025 vc4_hdmi->audio.streaming = false; 2026 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false); 2027 if (ret) 2028 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 2029 2030 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2031 2032 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 2033 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 2034 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 2035 2036 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2037 } 2038 2039 static void vc4_hdmi_audio_shutdown(struct drm_connector *connector) 2040 { 2041 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2042 struct drm_device *drm = vc4_hdmi->connector.dev; 2043 unsigned long flags; 2044 int idx; 2045 2046 mutex_lock(&vc4_hdmi->mutex); 2047 2048 if (!drm_dev_enter(drm, &idx)) 2049 goto out; 2050 2051 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2052 2053 HDMI_WRITE(HDMI_MAI_CTL, 2054 VC4_HD_MAI_CTL_DLATE | 2055 VC4_HD_MAI_CTL_ERRORE | 2056 VC4_HD_MAI_CTL_ERRORF); 2057 2058 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2059 2060 if (vc4_hdmi->variant->phy_rng_disable) 2061 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 2062 2063 vc4_hdmi->audio.streaming = false; 2064 vc4_hdmi_audio_reset(vc4_hdmi); 2065 2066 drm_dev_exit(idx); 2067 2068 out: 2069 mutex_unlock(&vc4_hdmi->mutex); 2070 } 2071 2072 static int sample_rate_to_mai_fmt(int samplerate) 2073 { 2074 switch (samplerate) { 2075 case 8000: 2076 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2077 case 11025: 2078 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2079 case 12000: 2080 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2081 case 16000: 2082 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2083 case 22050: 2084 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2085 case 24000: 2086 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2087 case 32000: 2088 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2089 case 44100: 2090 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2091 case 48000: 2092 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2093 case 64000: 2094 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2095 case 88200: 2096 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2097 case 96000: 2098 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2099 case 128000: 2100 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2101 case 176400: 2102 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2103 case 192000: 2104 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2105 default: 2106 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2107 } 2108 } 2109 2110 /* HDMI audio codec callbacks */ 2111 static int vc4_hdmi_audio_prepare(struct drm_connector *connector, 2112 struct hdmi_codec_daifmt *daifmt, 2113 struct hdmi_codec_params *params) 2114 { 2115 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2116 struct drm_device *drm = vc4_hdmi->connector.dev; 2117 struct vc4_dev *vc4 = to_vc4_dev(drm); 2118 unsigned int sample_rate = params->sample_rate; 2119 unsigned int channels = params->channels; 2120 unsigned long flags; 2121 u32 audio_packet_config, channel_mask; 2122 u32 channel_map; 2123 u32 mai_audio_format; 2124 u32 mai_sample_rate; 2125 int ret = 0; 2126 int idx; 2127 2128 dev_dbg(&vc4_hdmi->pdev->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2129 sample_rate, params->sample_width, channels); 2130 2131 mutex_lock(&vc4_hdmi->mutex); 2132 2133 if (!drm_dev_enter(drm, &idx)) { 2134 ret = -ENODEV; 2135 goto out; 2136 } 2137 2138 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2139 ret = -EINVAL; 2140 goto out_dev_exit; 2141 } 2142 2143 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2144 2145 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2146 HDMI_WRITE(HDMI_MAI_CTL, 2147 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2148 VC4_HD_MAI_CTL_WHOLSMP | 2149 VC4_HD_MAI_CTL_CHALIGN | 2150 VC4_HD_MAI_CTL_ENABLE); 2151 2152 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2153 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2154 params->channels == 8) 2155 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2156 else 2157 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2158 HDMI_WRITE(HDMI_MAI_FMT, 2159 VC4_SET_FIELD(mai_sample_rate, 2160 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2161 VC4_SET_FIELD(mai_audio_format, 2162 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2163 2164 /* The B frame identifier should match the value used by alsa-lib (8) */ 2165 audio_packet_config = 2166 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2167 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2168 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2169 2170 channel_mask = GENMASK(channels - 1, 0); 2171 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2172 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2173 2174 /* Set the MAI threshold */ 2175 switch (vc4->gen) { 2176 case VC4_GEN_6_D: 2177 HDMI_WRITE(HDMI_MAI_THR, 2178 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) | 2179 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) | 2180 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) | 2181 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW)); 2182 break; 2183 case VC4_GEN_6_C: 2184 case VC4_GEN_5: 2185 HDMI_WRITE(HDMI_MAI_THR, 2186 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 2187 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 2188 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) | 2189 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW)); 2190 break; 2191 case VC4_GEN_4: 2192 HDMI_WRITE(HDMI_MAI_THR, 2193 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) | 2194 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) | 2195 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) | 2196 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW)); 2197 break; 2198 default: 2199 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen); 2200 break; 2201 } 2202 2203 HDMI_WRITE(HDMI_MAI_CONFIG, 2204 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2205 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2206 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2207 2208 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2209 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2210 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2211 2212 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2213 2214 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2215 2216 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, 2217 ¶ms->cea); 2218 if (ret) 2219 goto out_dev_exit; 2220 2221 out_dev_exit: 2222 drm_dev_exit(idx); 2223 out: 2224 mutex_unlock(&vc4_hdmi->mutex); 2225 2226 return ret; 2227 } 2228 2229 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2230 .name = "vc4-hdmi-cpu-dai-component", 2231 .legacy_dai_naming = 1, 2232 }; 2233 2234 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2235 { 2236 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2237 2238 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2239 2240 return 0; 2241 } 2242 2243 static const struct snd_soc_dai_ops vc4_snd_dai_ops = { 2244 .probe = vc4_hdmi_audio_cpu_dai_probe, 2245 }; 2246 2247 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2248 .name = "vc4-hdmi-cpu-dai", 2249 .ops = &vc4_snd_dai_ops, 2250 .playback = { 2251 .stream_name = "Playback", 2252 .channels_min = 1, 2253 .channels_max = 8, 2254 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2255 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2256 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2257 SNDRV_PCM_RATE_192000, 2258 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2259 }, 2260 }; 2261 2262 static const struct snd_dmaengine_pcm_config pcm_conf = { 2263 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2264 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2265 }; 2266 2267 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs = { 2268 .startup = vc4_hdmi_audio_startup, 2269 .prepare = vc4_hdmi_audio_prepare, 2270 .shutdown = vc4_hdmi_audio_shutdown, 2271 }; 2272 2273 static int vc4_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd) 2274 { 2275 struct vc4_hdmi *vc4_hdmi = snd_soc_card_get_drvdata(rtd->card); 2276 struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component; 2277 int ret; 2278 2279 ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT, 2280 &vc4_hdmi->hdmi_jack); 2281 if (ret) { 2282 dev_err(rtd->dev, "HDMI Jack creation failed: %d\n", ret); 2283 return ret; 2284 } 2285 2286 return snd_soc_component_set_jack(component, &vc4_hdmi->hdmi_jack, NULL); 2287 } 2288 2289 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2290 { 2291 const struct vc4_hdmi_register *mai_data = 2292 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2293 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2294 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2295 struct device *dev = &vc4_hdmi->pdev->dev; 2296 const __be32 *addr; 2297 int index, len; 2298 int ret; 2299 2300 /* 2301 * ASoC makes it a bit hard to retrieve a pointer to the 2302 * vc4_hdmi structure. Registering the card will overwrite our 2303 * device drvdata with a pointer to the snd_soc_card structure, 2304 * which can then be used to retrieve whatever drvdata we want 2305 * to associate. 2306 * 2307 * However, that doesn't fly in the case where we wouldn't 2308 * register an ASoC card (because of an old DT that is missing 2309 * the dmas properties for example), then the card isn't 2310 * registered and the device drvdata wouldn't be set. 2311 * 2312 * We can deal with both cases by making sure a snd_soc_card 2313 * pointer and a vc4_hdmi structure are pointing to the same 2314 * memory address, so we can treat them indistinctly without any 2315 * issue. 2316 */ 2317 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2318 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2319 2320 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2321 dev_warn(dev, 2322 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2323 return 0; 2324 } 2325 2326 if (mai_data->reg != VC4_HD) { 2327 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2328 return -EINVAL; 2329 } 2330 2331 /* 2332 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2333 * the bus address specified in the DT, because the physical address 2334 * (the one returned by platform_get_resource()) is not appropriate 2335 * for DMA transfers. 2336 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2337 */ 2338 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2339 /* Before BCM2711, we don't have a named register range */ 2340 if (index < 0) 2341 index = 1; 2342 2343 addr = of_get_address(dev->of_node, index, NULL, NULL); 2344 if (!addr) 2345 return -EINVAL; 2346 2347 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2348 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2349 vc4_hdmi->audio.dma_data.maxburst = 2; 2350 2351 /* 2352 * NOTE: Strictly speaking, we should probably use a DRM-managed 2353 * registration there to avoid removing all the audio components 2354 * by the time the driver doesn't have any user anymore. 2355 * 2356 * However, the ASoC core uses a number of devm_kzalloc calls 2357 * when registering, even when using non-device-managed 2358 * functions (such as in snd_soc_register_component()). 2359 * 2360 * If we call snd_soc_unregister_component() in a DRM-managed 2361 * action, the device-managed actions have already been executed 2362 * and thus we would access memory that has been freed. 2363 * 2364 * Using device-managed hooks here probably leaves us open to a 2365 * bunch of issues if userspace still has a handle on the ALSA 2366 * device when the device is removed. However, this is mitigated 2367 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2368 * path to prevent the access to the device resources if it 2369 * isn't there anymore. 2370 * 2371 * Then, the vc4_hdmi structure is DRM-managed and thus only 2372 * freed whenever the last user has closed the DRM device file. 2373 * It should thus outlive ALSA in most situations. 2374 */ 2375 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2376 if (ret) { 2377 dev_err(dev, "Could not register PCM component: %d\n", ret); 2378 return ret; 2379 } 2380 2381 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2382 &vc4_hdmi_audio_cpu_dai_drv, 1); 2383 if (ret) { 2384 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2385 return ret; 2386 } 2387 2388 ret = drm_connector_hdmi_audio_init(&vc4_hdmi->connector, dev, 2389 &vc4_hdmi_audio_funcs, 8, 0, false, 2390 -1); 2391 if (ret) 2392 return ret; 2393 2394 dai_link->cpus = &vc4_hdmi->audio.cpu; 2395 dai_link->codecs = &vc4_hdmi->audio.codec; 2396 dai_link->platforms = &vc4_hdmi->audio.platform; 2397 2398 dai_link->num_cpus = 1; 2399 dai_link->num_codecs = 1; 2400 dai_link->num_platforms = 1; 2401 2402 dai_link->name = "MAI"; 2403 dai_link->stream_name = "MAI PCM"; 2404 dai_link->codecs->dai_name = "i2s-hifi"; 2405 dai_link->cpus->dai_name = dev_name(dev); 2406 dai_link->codecs->name = dev_name(&vc4_hdmi->connector.hdmi_audio.codec_pdev->dev); 2407 dai_link->platforms->name = dev_name(dev); 2408 dai_link->init = vc4_hdmi_codec_init; 2409 2410 card->dai_link = dai_link; 2411 card->num_links = 1; 2412 card->name = vc4_hdmi->variant->card_name; 2413 card->driver_name = "vc4-hdmi"; 2414 card->dev = dev; 2415 card->owner = THIS_MODULE; 2416 2417 /* 2418 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2419 * stores a pointer to the snd card object in dev->driver_data. This 2420 * means we cannot use it for something else. The hdmi back-pointer is 2421 * now stored in card->drvdata and should be retrieved with 2422 * snd_soc_card_get_drvdata() if needed. 2423 */ 2424 snd_soc_card_set_drvdata(card, vc4_hdmi); 2425 ret = devm_snd_soc_register_card(dev, card); 2426 if (ret) 2427 dev_err_probe(dev, ret, "Could not register sound card\n"); 2428 2429 return ret; 2430 2431 } 2432 2433 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2434 { 2435 struct vc4_hdmi *vc4_hdmi = priv; 2436 struct drm_connector *connector = &vc4_hdmi->connector; 2437 struct drm_device *dev = connector->dev; 2438 2439 if (dev && dev->registered) 2440 drm_connector_helper_hpd_irq_event(connector); 2441 2442 return IRQ_HANDLED; 2443 } 2444 2445 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2446 { 2447 struct drm_connector *connector = &vc4_hdmi->connector; 2448 struct platform_device *pdev = vc4_hdmi->pdev; 2449 int ret; 2450 2451 if (vc4_hdmi->variant->external_irq_controller) { 2452 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2453 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2454 2455 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2456 NULL, 2457 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2458 "vc4 hdmi hpd connected", vc4_hdmi); 2459 if (ret) 2460 return ret; 2461 2462 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2463 NULL, 2464 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2465 "vc4 hdmi hpd disconnected", vc4_hdmi); 2466 if (ret) 2467 return ret; 2468 2469 connector->polled = DRM_CONNECTOR_POLL_HPD; 2470 } 2471 2472 return 0; 2473 } 2474 2475 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2476 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2477 { 2478 struct vc4_hdmi *vc4_hdmi = priv; 2479 2480 if (vc4_hdmi->cec_rx_msg.len) 2481 drm_connector_hdmi_cec_received_msg(&vc4_hdmi->connector, 2482 &vc4_hdmi->cec_rx_msg); 2483 2484 return IRQ_HANDLED; 2485 } 2486 2487 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2488 { 2489 struct vc4_hdmi *vc4_hdmi = priv; 2490 2491 if (vc4_hdmi->cec_tx_ok) { 2492 drm_connector_hdmi_cec_transmit_done(&vc4_hdmi->connector, 2493 CEC_TX_STATUS_OK, 2494 0, 0, 0, 0); 2495 } else { 2496 /* 2497 * This CEC implementation makes 1 retry, so if we 2498 * get a NACK, then that means it made 2 attempts. 2499 */ 2500 drm_connector_hdmi_cec_transmit_done(&vc4_hdmi->connector, 2501 CEC_TX_STATUS_NACK, 2502 0, 2, 0, 0); 2503 } 2504 return IRQ_HANDLED; 2505 } 2506 2507 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2508 { 2509 struct vc4_hdmi *vc4_hdmi = priv; 2510 irqreturn_t ret; 2511 2512 if (vc4_hdmi->cec_irq_was_rx) 2513 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2514 else 2515 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2516 2517 return ret; 2518 } 2519 2520 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2521 { 2522 struct drm_device *dev = vc4_hdmi->connector.dev; 2523 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2524 unsigned int i; 2525 2526 lockdep_assert_held(&vc4_hdmi->hw_lock); 2527 2528 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2529 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2530 2531 if (msg->len > 16) { 2532 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2533 return; 2534 } 2535 2536 for (i = 0; i < msg->len; i += 4) { 2537 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2538 2539 msg->msg[i] = val & 0xff; 2540 msg->msg[i + 1] = (val >> 8) & 0xff; 2541 msg->msg[i + 2] = (val >> 16) & 0xff; 2542 msg->msg[i + 3] = (val >> 24) & 0xff; 2543 } 2544 } 2545 2546 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2547 { 2548 u32 cntrl1; 2549 2550 /* 2551 * We don't need to protect the register access using 2552 * drm_dev_enter() there because the interrupt handler lifetime 2553 * is tied to the device itself, and not to the DRM device. 2554 * 2555 * So when the device will be gone, one of the first thing we 2556 * will be doing will be to unregister the interrupt handler, 2557 * and then unregister the DRM device. drm_dev_enter() would 2558 * thus always succeed if we are here. 2559 */ 2560 2561 lockdep_assert_held(&vc4_hdmi->hw_lock); 2562 2563 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2564 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2565 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2566 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2567 2568 return IRQ_WAKE_THREAD; 2569 } 2570 2571 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2572 { 2573 struct vc4_hdmi *vc4_hdmi = priv; 2574 irqreturn_t ret; 2575 2576 spin_lock(&vc4_hdmi->hw_lock); 2577 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2578 spin_unlock(&vc4_hdmi->hw_lock); 2579 2580 return ret; 2581 } 2582 2583 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2584 { 2585 u32 cntrl1; 2586 2587 lockdep_assert_held(&vc4_hdmi->hw_lock); 2588 2589 /* 2590 * We don't need to protect the register access using 2591 * drm_dev_enter() there because the interrupt handler lifetime 2592 * is tied to the device itself, and not to the DRM device. 2593 * 2594 * So when the device will be gone, one of the first thing we 2595 * will be doing will be to unregister the interrupt handler, 2596 * and then unregister the DRM device. drm_dev_enter() would 2597 * thus always succeed if we are here. 2598 */ 2599 2600 vc4_hdmi->cec_rx_msg.len = 0; 2601 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2602 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2603 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2604 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2605 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2606 2607 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2608 2609 return IRQ_WAKE_THREAD; 2610 } 2611 2612 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2613 { 2614 struct vc4_hdmi *vc4_hdmi = priv; 2615 irqreturn_t ret; 2616 2617 spin_lock(&vc4_hdmi->hw_lock); 2618 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2619 spin_unlock(&vc4_hdmi->hw_lock); 2620 2621 return ret; 2622 } 2623 2624 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2625 { 2626 struct vc4_hdmi *vc4_hdmi = priv; 2627 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2628 irqreturn_t ret; 2629 u32 cntrl5; 2630 2631 /* 2632 * We don't need to protect the register access using 2633 * drm_dev_enter() there because the interrupt handler lifetime 2634 * is tied to the device itself, and not to the DRM device. 2635 * 2636 * So when the device will be gone, one of the first thing we 2637 * will be doing will be to unregister the interrupt handler, 2638 * and then unregister the DRM device. drm_dev_enter() would 2639 * thus always succeed if we are here. 2640 */ 2641 2642 if (!(stat & VC4_HDMI_CPU_CEC)) 2643 return IRQ_NONE; 2644 2645 spin_lock(&vc4_hdmi->hw_lock); 2646 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2647 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2648 if (vc4_hdmi->cec_irq_was_rx) 2649 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2650 else 2651 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2652 2653 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2654 spin_unlock(&vc4_hdmi->hw_lock); 2655 2656 return ret; 2657 } 2658 2659 static int vc4_hdmi_cec_enable(struct drm_connector *connector) 2660 { 2661 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2662 struct drm_device *drm = vc4_hdmi->connector.dev; 2663 /* clock period in microseconds */ 2664 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2665 unsigned long flags; 2666 u32 val; 2667 int ret; 2668 int idx; 2669 2670 if (!drm_dev_enter(drm, &idx)) 2671 /* 2672 * We can't return an error code, because the CEC 2673 * framework will emit WARN_ON messages at unbind 2674 * otherwise. 2675 */ 2676 return 0; 2677 2678 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2679 if (ret) { 2680 drm_dev_exit(idx); 2681 return ret; 2682 } 2683 2684 mutex_lock(&vc4_hdmi->mutex); 2685 2686 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2687 2688 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2689 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2690 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2691 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2692 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2693 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2694 2695 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2696 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2697 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2698 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2699 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2700 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2701 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2702 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2703 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2704 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2705 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2706 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2707 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2708 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2709 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2710 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2711 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2712 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2713 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2714 2715 if (!vc4_hdmi->variant->external_irq_controller) 2716 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2717 2718 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2719 2720 mutex_unlock(&vc4_hdmi->mutex); 2721 drm_dev_exit(idx); 2722 2723 return 0; 2724 } 2725 2726 static int vc4_hdmi_cec_disable(struct drm_connector *connector) 2727 { 2728 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2729 struct drm_device *drm = vc4_hdmi->connector.dev; 2730 unsigned long flags; 2731 int idx; 2732 2733 if (!drm_dev_enter(drm, &idx)) 2734 /* 2735 * We can't return an error code, because the CEC 2736 * framework will emit WARN_ON messages at unbind 2737 * otherwise. 2738 */ 2739 return 0; 2740 2741 mutex_lock(&vc4_hdmi->mutex); 2742 2743 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2744 2745 if (!vc4_hdmi->variant->external_irq_controller) 2746 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2747 2748 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2749 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2750 2751 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2752 2753 mutex_unlock(&vc4_hdmi->mutex); 2754 2755 pm_runtime_put(&vc4_hdmi->pdev->dev); 2756 2757 drm_dev_exit(idx); 2758 2759 return 0; 2760 } 2761 2762 static int vc4_hdmi_cec_adap_enable(struct drm_connector *connector, bool enable) 2763 { 2764 if (enable) 2765 return vc4_hdmi_cec_enable(connector); 2766 else 2767 return vc4_hdmi_cec_disable(connector); 2768 } 2769 2770 static int vc4_hdmi_cec_adap_log_addr(struct drm_connector *connector, u8 log_addr) 2771 { 2772 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2773 struct drm_device *drm = vc4_hdmi->connector.dev; 2774 unsigned long flags; 2775 int idx; 2776 2777 if (!drm_dev_enter(drm, &idx)) 2778 /* 2779 * We can't return an error code, because the CEC 2780 * framework will emit WARN_ON messages at unbind 2781 * otherwise. 2782 */ 2783 return 0; 2784 2785 mutex_lock(&vc4_hdmi->mutex); 2786 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2787 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2788 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2789 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2790 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2791 mutex_unlock(&vc4_hdmi->mutex); 2792 2793 drm_dev_exit(idx); 2794 2795 return 0; 2796 } 2797 2798 static int vc4_hdmi_cec_adap_transmit(struct drm_connector *connector, u8 attempts, 2799 u32 signal_free_time, struct cec_msg *msg) 2800 { 2801 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2802 struct drm_device *dev = vc4_hdmi->connector.dev; 2803 unsigned long flags; 2804 u32 val; 2805 unsigned int i; 2806 int idx; 2807 2808 if (!drm_dev_enter(dev, &idx)) 2809 return -ENODEV; 2810 2811 if (msg->len > 16) { 2812 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2813 drm_dev_exit(idx); 2814 return -ENOMEM; 2815 } 2816 2817 mutex_lock(&vc4_hdmi->mutex); 2818 2819 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2820 2821 for (i = 0; i < msg->len; i += 4) 2822 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2823 (msg->msg[i]) | 2824 (msg->msg[i + 1] << 8) | 2825 (msg->msg[i + 2] << 16) | 2826 (msg->msg[i + 3] << 24)); 2827 2828 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2829 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2830 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2831 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2832 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2833 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2834 2835 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2836 2837 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2838 mutex_unlock(&vc4_hdmi->mutex); 2839 drm_dev_exit(idx); 2840 2841 return 0; 2842 } 2843 2844 static int vc4_hdmi_cec_init(struct drm_connector *connector) 2845 { 2846 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2847 struct platform_device *pdev = vc4_hdmi->pdev; 2848 struct device *dev = &pdev->dev; 2849 int ret; 2850 2851 if (vc4_hdmi->variant->external_irq_controller) { 2852 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 2853 vc4_cec_irq_handler_rx_bare, 2854 vc4_cec_irq_handler_rx_thread, 0, 2855 "vc4 hdmi cec rx", vc4_hdmi); 2856 if (ret) 2857 return ret; 2858 2859 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 2860 vc4_cec_irq_handler_tx_bare, 2861 vc4_cec_irq_handler_tx_thread, 0, 2862 "vc4 hdmi cec tx", vc4_hdmi); 2863 if (ret) 2864 return ret; 2865 } else { 2866 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 2867 vc4_cec_irq_handler, 2868 vc4_cec_irq_handler_thread, 0, 2869 "vc4 hdmi cec", vc4_hdmi); 2870 if (ret) 2871 return ret; 2872 } 2873 2874 return 0; 2875 } 2876 2877 static const struct drm_connector_hdmi_cec_funcs vc4_hdmi_cec_funcs = { 2878 .init = vc4_hdmi_cec_init, 2879 .enable = vc4_hdmi_cec_adap_enable, 2880 .log_addr = vc4_hdmi_cec_adap_log_addr, 2881 .transmit = vc4_hdmi_cec_adap_transmit, 2882 }; 2883 2884 static int vc4_hdmi_cec_register(struct vc4_hdmi *vc4_hdmi) 2885 { 2886 struct platform_device *pdev = vc4_hdmi->pdev; 2887 struct device *dev = &pdev->dev; 2888 2889 if (!of_property_present(dev->of_node, "interrupts")) { 2890 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2891 return 0; 2892 } 2893 2894 /* 2895 * NOTE: the CEC adapter will be unregistered by drmm cleanup from 2896 * drm_managed_release(), which is called from drm_dev_release() 2897 * during device unbind. 2898 * 2899 * However, the CEC framework already cleans up the CEC adapter 2900 * only when the last user has closed its file descriptor, so we 2901 * don't need to handle it in DRM. 2902 * 2903 * There's still a problematic sequence: if we unregister our 2904 * CEC adapter, but the userspace keeps a handle on the CEC 2905 * adapter but not the DRM device for some reason. In such a 2906 * case, our vc4_hdmi structure will be freed, but the 2907 * cec_adapter structure will have a dangling pointer to what 2908 * used to be our HDMI controller. If we get a CEC call at that 2909 * moment, we could end up with a use-after-free. Fortunately, 2910 * the CEC framework already handles this too, by calling 2911 * cec_is_registered() in cec_ioctl() and cec_poll(). 2912 */ 2913 return drmm_connector_hdmi_cec_register(&vc4_hdmi->connector, 2914 &vc4_hdmi_cec_funcs, 2915 vc4_hdmi->variant->card_name, 2916 1, 2917 &pdev->dev); 2918 } 2919 #else 2920 static int vc4_hdmi_cec_register(struct vc4_hdmi *vc4_hdmi) 2921 { 2922 return 0; 2923 } 2924 #endif 2925 2926 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 2927 { 2928 struct debugfs_reg32 *regs = ptr; 2929 2930 kfree(regs); 2931 } 2932 2933 static int vc4_hdmi_build_regset(struct drm_device *drm, 2934 struct vc4_hdmi *vc4_hdmi, 2935 struct debugfs_regset32 *regset, 2936 enum vc4_hdmi_regs reg) 2937 { 2938 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2939 struct debugfs_reg32 *regs, *new_regs; 2940 unsigned int count = 0; 2941 unsigned int i; 2942 int ret; 2943 2944 regs = kcalloc(variant->num_registers, sizeof(*regs), 2945 GFP_KERNEL); 2946 if (!regs) 2947 return -ENOMEM; 2948 2949 for (i = 0; i < variant->num_registers; i++) { 2950 const struct vc4_hdmi_register *field = &variant->registers[i]; 2951 2952 if (field->reg != reg) 2953 continue; 2954 2955 regs[count].name = field->name; 2956 regs[count].offset = field->offset; 2957 count++; 2958 } 2959 2960 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2961 if (!new_regs) 2962 return -ENOMEM; 2963 2964 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2965 regset->regs = new_regs; 2966 regset->nregs = count; 2967 2968 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 2969 if (ret) 2970 return ret; 2971 2972 return 0; 2973 } 2974 2975 static int vc4_hdmi_init_resources(struct drm_device *drm, 2976 struct vc4_hdmi *vc4_hdmi) 2977 { 2978 struct platform_device *pdev = vc4_hdmi->pdev; 2979 struct device *dev = &pdev->dev; 2980 int ret; 2981 2982 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2983 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2984 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2985 2986 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2987 if (IS_ERR(vc4_hdmi->hd_regs)) 2988 return PTR_ERR(vc4_hdmi->hd_regs); 2989 2990 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2991 if (ret) 2992 return ret; 2993 2994 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2995 if (ret) 2996 return ret; 2997 2998 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2999 if (IS_ERR(vc4_hdmi->pixel_clock)) { 3000 ret = PTR_ERR(vc4_hdmi->pixel_clock); 3001 if (ret != -EPROBE_DEFER) 3002 drm_err(drm, "Failed to get pixel clock\n"); 3003 return ret; 3004 } 3005 3006 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3007 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3008 drm_err(drm, "Failed to get HDMI state machine clock\n"); 3009 return PTR_ERR(vc4_hdmi->hsm_clock); 3010 } 3011 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 3012 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 3013 3014 return 0; 3015 } 3016 3017 static int vc5_hdmi_init_resources(struct drm_device *drm, 3018 struct vc4_hdmi *vc4_hdmi) 3019 { 3020 struct platform_device *pdev = vc4_hdmi->pdev; 3021 struct device *dev = &pdev->dev; 3022 struct resource *res; 3023 int ret; 3024 3025 vc4_hdmi->hdmicore_regs = devm_platform_ioremap_resource_byname(pdev, 3026 "hdmi"); 3027 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 3028 return PTR_ERR(vc4_hdmi->hdmicore_regs); 3029 3030 /* This is shared between both HDMI controllers. Cannot 3031 * claim for both instances. Lets not convert to using 3032 * devm_platform_ioremap_resource_byname() like 3033 * the rest 3034 */ 3035 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 3036 if (!res) 3037 return -ENODEV; 3038 3039 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 3040 if (!vc4_hdmi->hd_regs) 3041 return -ENOMEM; 3042 3043 vc4_hdmi->cec_regs = devm_platform_ioremap_resource_byname(pdev, 3044 "cec"); 3045 if (IS_ERR(vc4_hdmi->cec_regs)) 3046 return PTR_ERR(vc4_hdmi->cec_regs); 3047 3048 vc4_hdmi->csc_regs = devm_platform_ioremap_resource_byname(pdev, 3049 "csc"); 3050 if (IS_ERR(vc4_hdmi->csc_regs)) 3051 return PTR_ERR(vc4_hdmi->csc_regs); 3052 3053 vc4_hdmi->dvp_regs = devm_platform_ioremap_resource_byname(pdev, 3054 "dvp"); 3055 if (IS_ERR(vc4_hdmi->dvp_regs)) 3056 return PTR_ERR(vc4_hdmi->dvp_regs); 3057 3058 vc4_hdmi->phy_regs = devm_platform_ioremap_resource_byname(pdev, 3059 "phy"); 3060 3061 if (IS_ERR(vc4_hdmi->phy_regs)) 3062 return PTR_ERR(vc4_hdmi->phy_regs); 3063 3064 vc4_hdmi->ram_regs = devm_platform_ioremap_resource_byname(pdev, 3065 "packet"); 3066 if (IS_ERR(vc4_hdmi->ram_regs)) 3067 return PTR_ERR(vc4_hdmi->ram_regs); 3068 3069 vc4_hdmi->rm_regs = devm_platform_ioremap_resource_byname(pdev, "rm"); 3070 if (IS_ERR(vc4_hdmi->rm_regs)) 3071 return PTR_ERR(vc4_hdmi->rm_regs); 3072 3073 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3074 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3075 drm_err(drm, "Failed to get HDMI state machine clock\n"); 3076 return PTR_ERR(vc4_hdmi->hsm_clock); 3077 } 3078 3079 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3080 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3081 drm_err(drm, "Failed to get pixel bvb clock\n"); 3082 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3083 } 3084 3085 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3086 if (IS_ERR(vc4_hdmi->audio_clock)) { 3087 drm_err(drm, "Failed to get audio clock\n"); 3088 return PTR_ERR(vc4_hdmi->audio_clock); 3089 } 3090 3091 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3092 if (IS_ERR(vc4_hdmi->cec_clock)) { 3093 drm_err(drm, "Failed to get CEC clock\n"); 3094 return PTR_ERR(vc4_hdmi->cec_clock); 3095 } 3096 3097 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3098 if (IS_ERR(vc4_hdmi->reset)) { 3099 drm_err(drm, "Failed to get HDMI reset line\n"); 3100 return PTR_ERR(vc4_hdmi->reset); 3101 } 3102 3103 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3104 if (ret) 3105 return ret; 3106 3107 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3108 if (ret) 3109 return ret; 3110 3111 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3112 if (ret) 3113 return ret; 3114 3115 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3116 if (ret) 3117 return ret; 3118 3119 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3120 if (ret) 3121 return ret; 3122 3123 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3124 if (ret) 3125 return ret; 3126 3127 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3128 if (ret) 3129 return ret; 3130 3131 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3132 if (ret) 3133 return ret; 3134 3135 return 0; 3136 } 3137 3138 static int vc4_hdmi_runtime_suspend(struct device *dev) 3139 { 3140 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3141 3142 clk_disable_unprepare(vc4_hdmi->audio_clock); 3143 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3144 3145 return 0; 3146 } 3147 3148 static int vc4_hdmi_runtime_resume(struct device *dev) 3149 { 3150 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3151 unsigned long __maybe_unused flags; 3152 u32 __maybe_unused value; 3153 unsigned long rate; 3154 int ret; 3155 3156 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3157 if (ret) 3158 return ret; 3159 3160 /* 3161 * Whenever the RaspberryPi boots without an HDMI monitor 3162 * plugged in, the firmware won't have initialized the HSM clock 3163 * rate and it will be reported as 0. 3164 * 3165 * If we try to access a register of the controller in such a 3166 * case, it will lead to a silent CPU stall. Let's make sure we 3167 * prevent such a case. 3168 */ 3169 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3170 if (!rate) { 3171 ret = -EINVAL; 3172 goto err_disable_clk; 3173 } 3174 3175 ret = clk_prepare_enable(vc4_hdmi->audio_clock); 3176 if (ret) 3177 goto err_disable_clk; 3178 3179 if (vc4_hdmi->variant->reset) 3180 vc4_hdmi->variant->reset(vc4_hdmi); 3181 3182 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3183 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3184 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3185 /* Set the logical address to Unregistered */ 3186 value |= VC4_HDMI_CEC_ADDR_MASK; 3187 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3188 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3189 3190 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3191 3192 if (!vc4_hdmi->variant->external_irq_controller) { 3193 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3194 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3195 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3196 } 3197 #endif 3198 3199 return 0; 3200 3201 err_disable_clk: 3202 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3203 return ret; 3204 } 3205 3206 static void vc4_hdmi_put_ddc_device(void *ptr) 3207 { 3208 struct vc4_hdmi *vc4_hdmi = ptr; 3209 3210 put_device(&vc4_hdmi->ddc->dev); 3211 } 3212 3213 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3214 { 3215 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3216 struct platform_device *pdev = to_platform_device(dev); 3217 struct drm_device *drm = dev_get_drvdata(master); 3218 struct vc4_hdmi *vc4_hdmi; 3219 struct drm_encoder *encoder; 3220 struct device_node *ddc_node; 3221 int ret; 3222 3223 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3224 if (!vc4_hdmi) 3225 return -ENOMEM; 3226 3227 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3228 if (ret) 3229 return ret; 3230 3231 spin_lock_init(&vc4_hdmi->hw_lock); 3232 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3233 3234 dev_set_drvdata(dev, vc4_hdmi); 3235 encoder = &vc4_hdmi->encoder.base; 3236 vc4_hdmi->encoder.type = variant->encoder_type; 3237 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3238 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3239 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3240 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3241 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3242 vc4_hdmi->pdev = pdev; 3243 vc4_hdmi->variant = variant; 3244 3245 /* 3246 * Since we don't know the state of the controller and its 3247 * display (if any), let's assume it's always enabled. 3248 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3249 * sure it's disabled, and avoid any inconsistency. 3250 */ 3251 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3252 vc4_hdmi->scdc_enabled = true; 3253 3254 ret = variant->init_resources(drm, vc4_hdmi); 3255 if (ret) 3256 return ret; 3257 3258 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3259 if (!ddc_node) { 3260 drm_err(drm, "Failed to find ddc node in device tree\n"); 3261 return -ENODEV; 3262 } 3263 3264 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3265 of_node_put(ddc_node); 3266 if (!vc4_hdmi->ddc) { 3267 drm_err(drm, "Failed to get ddc i2c adapter by node\n"); 3268 return -EPROBE_DEFER; 3269 } 3270 3271 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3272 if (ret) 3273 return ret; 3274 3275 /* Only use the GPIO HPD pin if present in the DT, otherwise 3276 * we'll use the HDMI core's register. 3277 */ 3278 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3279 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3280 return PTR_ERR(vc4_hdmi->hpd_gpio); 3281 } 3282 3283 vc4_hdmi->disable_wifi_frequencies = 3284 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3285 3286 ret = devm_pm_runtime_enable(dev); 3287 if (ret) 3288 return ret; 3289 3290 /* 3291 * We need to have the device powered up at this point to call 3292 * our reset hook and for the CEC init. 3293 */ 3294 ret = pm_runtime_resume_and_get(dev); 3295 if (ret) 3296 return ret; 3297 3298 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3299 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") || 3300 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") || 3301 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) && 3302 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3303 clk_prepare_enable(vc4_hdmi->pixel_clock); 3304 clk_prepare_enable(vc4_hdmi->hsm_clock); 3305 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3306 } 3307 3308 ret = drmm_encoder_init(drm, encoder, 3309 &vc4_hdmi_encoder_funcs, 3310 DRM_MODE_ENCODER_TMDS, 3311 NULL); 3312 if (ret) 3313 goto err_put_runtime_pm; 3314 3315 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3316 3317 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3318 if (ret) 3319 goto err_put_runtime_pm; 3320 3321 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3322 if (ret) 3323 goto err_put_runtime_pm; 3324 3325 ret = vc4_hdmi_cec_register(vc4_hdmi); 3326 if (ret) 3327 goto err_put_runtime_pm; 3328 3329 ret = vc4_hdmi_audio_init(vc4_hdmi); 3330 if (ret) 3331 goto err_put_runtime_pm; 3332 3333 pm_runtime_put_sync(dev); 3334 3335 return 0; 3336 3337 err_put_runtime_pm: 3338 pm_runtime_put_sync(dev); 3339 3340 return ret; 3341 } 3342 3343 static const struct component_ops vc4_hdmi_ops = { 3344 .bind = vc4_hdmi_bind, 3345 }; 3346 3347 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3348 { 3349 return component_add(&pdev->dev, &vc4_hdmi_ops); 3350 } 3351 3352 static void vc4_hdmi_dev_remove(struct platform_device *pdev) 3353 { 3354 component_del(&pdev->dev, &vc4_hdmi_ops); 3355 } 3356 3357 static const struct vc4_hdmi_variant bcm2835_variant = { 3358 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3359 .debugfs_name = "hdmi_regs", 3360 .card_name = "vc4-hdmi", 3361 .max_pixel_clock = 162000000, 3362 .registers = vc4_hdmi_fields, 3363 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3364 3365 .init_resources = vc4_hdmi_init_resources, 3366 .csc_setup = vc4_hdmi_csc_setup, 3367 .reset = vc4_hdmi_reset, 3368 .set_timings = vc4_hdmi_set_timings, 3369 .phy_init = vc4_hdmi_phy_init, 3370 .phy_disable = vc4_hdmi_phy_disable, 3371 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3372 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3373 .channel_map = vc4_hdmi_channel_map, 3374 .supports_hdr = false, 3375 }; 3376 3377 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3378 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3379 .debugfs_name = "hdmi0_regs", 3380 .card_name = "vc4-hdmi-0", 3381 .max_pixel_clock = 600000000, 3382 .registers = vc5_hdmi_hdmi0_fields, 3383 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3384 .phy_lane_mapping = { 3385 PHY_LANE_0, 3386 PHY_LANE_1, 3387 PHY_LANE_2, 3388 PHY_LANE_CK, 3389 }, 3390 .unsupported_odd_h_timings = true, 3391 .external_irq_controller = true, 3392 3393 .init_resources = vc5_hdmi_init_resources, 3394 .csc_setup = vc5_hdmi_csc_setup, 3395 .reset = vc5_hdmi_reset, 3396 .set_timings = vc5_hdmi_set_timings, 3397 .phy_init = vc5_hdmi_phy_init, 3398 .phy_disable = vc5_hdmi_phy_disable, 3399 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3400 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3401 .channel_map = vc5_hdmi_channel_map, 3402 .supports_hdr = true, 3403 .hp_detect = vc5_hdmi_hp_detect, 3404 }; 3405 3406 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3407 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3408 .debugfs_name = "hdmi1_regs", 3409 .card_name = "vc4-hdmi-1", 3410 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3411 .registers = vc5_hdmi_hdmi1_fields, 3412 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3413 .phy_lane_mapping = { 3414 PHY_LANE_1, 3415 PHY_LANE_0, 3416 PHY_LANE_CK, 3417 PHY_LANE_2, 3418 }, 3419 .unsupported_odd_h_timings = true, 3420 .external_irq_controller = true, 3421 3422 .init_resources = vc5_hdmi_init_resources, 3423 .csc_setup = vc5_hdmi_csc_setup, 3424 .reset = vc5_hdmi_reset, 3425 .set_timings = vc5_hdmi_set_timings, 3426 .phy_init = vc5_hdmi_phy_init, 3427 .phy_disable = vc5_hdmi_phy_disable, 3428 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3429 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3430 .channel_map = vc5_hdmi_channel_map, 3431 .supports_hdr = true, 3432 .hp_detect = vc5_hdmi_hp_detect, 3433 }; 3434 3435 static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = { 3436 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3437 .debugfs_name = "hdmi0_regs", 3438 .card_name = "vc4-hdmi-0", 3439 .max_pixel_clock = 600000000, 3440 .registers = vc6_hdmi_hdmi0_fields, 3441 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi0_fields), 3442 .phy_lane_mapping = { 3443 PHY_LANE_0, 3444 PHY_LANE_1, 3445 PHY_LANE_2, 3446 PHY_LANE_CK, 3447 }, 3448 .unsupported_odd_h_timings = false, 3449 .external_irq_controller = true, 3450 3451 .init_resources = vc5_hdmi_init_resources, 3452 .csc_setup = vc5_hdmi_csc_setup, 3453 .reset = vc5_hdmi_reset, 3454 .set_timings = vc5_hdmi_set_timings, 3455 .phy_init = vc6_hdmi_phy_init, 3456 .phy_disable = vc6_hdmi_phy_disable, 3457 .channel_map = vc5_hdmi_channel_map, 3458 .supports_hdr = true, 3459 .hp_detect = vc5_hdmi_hp_detect, 3460 }; 3461 3462 static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = { 3463 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3464 .debugfs_name = "hdmi1_regs", 3465 .card_name = "vc4-hdmi-1", 3466 .max_pixel_clock = 600000000, 3467 .registers = vc6_hdmi_hdmi1_fields, 3468 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi1_fields), 3469 .phy_lane_mapping = { 3470 PHY_LANE_0, 3471 PHY_LANE_1, 3472 PHY_LANE_2, 3473 PHY_LANE_CK, 3474 }, 3475 .unsupported_odd_h_timings = false, 3476 .external_irq_controller = true, 3477 3478 .init_resources = vc5_hdmi_init_resources, 3479 .csc_setup = vc5_hdmi_csc_setup, 3480 .reset = vc5_hdmi_reset, 3481 .set_timings = vc5_hdmi_set_timings, 3482 .phy_init = vc6_hdmi_phy_init, 3483 .phy_disable = vc6_hdmi_phy_disable, 3484 .channel_map = vc5_hdmi_channel_map, 3485 .supports_hdr = true, 3486 .hp_detect = vc5_hdmi_hp_detect, 3487 }; 3488 3489 static const struct of_device_id vc4_hdmi_dt_match[] = { 3490 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3491 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3492 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3493 { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant }, 3494 { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant }, 3495 {} 3496 }; 3497 3498 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3499 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3500 vc4_hdmi_runtime_resume, 3501 NULL) 3502 }; 3503 3504 struct platform_driver vc4_hdmi_driver = { 3505 .probe = vc4_hdmi_dev_probe, 3506 .remove = vc4_hdmi_dev_remove, 3507 .driver = { 3508 .name = "vc4_hdmi", 3509 .of_match_table = vc4_hdmi_dt_match, 3510 .pm = &vc4_hdmi_pm_ops, 3511 }, 3512 }; 3513