1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/display/drm_hdmi_state_helper.h> 36 #include <drm/display/drm_scdc_helper.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_drv.h> 39 #include <drm/drm_edid.h> 40 #include <drm/drm_probe_helper.h> 41 #include <drm/drm_simple_kms_helper.h> 42 #include <linux/clk.h> 43 #include <linux/component.h> 44 #include <linux/gpio/consumer.h> 45 #include <linux/i2c.h> 46 #include <linux/of.h> 47 #include <linux/of_address.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/rational.h> 50 #include <linux/reset.h> 51 #include <sound/dmaengine_pcm.h> 52 #include <sound/hdmi-codec.h> 53 #include <sound/pcm_drm_eld.h> 54 #include <sound/pcm_params.h> 55 #include <sound/soc.h> 56 #include "media/cec.h" 57 #include "vc4_drv.h" 58 #include "vc4_hdmi.h" 59 #include "vc4_hdmi_regs.h" 60 #include "vc4_regs.h" 61 62 #define VC5_HDMI_HORZA_HFP_SHIFT 16 63 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 64 #define VC5_HDMI_HORZA_VPOS BIT(15) 65 #define VC5_HDMI_HORZA_HPOS BIT(14) 66 #define VC5_HDMI_HORZA_HAP_SHIFT 0 67 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 68 69 #define VC5_HDMI_HORZB_HBP_SHIFT 16 70 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 71 #define VC5_HDMI_HORZB_HSP_SHIFT 0 72 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 73 74 #define VC5_HDMI_VERTA_VSP_SHIFT 24 75 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 76 #define VC5_HDMI_VERTA_VFP_SHIFT 16 77 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 78 #define VC5_HDMI_VERTA_VAL_SHIFT 0 79 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 80 81 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 82 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 83 84 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 85 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 86 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 87 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 88 89 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 90 91 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 93 94 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 96 97 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 98 99 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 101 102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0) 103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0) 104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4) 105 106 # define VC4_HD_M_SW_RST BIT(2) 107 # define VC4_HD_M_ENABLE BIT(0) 108 109 #define HSM_MIN_CLOCK_FREQ 120000000 110 #define CEC_CLOCK_FREQ 40000 111 112 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 113 114 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 115 { 116 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 117 118 lockdep_assert_held(&vc4_hdmi->mutex); 119 120 if (!display->is_hdmi) 121 return false; 122 123 if (!display->hdmi.scdc.supported || 124 !display->hdmi.scdc.scrambling.supported) 125 return false; 126 127 return true; 128 } 129 130 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 131 unsigned int bpc, 132 enum hdmi_colorspace fmt) 133 { 134 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt); 135 136 return clock > HDMI_14_MAX_TMDS_CLK; 137 } 138 139 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 140 { 141 struct drm_debugfs_entry *entry = m->private; 142 struct vc4_hdmi *vc4_hdmi = entry->file.data; 143 struct drm_device *drm = vc4_hdmi->connector.dev; 144 struct drm_printer p = drm_seq_file_printer(m); 145 int idx; 146 147 if (!drm_dev_enter(drm, &idx)) 148 return -ENODEV; 149 150 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 151 152 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 153 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 154 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 155 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 156 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 157 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 158 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 159 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 160 161 pm_runtime_put(&vc4_hdmi->pdev->dev); 162 163 drm_dev_exit(idx); 164 165 return 0; 166 } 167 168 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 169 { 170 struct drm_device *drm = vc4_hdmi->connector.dev; 171 unsigned long flags; 172 int idx; 173 174 /* 175 * We can be called by our bind callback, when the 176 * connector->dev pointer might not be initialised yet. 177 */ 178 if (drm && !drm_dev_enter(drm, &idx)) 179 return; 180 181 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 182 183 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 184 udelay(1); 185 HDMI_WRITE(HDMI_M_CTL, 0); 186 187 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 188 189 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 190 VC4_HDMI_SW_RESET_HDMI | 191 VC4_HDMI_SW_RESET_FORMAT_DETECT); 192 193 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 194 195 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 196 197 if (drm) 198 drm_dev_exit(idx); 199 } 200 201 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 202 { 203 struct drm_device *drm = vc4_hdmi->connector.dev; 204 unsigned long flags; 205 int idx; 206 207 /* 208 * We can be called by our bind callback, when the 209 * connector->dev pointer might not be initialised yet. 210 */ 211 if (drm && !drm_dev_enter(drm, &idx)) 212 return; 213 214 reset_control_reset(vc4_hdmi->reset); 215 216 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 217 218 HDMI_WRITE(HDMI_DVP_CTL, 0); 219 220 HDMI_WRITE(HDMI_CLOCK_STOP, 221 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 222 223 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 224 225 if (drm) 226 drm_dev_exit(idx); 227 } 228 229 #ifdef CONFIG_DRM_VC4_HDMI_CEC 230 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 231 { 232 struct drm_device *drm = vc4_hdmi->connector.dev; 233 unsigned long cec_rate; 234 unsigned long flags; 235 u16 clk_cnt; 236 u32 value; 237 int idx; 238 239 /* 240 * This function is called by our runtime_resume implementation 241 * and thus at bind time, when we haven't registered our 242 * connector yet and thus don't have a pointer to the DRM 243 * device. 244 */ 245 if (drm && !drm_dev_enter(drm, &idx)) 246 return; 247 248 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 249 250 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 251 252 value = HDMI_READ(HDMI_CEC_CNTRL_1); 253 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 254 255 /* 256 * Set the clock divider: the hsm_clock rate and this divider 257 * setting will give a 40 kHz CEC clock. 258 */ 259 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 260 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 261 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 262 263 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 264 265 if (drm) 266 drm_dev_exit(idx); 267 } 268 #else 269 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 270 #endif 271 272 static int reset_pipe(struct drm_crtc *crtc, 273 struct drm_modeset_acquire_ctx *ctx) 274 { 275 struct drm_atomic_state *state; 276 struct drm_crtc_state *crtc_state; 277 int ret; 278 279 state = drm_atomic_state_alloc(crtc->dev); 280 if (!state) 281 return -ENOMEM; 282 283 state->acquire_ctx = ctx; 284 285 crtc_state = drm_atomic_get_crtc_state(state, crtc); 286 if (IS_ERR(crtc_state)) { 287 ret = PTR_ERR(crtc_state); 288 goto out; 289 } 290 291 crtc_state->connectors_changed = true; 292 293 ret = drm_atomic_commit(state); 294 out: 295 drm_atomic_state_put(state); 296 297 return ret; 298 } 299 300 static int vc4_hdmi_reset_link(struct drm_connector *connector, 301 struct drm_modeset_acquire_ctx *ctx) 302 { 303 struct drm_device *drm; 304 struct vc4_hdmi *vc4_hdmi; 305 struct drm_connector_state *conn_state; 306 struct drm_crtc_state *crtc_state; 307 struct drm_crtc *crtc; 308 bool scrambling_needed; 309 u8 config; 310 int ret; 311 312 if (!connector) 313 return 0; 314 315 drm = connector->dev; 316 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 317 if (ret) 318 return ret; 319 320 conn_state = connector->state; 321 crtc = conn_state->crtc; 322 if (!crtc) 323 return 0; 324 325 ret = drm_modeset_lock(&crtc->mutex, ctx); 326 if (ret) 327 return ret; 328 329 crtc_state = crtc->state; 330 if (!crtc_state->active) 331 return 0; 332 333 vc4_hdmi = connector_to_vc4_hdmi(connector); 334 mutex_lock(&vc4_hdmi->mutex); 335 336 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 337 mutex_unlock(&vc4_hdmi->mutex); 338 return 0; 339 } 340 341 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 342 vc4_hdmi->output_bpc, 343 vc4_hdmi->output_format); 344 if (!scrambling_needed) { 345 mutex_unlock(&vc4_hdmi->mutex); 346 return 0; 347 } 348 349 if (conn_state->commit && 350 !try_wait_for_completion(&conn_state->commit->hw_done)) { 351 mutex_unlock(&vc4_hdmi->mutex); 352 return 0; 353 } 354 355 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 356 if (ret < 0) { 357 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 358 mutex_unlock(&vc4_hdmi->mutex); 359 return 0; 360 } 361 362 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 363 mutex_unlock(&vc4_hdmi->mutex); 364 return 0; 365 } 366 367 mutex_unlock(&vc4_hdmi->mutex); 368 369 /* 370 * HDMI 2.0 says that one should not send scrambled data 371 * prior to configuring the sink scrambling, and that 372 * TMDS clock/data transmission should be suspended when 373 * changing the TMDS clock rate in the sink. So let's 374 * just do a full modeset here, even though some sinks 375 * would be perfectly happy if were to just reconfigure 376 * the SCDC settings on the fly. 377 */ 378 return reset_pipe(crtc, ctx); 379 } 380 381 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 382 struct drm_modeset_acquire_ctx *ctx, 383 enum drm_connector_status status) 384 { 385 struct drm_connector *connector = &vc4_hdmi->connector; 386 const struct drm_edid *drm_edid; 387 int ret; 388 389 /* 390 * NOTE: This function should really be called with vc4_hdmi->mutex 391 * held, but doing so results in reentrancy issues since 392 * cec_s_phys_addr() might call .adap_enable, which leads to that 393 * funtion being called with our mutex held. 394 * 395 * A similar situation occurs with vc4_hdmi_reset_link() that 396 * will call into our KMS hooks if the scrambling was enabled. 397 * 398 * Concurrency isn't an issue at the moment since we don't share 399 * any state with any of the other frameworks so we can ignore 400 * the lock for now. 401 */ 402 403 if (status == connector_status_disconnected) { 404 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 405 return; 406 } 407 408 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc); 409 410 drm_edid_connector_update(connector, drm_edid); 411 cec_s_phys_addr(vc4_hdmi->cec_adap, 412 connector->display_info.source_physical_address, false); 413 414 if (!drm_edid) 415 return; 416 417 drm_edid_free(drm_edid); 418 419 for (;;) { 420 ret = vc4_hdmi_reset_link(connector, ctx); 421 if (ret == -EDEADLK) { 422 drm_modeset_backoff(ctx); 423 continue; 424 } 425 426 break; 427 } 428 } 429 430 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 431 struct drm_modeset_acquire_ctx *ctx, 432 bool force) 433 { 434 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 435 enum drm_connector_status status = connector_status_disconnected; 436 int ret; 437 438 /* 439 * NOTE: This function should really take vc4_hdmi->mutex, but 440 * doing so results in reentrancy issues since 441 * vc4_hdmi_handle_hotplug() can call into other functions that 442 * would take the mutex while it's held here. 443 * 444 * Concurrency isn't an issue at the moment since we don't share 445 * any state with any of the other frameworks so we can ignore 446 * the lock for now. 447 */ 448 449 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 450 if (ret) { 451 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n", 452 ret); 453 return connector_status_unknown; 454 } 455 456 if (vc4_hdmi->hpd_gpio) { 457 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 458 status = connector_status_connected; 459 } else { 460 if (vc4_hdmi->variant->hp_detect && 461 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 462 status = connector_status_connected; 463 } 464 465 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 466 pm_runtime_put(&vc4_hdmi->pdev->dev); 467 468 return status; 469 } 470 471 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 472 { 473 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 474 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 475 const struct drm_edid *drm_edid; 476 int ret = 0; 477 478 /* 479 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 480 * results in reentrancy issues since cec_s_phys_addr() might call 481 * .adap_enable, which leads to that funtion being called with our mutex 482 * held. 483 * 484 * Concurrency isn't an issue at the moment since we don't share 485 * any state with any of the other frameworks so we can ignore 486 * the lock for now. 487 */ 488 489 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc); 490 drm_edid_connector_update(connector, drm_edid); 491 cec_s_phys_addr(vc4_hdmi->cec_adap, 492 connector->display_info.source_physical_address, false); 493 if (!drm_edid) 494 return 0; 495 496 ret = drm_edid_connector_add_modes(connector); 497 drm_edid_free(drm_edid); 498 499 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 500 struct drm_device *drm = connector->dev; 501 const struct drm_display_mode *mode; 502 503 list_for_each_entry(mode, &connector->probed_modes, head) { 504 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) { 505 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 506 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 507 } 508 } 509 } 510 511 return ret; 512 } 513 514 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 515 struct drm_atomic_state *state) 516 { 517 struct drm_connector_state *old_state = 518 drm_atomic_get_old_connector_state(state, connector); 519 struct drm_connector_state *new_state = 520 drm_atomic_get_new_connector_state(state, connector); 521 struct drm_crtc *crtc = new_state->crtc; 522 523 if (!crtc) 524 return 0; 525 526 if (old_state->tv.margins.left != new_state->tv.margins.left || 527 old_state->tv.margins.right != new_state->tv.margins.right || 528 old_state->tv.margins.top != new_state->tv.margins.top || 529 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 530 struct drm_crtc_state *crtc_state; 531 int ret; 532 533 crtc_state = drm_atomic_get_crtc_state(state, crtc); 534 if (IS_ERR(crtc_state)) 535 return PTR_ERR(crtc_state); 536 537 /* 538 * Strictly speaking, we should be calling 539 * drm_atomic_helper_check_planes() after our call to 540 * drm_atomic_add_affected_planes(). However, the 541 * connector atomic_check is called as part of 542 * drm_atomic_helper_check_modeset() that already 543 * happens before a call to 544 * drm_atomic_helper_check_planes() in 545 * drm_atomic_helper_check(). 546 */ 547 ret = drm_atomic_add_affected_planes(state, crtc); 548 if (ret) 549 return ret; 550 } 551 552 if (old_state->colorspace != new_state->colorspace) { 553 struct drm_crtc_state *crtc_state; 554 555 crtc_state = drm_atomic_get_crtc_state(state, crtc); 556 if (IS_ERR(crtc_state)) 557 return PTR_ERR(crtc_state); 558 559 crtc_state->mode_changed = true; 560 } 561 562 return drm_atomic_helper_connector_hdmi_check(connector, state); 563 } 564 565 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 566 { 567 drm_atomic_helper_connector_reset(connector); 568 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); 569 drm_atomic_helper_connector_tv_margins_reset(connector); 570 } 571 572 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 573 .fill_modes = drm_helper_probe_single_connector_modes, 574 .reset = vc4_hdmi_connector_reset, 575 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 576 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 577 }; 578 579 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 580 .detect_ctx = vc4_hdmi_connector_detect_ctx, 581 .get_modes = vc4_hdmi_connector_get_modes, 582 .atomic_check = vc4_hdmi_connector_atomic_check, 583 .mode_valid = drm_hdmi_connector_mode_valid, 584 }; 585 586 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs; 587 588 static int vc4_hdmi_connector_init(struct drm_device *dev, 589 struct vc4_hdmi *vc4_hdmi) 590 { 591 struct drm_connector *connector = &vc4_hdmi->connector; 592 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 593 unsigned int max_bpc = 8; 594 int ret; 595 596 if (vc4_hdmi->variant->supports_hdr) 597 max_bpc = 12; 598 599 ret = drmm_connector_hdmi_init(dev, connector, 600 "Broadcom", "Videocore", 601 &vc4_hdmi_connector_funcs, 602 &vc4_hdmi_hdmi_connector_funcs, 603 DRM_MODE_CONNECTOR_HDMIA, 604 vc4_hdmi->ddc, 605 BIT(HDMI_COLORSPACE_RGB) | 606 BIT(HDMI_COLORSPACE_YUV422) | 607 BIT(HDMI_COLORSPACE_YUV444), 608 max_bpc); 609 if (ret) 610 return ret; 611 612 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 613 614 /* 615 * Some of the properties below require access to state, like bpc. 616 * Allocate some default initial connector state with our reset helper. 617 */ 618 if (connector->funcs->reset) 619 connector->funcs->reset(connector); 620 621 /* Create and attach TV margin props to this connector. */ 622 ret = drm_mode_create_tv_margin_properties(dev); 623 if (ret) 624 return ret; 625 626 ret = drm_mode_create_hdmi_colorspace_property(connector, 0); 627 if (ret) 628 return ret; 629 630 drm_connector_attach_colorspace_property(connector); 631 drm_connector_attach_tv_margin_properties(connector); 632 633 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 634 DRM_CONNECTOR_POLL_DISCONNECT); 635 636 connector->interlace_allowed = 1; 637 connector->doublescan_allowed = 0; 638 connector->stereo_allowed = 1; 639 640 ret = drm_connector_attach_broadcast_rgb_property(connector); 641 if (ret) 642 return ret; 643 644 drm_connector_attach_encoder(connector, encoder); 645 646 return 0; 647 } 648 649 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi, 650 enum hdmi_infoframe_type type, 651 bool poll) 652 { 653 struct drm_device *drm = vc4_hdmi->connector.dev; 654 u32 packet_id = type - 0x80; 655 unsigned long flags; 656 int ret = 0; 657 int idx; 658 659 if (!drm_dev_enter(drm, &idx)) 660 return -ENODEV; 661 662 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 663 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 664 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 665 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 666 667 if (poll) { 668 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 669 BIT(packet_id)), 100); 670 } 671 672 drm_dev_exit(idx); 673 return ret; 674 } 675 676 static int vc4_hdmi_write_infoframe(struct drm_connector *connector, 677 enum hdmi_infoframe_type type, 678 const u8 *infoframe, size_t len) 679 { 680 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 681 struct drm_device *drm = connector->dev; 682 u32 packet_id = type - 0x80; 683 const struct vc4_hdmi_register *ram_packet_start = 684 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 685 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 686 u32 packet_reg_next = ram_packet_start->offset + 687 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 688 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 689 ram_packet_start->reg); 690 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 691 unsigned long flags; 692 ssize_t i; 693 int ret; 694 int idx; 695 696 if (!drm_dev_enter(drm, &idx)) 697 return 0; 698 699 if (len > sizeof(buffer)) { 700 ret = -ENOMEM; 701 goto out; 702 } 703 704 memcpy(buffer, infoframe, len); 705 706 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 707 VC4_HDMI_RAM_PACKET_ENABLE), 708 "Packet RAM has to be on to store the packet."); 709 710 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true); 711 if (ret) { 712 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret); 713 goto out; 714 } 715 716 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 717 718 for (i = 0; i < len; i += 7) { 719 writel(buffer[i + 0] << 0 | 720 buffer[i + 1] << 8 | 721 buffer[i + 2] << 16, 722 base + packet_reg); 723 packet_reg += 4; 724 725 writel(buffer[i + 3] << 0 | 726 buffer[i + 4] << 8 | 727 buffer[i + 5] << 16 | 728 buffer[i + 6] << 24, 729 base + packet_reg); 730 packet_reg += 4; 731 } 732 733 /* 734 * clear remainder of packet ram as it's included in the 735 * infoframe and triggers a checksum error on hdmi analyser 736 */ 737 for (; packet_reg < packet_reg_next; packet_reg += 4) 738 writel(0, base + packet_reg); 739 740 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 741 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 742 743 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 744 745 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 746 BIT(packet_id)), 100); 747 if (ret) 748 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret); 749 750 out: 751 drm_dev_exit(idx); 752 return ret; 753 } 754 755 #define SCRAMBLING_POLLING_DELAY_MS 1000 756 757 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 758 { 759 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 760 struct drm_connector *connector = &vc4_hdmi->connector; 761 struct drm_device *drm = connector->dev; 762 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 763 unsigned long flags; 764 int idx; 765 766 lockdep_assert_held(&vc4_hdmi->mutex); 767 768 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 769 return; 770 771 if (!vc4_hdmi_mode_needs_scrambling(mode, 772 vc4_hdmi->output_bpc, 773 vc4_hdmi->output_format)) 774 return; 775 776 if (!drm_dev_enter(drm, &idx)) 777 return; 778 779 drm_scdc_set_high_tmds_clock_ratio(connector, true); 780 drm_scdc_set_scrambling(connector, true); 781 782 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 783 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 784 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 785 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 786 787 drm_dev_exit(idx); 788 789 vc4_hdmi->scdc_enabled = true; 790 791 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 792 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 793 } 794 795 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 796 { 797 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 798 struct drm_connector *connector = &vc4_hdmi->connector; 799 struct drm_device *drm = connector->dev; 800 unsigned long flags; 801 int idx; 802 803 lockdep_assert_held(&vc4_hdmi->mutex); 804 805 if (!vc4_hdmi->scdc_enabled) 806 return; 807 808 vc4_hdmi->scdc_enabled = false; 809 810 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 811 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 812 813 if (!drm_dev_enter(drm, &idx)) 814 return; 815 816 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 817 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 818 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 819 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 820 821 drm_scdc_set_scrambling(connector, false); 822 drm_scdc_set_high_tmds_clock_ratio(connector, false); 823 824 drm_dev_exit(idx); 825 } 826 827 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 828 { 829 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 830 struct vc4_hdmi, 831 scrambling_work); 832 struct drm_connector *connector = &vc4_hdmi->connector; 833 834 if (drm_scdc_get_scrambling_status(connector)) 835 return; 836 837 drm_scdc_set_high_tmds_clock_ratio(connector, true); 838 drm_scdc_set_scrambling(connector, true); 839 840 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 841 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 842 } 843 844 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 845 struct drm_atomic_state *state) 846 { 847 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 848 struct drm_device *drm = vc4_hdmi->connector.dev; 849 struct vc4_dev *vc4 = to_vc4_dev(drm); 850 unsigned long flags; 851 int idx; 852 853 mutex_lock(&vc4_hdmi->mutex); 854 855 vc4_hdmi->packet_ram_enabled = false; 856 857 if (!drm_dev_enter(drm, &idx)) 858 goto out; 859 860 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 861 862 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 863 864 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 865 866 if (vc4->gen >= VC4_GEN_6_C) 867 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 868 VC4_HD_VID_CTL_BLANKPIX); 869 870 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 871 872 mdelay(1); 873 874 /* 875 * TODO: This should work on BCM2712, but doesn't for some 876 * reason and result in a system lockup. 877 */ 878 if (vc4->gen < VC4_GEN_6_C) { 879 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 880 HDMI_WRITE(HDMI_VID_CTL, 881 HDMI_READ(HDMI_VID_CTL) & 882 ~VC4_HD_VID_CTL_ENABLE); 883 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 884 } 885 886 vc4_hdmi_disable_scrambling(encoder); 887 888 drm_dev_exit(idx); 889 890 out: 891 mutex_unlock(&vc4_hdmi->mutex); 892 } 893 894 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 895 struct drm_atomic_state *state) 896 { 897 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 898 struct drm_device *drm = vc4_hdmi->connector.dev; 899 unsigned long flags; 900 int ret; 901 int idx; 902 903 mutex_lock(&vc4_hdmi->mutex); 904 905 if (!drm_dev_enter(drm, &idx)) 906 goto out; 907 908 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 909 HDMI_WRITE(HDMI_VID_CTL, 910 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 911 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 912 913 if (vc4_hdmi->variant->phy_disable) 914 vc4_hdmi->variant->phy_disable(vc4_hdmi); 915 916 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 917 clk_disable_unprepare(vc4_hdmi->pixel_clock); 918 919 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 920 if (ret < 0) 921 drm_err(drm, "Failed to release power domain: %d\n", ret); 922 923 drm_dev_exit(idx); 924 925 out: 926 mutex_unlock(&vc4_hdmi->mutex); 927 } 928 929 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 930 struct drm_connector_state *state, 931 const struct drm_display_mode *mode) 932 { 933 struct drm_device *drm = vc4_hdmi->connector.dev; 934 unsigned long flags; 935 u32 csc_ctl; 936 int idx; 937 938 if (!drm_dev_enter(drm, &idx)) 939 return; 940 941 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 942 943 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 944 VC4_HD_CSC_CTL_ORDER); 945 946 if (state->hdmi.is_limited_range) { 947 /* CEA VICs other than #1 requre limited range RGB 948 * output unless overridden by an AVI infoframe. 949 * Apply a colorspace conversion to squash 0-255 down 950 * to 16-235. The matrix here is: 951 * 952 * [ 0 0 0.8594 16] 953 * [ 0 0.8594 0 16] 954 * [ 0.8594 0 0 16] 955 * [ 0 0 0 1] 956 */ 957 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 958 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 959 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 960 VC4_HD_CSC_CTL_MODE); 961 962 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 963 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 964 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 965 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 966 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 967 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 968 } 969 970 /* The RGB order applies even when CSC is disabled. */ 971 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 972 973 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 974 975 drm_dev_exit(idx); 976 } 977 978 /* 979 * Matrices for (internal) RGB to RGB output. 980 * 981 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 982 */ 983 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = { 984 { 985 /* 986 * Full range - unity 987 * 988 * [ 1 0 0 0] 989 * [ 0 1 0 0] 990 * [ 0 0 1 0] 991 */ 992 { 0x2000, 0x0000, 0x0000, 0x0000 }, 993 { 0x0000, 0x2000, 0x0000, 0x0000 }, 994 { 0x0000, 0x0000, 0x2000, 0x0000 }, 995 }, 996 { 997 /* 998 * Limited range 999 * 1000 * CEA VICs other than #1 require limited range RGB 1001 * output unless overridden by an AVI infoframe. Apply a 1002 * colorspace conversion to squash 0-255 down to 16-235. 1003 * The matrix here is: 1004 * 1005 * [ 0.8594 0 0 16] 1006 * [ 0 0.8594 0 16] 1007 * [ 0 0 0.8594 16] 1008 */ 1009 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 1010 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 1011 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 1012 }, 1013 }; 1014 1015 /* 1016 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace 1017 * 1018 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1019 */ 1020 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = { 1021 { 1022 /* 1023 * Full Range 1024 * 1025 * [ 0.299000 0.587000 0.114000 0 ] 1026 * [ -0.168736 -0.331264 0.500000 128 ] 1027 * [ 0.500000 -0.418688 -0.081312 128 ] 1028 */ 1029 { 0x0991, 0x12c9, 0x03a6, 0x0000 }, 1030 { 0xfa9b, 0xf567, 0x1000, 0x2000 }, 1031 { 0x1000, 0xf29b, 0xfd67, 0x2000 }, 1032 }, 1033 { 1034 /* Limited Range 1035 * 1036 * [ 0.255785 0.502160 0.097523 16 ] 1037 * [ -0.147644 -0.289856 0.437500 128 ] 1038 * [ 0.437500 -0.366352 -0.071148 128 ] 1039 */ 1040 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1041 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1042 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1043 }, 1044 }; 1045 1046 /* 1047 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace 1048 * 1049 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1050 */ 1051 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = { 1052 { 1053 /* 1054 * Full Range 1055 * 1056 * [ 0.212600 0.715200 0.072200 0 ] 1057 * [ -0.114572 -0.385428 0.500000 128 ] 1058 * [ 0.500000 -0.454153 -0.045847 128 ] 1059 */ 1060 { 0x06ce, 0x16e3, 0x024f, 0x0000 }, 1061 { 0xfc56, 0xf3ac, 0x1000, 0x2000 }, 1062 { 0x1000, 0xf179, 0xfe89, 0x2000 }, 1063 }, 1064 { 1065 /* 1066 * Limited Range 1067 * 1068 * [ 0.181906 0.611804 0.061758 16 ] 1069 * [ -0.100268 -0.337232 0.437500 128 ] 1070 * [ 0.437500 -0.397386 -0.040114 128 ] 1071 */ 1072 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1073 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1074 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1075 }, 1076 }; 1077 1078 /* 1079 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace 1080 * 1081 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1082 */ 1083 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = { 1084 { 1085 /* 1086 * Full Range 1087 * 1088 * [ 0.262700 0.678000 0.059300 0 ] 1089 * [ -0.139630 -0.360370 0.500000 128 ] 1090 * [ 0.500000 -0.459786 -0.040214 128 ] 1091 */ 1092 { 0x0868, 0x15b2, 0x01e6, 0x0000 }, 1093 { 0xfb89, 0xf479, 0x1000, 0x2000 }, 1094 { 0x1000, 0xf14a, 0xfeb8, 0x2000 }, 1095 }, 1096 { 1097 /* Limited Range 1098 * 1099 * [ 0.224732 0.580008 0.050729 16 ] 1100 * [ -0.122176 -0.315324 0.437500 128 ] 1101 * [ 0.437500 -0.402312 -0.035188 128 ] 1102 */ 1103 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1104 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1105 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1106 }, 1107 }; 1108 1109 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1110 const u16 coeffs[3][4]) 1111 { 1112 lockdep_assert_held(&vc4_hdmi->hw_lock); 1113 1114 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1115 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1116 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1117 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1118 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1119 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1120 } 1121 1122 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi, 1123 const u16 coeffs[3][4]) 1124 { 1125 lockdep_assert_held(&vc4_hdmi->hw_lock); 1126 1127 /* YUV444 needs the CSC matrices using the channels in a different order */ 1128 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]); 1129 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]); 1130 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]); 1131 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]); 1132 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]); 1133 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]); 1134 } 1135 1136 static const u16 1137 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4] 1138 { 1139 switch (colorspace) { 1140 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC: 1141 case DRM_MODE_COLORIMETRY_XVYCC_601: 1142 case DRM_MODE_COLORIMETRY_SYCC_601: 1143 case DRM_MODE_COLORIMETRY_OPYCC_601: 1144 case DRM_MODE_COLORIMETRY_BT601_YCC: 1145 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited]; 1146 1147 default: 1148 case DRM_MODE_COLORIMETRY_NO_DATA: 1149 case DRM_MODE_COLORIMETRY_BT709_YCC: 1150 case DRM_MODE_COLORIMETRY_XVYCC_709: 1151 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED: 1152 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT: 1153 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited]; 1154 1155 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 1156 case DRM_MODE_COLORIMETRY_BT2020_YCC: 1157 case DRM_MODE_COLORIMETRY_BT2020_RGB: 1158 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 1159 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 1160 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited]; 1161 } 1162 } 1163 1164 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1165 struct drm_connector_state *state, 1166 const struct drm_display_mode *mode) 1167 { 1168 struct drm_device *drm = vc4_hdmi->connector.dev; 1169 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0; 1170 unsigned long flags; 1171 const u16 (*csc)[4]; 1172 u32 if_cfg = 0; 1173 u32 if_xbar = 0x543210; 1174 u32 csc_chan_ctl = 0; 1175 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1176 VC5_MT_CP_CSC_CTL_MODE); 1177 int idx; 1178 1179 if (!drm_dev_enter(drm, &idx)) 1180 return; 1181 1182 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1183 1184 switch (state->hdmi.output_format) { 1185 case HDMI_COLORSPACE_YUV444: 1186 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1187 1188 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc); 1189 break; 1190 1191 case HDMI_COLORSPACE_YUV422: 1192 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1193 1194 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1195 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1196 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1197 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1198 1199 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1200 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1201 1202 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1203 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1204 1205 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc); 1206 break; 1207 1208 case HDMI_COLORSPACE_RGB: 1209 if_xbar = 0x354021; 1210 1211 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]); 1212 break; 1213 1214 default: 1215 break; 1216 } 1217 1218 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1219 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1220 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1221 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1222 1223 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1224 1225 drm_dev_exit(idx); 1226 } 1227 1228 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1229 struct drm_connector_state *state, 1230 const struct drm_display_mode *mode) 1231 { 1232 struct drm_device *drm = vc4_hdmi->connector.dev; 1233 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1234 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1235 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1236 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1237 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1238 VC4_HDMI_VERTA_VSP) | 1239 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1240 VC4_HDMI_VERTA_VFP) | 1241 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1242 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1243 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1244 interlaced, 1245 VC4_HDMI_VERTB_VBP)); 1246 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1247 VC4_SET_FIELD(mode->crtc_vtotal - 1248 mode->crtc_vsync_end, 1249 VC4_HDMI_VERTB_VBP)); 1250 unsigned long flags; 1251 u32 reg; 1252 int idx; 1253 1254 if (!drm_dev_enter(drm, &idx)) 1255 return; 1256 1257 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1258 1259 HDMI_WRITE(HDMI_HORZA, 1260 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1261 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1262 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1263 VC4_HDMI_HORZA_HAP)); 1264 1265 HDMI_WRITE(HDMI_HORZB, 1266 VC4_SET_FIELD((mode->htotal - 1267 mode->hsync_end) * pixel_rep, 1268 VC4_HDMI_HORZB_HBP) | 1269 VC4_SET_FIELD((mode->hsync_end - 1270 mode->hsync_start) * pixel_rep, 1271 VC4_HDMI_HORZB_HSP) | 1272 VC4_SET_FIELD((mode->hsync_start - 1273 mode->hdisplay) * pixel_rep, 1274 VC4_HDMI_HORZB_HFP)); 1275 1276 HDMI_WRITE(HDMI_VERTA0, verta); 1277 HDMI_WRITE(HDMI_VERTA1, verta); 1278 1279 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1280 HDMI_WRITE(HDMI_VERTB1, vertb); 1281 1282 reg = HDMI_READ(HDMI_MISC_CONTROL); 1283 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1284 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1285 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1286 1287 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1288 1289 drm_dev_exit(idx); 1290 } 1291 1292 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1293 struct drm_connector_state *state, 1294 const struct drm_display_mode *mode) 1295 { 1296 struct drm_device *drm = vc4_hdmi->connector.dev; 1297 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1298 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1299 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1300 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1301 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1302 VC5_HDMI_VERTA_VSP) | 1303 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1304 VC5_HDMI_VERTA_VFP) | 1305 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1306 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1307 VC5_HDMI_VERTB_VSPO) | 1308 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1309 interlaced, 1310 VC4_HDMI_VERTB_VBP)); 1311 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1312 VC4_SET_FIELD(mode->crtc_vtotal - 1313 mode->crtc_vsync_end, 1314 VC4_HDMI_VERTB_VBP)); 1315 unsigned long flags; 1316 unsigned char gcp; 1317 u32 reg; 1318 int idx; 1319 1320 if (!drm_dev_enter(drm, &idx)) 1321 return; 1322 1323 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1324 1325 HDMI_WRITE(HDMI_HORZA, 1326 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1327 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1328 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1329 VC5_HDMI_HORZA_HAP) | 1330 VC4_SET_FIELD((mode->hsync_start - 1331 mode->hdisplay) * pixel_rep, 1332 VC5_HDMI_HORZA_HFP)); 1333 1334 HDMI_WRITE(HDMI_HORZB, 1335 VC4_SET_FIELD((mode->htotal - 1336 mode->hsync_end) * pixel_rep, 1337 VC5_HDMI_HORZB_HBP) | 1338 VC4_SET_FIELD((mode->hsync_end - 1339 mode->hsync_start) * pixel_rep, 1340 VC5_HDMI_HORZB_HSP)); 1341 1342 HDMI_WRITE(HDMI_VERTA0, verta); 1343 HDMI_WRITE(HDMI_VERTA1, verta); 1344 1345 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1346 HDMI_WRITE(HDMI_VERTB1, vertb); 1347 1348 switch (state->hdmi.output_bpc) { 1349 case 12: 1350 gcp = 6; 1351 break; 1352 case 10: 1353 gcp = 5; 1354 break; 1355 case 8: 1356 default: 1357 gcp = 0; 1358 break; 1359 } 1360 1361 /* 1362 * YCC422 is always 36-bit and not considered deep colour so 1363 * doesn't signal in GCP. 1364 */ 1365 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) { 1366 gcp = 0; 1367 } 1368 1369 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1370 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1371 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1372 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1373 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1374 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1375 1376 reg = HDMI_READ(HDMI_GCP_WORD_1); 1377 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1378 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1379 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK; 1380 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE; 1381 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1382 1383 reg = HDMI_READ(HDMI_GCP_CONFIG); 1384 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1385 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1386 1387 reg = HDMI_READ(HDMI_MISC_CONTROL); 1388 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1389 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1390 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1391 1392 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1393 1394 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1395 1396 drm_dev_exit(idx); 1397 } 1398 1399 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1400 { 1401 struct drm_device *drm = vc4_hdmi->connector.dev; 1402 unsigned long flags; 1403 u32 drift; 1404 int ret; 1405 int idx; 1406 1407 if (!drm_dev_enter(drm, &idx)) 1408 return; 1409 1410 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1411 1412 drift = HDMI_READ(HDMI_FIFO_CTL); 1413 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1414 1415 HDMI_WRITE(HDMI_FIFO_CTL, 1416 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1417 HDMI_WRITE(HDMI_FIFO_CTL, 1418 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1419 1420 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1421 1422 usleep_range(1000, 1100); 1423 1424 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1425 1426 HDMI_WRITE(HDMI_FIFO_CTL, 1427 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1428 HDMI_WRITE(HDMI_FIFO_CTL, 1429 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1430 1431 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1432 1433 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1434 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1435 WARN_ONCE(ret, "Timeout waiting for " 1436 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1437 1438 drm_dev_exit(idx); 1439 } 1440 1441 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1442 struct drm_atomic_state *state) 1443 { 1444 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1445 struct drm_device *drm = vc4_hdmi->connector.dev; 1446 struct drm_connector *connector = &vc4_hdmi->connector; 1447 struct drm_connector_state *conn_state = 1448 drm_atomic_get_new_connector_state(state, connector); 1449 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1450 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate; 1451 unsigned long bvb_rate, hsm_rate; 1452 unsigned long flags; 1453 int ret; 1454 int idx; 1455 1456 mutex_lock(&vc4_hdmi->mutex); 1457 1458 if (!drm_dev_enter(drm, &idx)) 1459 goto out; 1460 1461 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1462 if (ret < 0) { 1463 drm_err(drm, "Failed to retain power domain: %d\n", ret); 1464 goto err_dev_exit; 1465 } 1466 1467 /* 1468 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1469 * be faster than pixel clock, infinitesimally faster, tested in 1470 * simulation. Otherwise, exact value is unimportant for HDMI 1471 * operation." This conflicts with bcm2835's vc4 documentation, which 1472 * states HSM's clock has to be at least 108% of the pixel clock. 1473 * 1474 * Real life tests reveal that vc4's firmware statement holds up, and 1475 * users are able to use pixel clocks closer to HSM's, namely for 1476 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1477 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1478 * 162MHz. 1479 * 1480 * Additionally, the AXI clock needs to be at least 25% of 1481 * pixel clock, but HSM ends up being the limiting factor. 1482 */ 1483 hsm_rate = max_t(unsigned long, 1484 HSM_MIN_CLOCK_FREQ, 1485 div_u64(tmds_char_rate, 100) * 101); 1486 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1487 if (ret) { 1488 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret); 1489 goto err_put_runtime_pm; 1490 } 1491 1492 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1493 if (ret) { 1494 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret); 1495 goto err_put_runtime_pm; 1496 } 1497 1498 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1499 if (ret) { 1500 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret); 1501 goto err_put_runtime_pm; 1502 } 1503 1504 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1505 1506 if (tmds_char_rate > 297000000) 1507 bvb_rate = 300000000; 1508 else if (tmds_char_rate > 148500000) 1509 bvb_rate = 150000000; 1510 else 1511 bvb_rate = 75000000; 1512 1513 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1514 if (ret) { 1515 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret); 1516 goto err_disable_pixel_clock; 1517 } 1518 1519 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1520 if (ret) { 1521 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret); 1522 goto err_disable_pixel_clock; 1523 } 1524 1525 if (vc4_hdmi->variant->phy_init) 1526 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state); 1527 1528 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1529 1530 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1531 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1532 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1533 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1534 1535 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1536 1537 if (vc4_hdmi->variant->set_timings) 1538 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1539 1540 drm_dev_exit(idx); 1541 1542 mutex_unlock(&vc4_hdmi->mutex); 1543 1544 return; 1545 1546 err_disable_pixel_clock: 1547 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1548 err_put_runtime_pm: 1549 pm_runtime_put(&vc4_hdmi->pdev->dev); 1550 err_dev_exit: 1551 drm_dev_exit(idx); 1552 out: 1553 mutex_unlock(&vc4_hdmi->mutex); 1554 return; 1555 } 1556 1557 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1558 struct drm_atomic_state *state) 1559 { 1560 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1561 struct drm_device *drm = vc4_hdmi->connector.dev; 1562 struct drm_connector *connector = &vc4_hdmi->connector; 1563 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1564 struct drm_connector_state *conn_state = 1565 drm_atomic_get_new_connector_state(state, connector); 1566 unsigned long flags; 1567 int idx; 1568 1569 mutex_lock(&vc4_hdmi->mutex); 1570 1571 if (!drm_dev_enter(drm, &idx)) 1572 goto out; 1573 1574 if (vc4_hdmi->variant->csc_setup) 1575 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1576 1577 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1578 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1579 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1580 1581 drm_dev_exit(idx); 1582 1583 out: 1584 mutex_unlock(&vc4_hdmi->mutex); 1585 } 1586 1587 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1588 struct drm_atomic_state *state) 1589 { 1590 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1591 struct drm_connector *connector = &vc4_hdmi->connector; 1592 struct drm_device *drm = connector->dev; 1593 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1594 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1595 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1596 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1597 unsigned long flags; 1598 int ret; 1599 int idx; 1600 1601 mutex_lock(&vc4_hdmi->mutex); 1602 1603 if (!drm_dev_enter(drm, &idx)) 1604 goto out; 1605 1606 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1607 1608 HDMI_WRITE(HDMI_VID_CTL, 1609 (HDMI_READ(HDMI_VID_CTL) & 1610 ~(VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) | 1611 VC4_HD_VID_CTL_ENABLE | 1612 VC4_HD_VID_CTL_CLRRGB | 1613 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1614 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1615 VC4_HD_VID_CTL_BLANK_INSERT_EN | 1616 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1617 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1618 1619 HDMI_WRITE(HDMI_VID_CTL, 1620 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1621 1622 if (display->is_hdmi) { 1623 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1624 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1625 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1626 1627 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1628 1629 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1630 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1631 WARN_ONCE(ret, "Timeout waiting for " 1632 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1633 } else { 1634 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1635 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1636 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1637 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1638 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1639 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1640 1641 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1642 1643 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1644 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1645 WARN_ONCE(ret, "Timeout waiting for " 1646 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1647 } 1648 1649 if (display->is_hdmi) { 1650 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1651 1652 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1653 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1654 1655 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1656 VC4_HDMI_RAM_PACKET_ENABLE); 1657 1658 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1659 vc4_hdmi->packet_ram_enabled = true; 1660 1661 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 1662 } 1663 1664 vc4_hdmi_recenter_fifo(vc4_hdmi); 1665 vc4_hdmi_enable_scrambling(encoder); 1666 1667 drm_dev_exit(idx); 1668 1669 out: 1670 mutex_unlock(&vc4_hdmi->mutex); 1671 } 1672 1673 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1674 struct drm_crtc_state *crtc_state, 1675 struct drm_connector_state *conn_state) 1676 { 1677 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1678 1679 mutex_lock(&vc4_hdmi->mutex); 1680 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1681 &crtc_state->adjusted_mode); 1682 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc; 1683 vc4_hdmi->output_format = conn_state->hdmi.output_format; 1684 mutex_unlock(&vc4_hdmi->mutex); 1685 } 1686 1687 static enum drm_mode_status 1688 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector, 1689 const struct drm_display_mode *mode, 1690 unsigned long long clock) 1691 { 1692 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1693 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 1694 1695 if (clock > vc4_hdmi->variant->max_pixel_clock) 1696 return MODE_CLOCK_HIGH; 1697 1698 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 1699 return MODE_CLOCK_HIGH; 1700 1701 /* 4096x2160@60 is not reliable without overclocking core */ 1702 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 1703 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 1704 drm_mode_vrefresh(mode) >= 50) 1705 return MODE_CLOCK_HIGH; 1706 1707 return MODE_OK; 1708 } 1709 1710 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = { 1711 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid, 1712 .write_infoframe = vc4_hdmi_write_infoframe, 1713 }; 1714 1715 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1716 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1717 1718 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1719 struct drm_crtc_state *crtc_state, 1720 struct drm_connector_state *conn_state) 1721 { 1722 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1723 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1724 unsigned long long tmds_char_rate = mode->clock * 1000; 1725 unsigned long long tmds_bit_rate; 1726 1727 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1728 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1729 /* Only try to fixup DBLCLK modes to get 480i and 576i 1730 * working. 1731 * A generic solution for all modes with odd horizontal 1732 * timing values seems impossible based on trying to 1733 * solve it for 1366x768 monitors. 1734 */ 1735 if ((mode->hsync_start - mode->hdisplay) & 1) 1736 mode->hsync_start--; 1737 if ((mode->hsync_end - mode->hsync_start) & 1) 1738 mode->hsync_end--; 1739 } 1740 1741 /* Now check whether we still have odd values remaining */ 1742 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1743 (mode->hsync_end % 2) || (mode->htotal % 2)) 1744 return -EINVAL; 1745 } 1746 1747 /* 1748 * The 1440p@60 pixel rate is in the same range than the first 1749 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1750 * bandwidth). Slightly lower the frequency to bring it out of 1751 * the WiFi range. 1752 */ 1753 tmds_bit_rate = tmds_char_rate * 10; 1754 if (vc4_hdmi->disable_wifi_frequencies && 1755 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1756 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1757 mode->clock = 238560; 1758 tmds_char_rate = mode->clock * 1000; 1759 } 1760 1761 return 0; 1762 } 1763 1764 static enum drm_mode_status 1765 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1766 const struct drm_display_mode *mode) 1767 { 1768 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1769 1770 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1771 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1772 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1773 (mode->hsync_end % 2) || (mode->htotal % 2))) 1774 return MODE_H_ILLEGAL; 1775 1776 return MODE_OK; 1777 } 1778 1779 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1780 .atomic_check = vc4_hdmi_encoder_atomic_check, 1781 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1782 .mode_valid = vc4_hdmi_encoder_mode_valid, 1783 }; 1784 1785 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 1786 { 1787 struct drm_device *drm = encoder->dev; 1788 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1789 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1790 1791 drm_debugfs_add_file(drm, variant->debugfs_name, 1792 vc4_hdmi_debugfs_regs, vc4_hdmi); 1793 1794 return 0; 1795 } 1796 1797 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 1798 .late_register = vc4_hdmi_late_register, 1799 }; 1800 1801 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1802 { 1803 int i; 1804 u32 channel_map = 0; 1805 1806 for (i = 0; i < 8; i++) { 1807 if (channel_mask & BIT(i)) 1808 channel_map |= i << (3 * i); 1809 } 1810 return channel_map; 1811 } 1812 1813 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1814 { 1815 int i; 1816 u32 channel_map = 0; 1817 1818 for (i = 0; i < 8; i++) { 1819 if (channel_mask & BIT(i)) 1820 channel_map |= i << (4 * i); 1821 } 1822 return channel_map; 1823 } 1824 1825 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1826 { 1827 struct drm_device *drm = vc4_hdmi->connector.dev; 1828 unsigned long flags; 1829 u32 hotplug; 1830 int idx; 1831 1832 if (!drm_dev_enter(drm, &idx)) 1833 return false; 1834 1835 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1836 hotplug = HDMI_READ(HDMI_HOTPLUG); 1837 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1838 1839 drm_dev_exit(idx); 1840 1841 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1842 } 1843 1844 /* HDMI audio codec callbacks */ 1845 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1846 unsigned int samplerate) 1847 { 1848 struct drm_device *drm = vc4_hdmi->connector.dev; 1849 u32 hsm_clock; 1850 unsigned long flags; 1851 unsigned long n, m; 1852 int idx; 1853 1854 if (!drm_dev_enter(drm, &idx)) 1855 return; 1856 1857 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1858 rational_best_approximation(hsm_clock, samplerate, 1859 VC4_HD_MAI_SMP_N_MASK >> 1860 VC4_HD_MAI_SMP_N_SHIFT, 1861 (VC4_HD_MAI_SMP_M_MASK >> 1862 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1863 &n, &m); 1864 1865 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1866 HDMI_WRITE(HDMI_MAI_SMP, 1867 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1868 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1869 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1870 1871 drm_dev_exit(idx); 1872 } 1873 1874 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1875 { 1876 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1877 u32 n, cts; 1878 u64 tmp; 1879 1880 lockdep_assert_held(&vc4_hdmi->mutex); 1881 lockdep_assert_held(&vc4_hdmi->hw_lock); 1882 1883 n = 128 * samplerate / 1000; 1884 tmp = (u64)(mode->clock * 1000) * n; 1885 do_div(tmp, 128 * samplerate); 1886 cts = tmp; 1887 1888 HDMI_WRITE(HDMI_CRP_CFG, 1889 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1890 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1891 1892 /* 1893 * We could get slightly more accurate clocks in some cases by 1894 * providing a CTS_1 value. The two CTS values are alternated 1895 * between based on the period fields 1896 */ 1897 HDMI_WRITE(HDMI_CTS_0, cts); 1898 HDMI_WRITE(HDMI_CTS_1, cts); 1899 } 1900 1901 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1902 { 1903 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1904 1905 return snd_soc_card_get_drvdata(card); 1906 } 1907 1908 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1909 { 1910 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1911 1912 lockdep_assert_held(&vc4_hdmi->mutex); 1913 1914 /* 1915 * If the encoder is currently in DVI mode, treat the codec DAI 1916 * as missing. 1917 */ 1918 if (!display->is_hdmi) 1919 return false; 1920 1921 return true; 1922 } 1923 1924 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1925 { 1926 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1927 struct drm_device *drm = vc4_hdmi->connector.dev; 1928 unsigned long flags; 1929 int ret = 0; 1930 int idx; 1931 1932 mutex_lock(&vc4_hdmi->mutex); 1933 1934 if (!drm_dev_enter(drm, &idx)) { 1935 ret = -ENODEV; 1936 goto out; 1937 } 1938 1939 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1940 ret = -ENOTSUPP; 1941 goto out_dev_exit; 1942 } 1943 1944 vc4_hdmi->audio.streaming = true; 1945 1946 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1947 HDMI_WRITE(HDMI_MAI_CTL, 1948 VC4_HD_MAI_CTL_RESET | 1949 VC4_HD_MAI_CTL_FLUSH | 1950 VC4_HD_MAI_CTL_DLATE | 1951 VC4_HD_MAI_CTL_ERRORE | 1952 VC4_HD_MAI_CTL_ERRORF); 1953 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1954 1955 if (vc4_hdmi->variant->phy_rng_enable) 1956 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1957 1958 out_dev_exit: 1959 drm_dev_exit(idx); 1960 out: 1961 mutex_unlock(&vc4_hdmi->mutex); 1962 1963 return ret; 1964 } 1965 1966 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1967 { 1968 struct device *dev = &vc4_hdmi->pdev->dev; 1969 unsigned long flags; 1970 int ret; 1971 1972 lockdep_assert_held(&vc4_hdmi->mutex); 1973 1974 vc4_hdmi->audio.streaming = false; 1975 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false); 1976 if (ret) 1977 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1978 1979 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1980 1981 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1982 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1983 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1984 1985 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1986 } 1987 1988 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1989 { 1990 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1991 struct drm_device *drm = vc4_hdmi->connector.dev; 1992 unsigned long flags; 1993 int idx; 1994 1995 mutex_lock(&vc4_hdmi->mutex); 1996 1997 if (!drm_dev_enter(drm, &idx)) 1998 goto out; 1999 2000 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2001 2002 HDMI_WRITE(HDMI_MAI_CTL, 2003 VC4_HD_MAI_CTL_DLATE | 2004 VC4_HD_MAI_CTL_ERRORE | 2005 VC4_HD_MAI_CTL_ERRORF); 2006 2007 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2008 2009 if (vc4_hdmi->variant->phy_rng_disable) 2010 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 2011 2012 vc4_hdmi->audio.streaming = false; 2013 vc4_hdmi_audio_reset(vc4_hdmi); 2014 2015 drm_dev_exit(idx); 2016 2017 out: 2018 mutex_unlock(&vc4_hdmi->mutex); 2019 } 2020 2021 static int sample_rate_to_mai_fmt(int samplerate) 2022 { 2023 switch (samplerate) { 2024 case 8000: 2025 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2026 case 11025: 2027 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2028 case 12000: 2029 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2030 case 16000: 2031 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2032 case 22050: 2033 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2034 case 24000: 2035 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2036 case 32000: 2037 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2038 case 44100: 2039 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2040 case 48000: 2041 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2042 case 64000: 2043 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2044 case 88200: 2045 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2046 case 96000: 2047 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2048 case 128000: 2049 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2050 case 176400: 2051 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2052 case 192000: 2053 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2054 default: 2055 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2056 } 2057 } 2058 2059 /* HDMI audio codec callbacks */ 2060 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 2061 struct hdmi_codec_daifmt *daifmt, 2062 struct hdmi_codec_params *params) 2063 { 2064 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2065 struct drm_device *drm = vc4_hdmi->connector.dev; 2066 struct drm_connector *connector = &vc4_hdmi->connector; 2067 struct vc4_dev *vc4 = to_vc4_dev(drm); 2068 unsigned int sample_rate = params->sample_rate; 2069 unsigned int channels = params->channels; 2070 unsigned long flags; 2071 u32 audio_packet_config, channel_mask; 2072 u32 channel_map; 2073 u32 mai_audio_format; 2074 u32 mai_sample_rate; 2075 int ret = 0; 2076 int idx; 2077 2078 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2079 sample_rate, params->sample_width, channels); 2080 2081 mutex_lock(&vc4_hdmi->mutex); 2082 2083 if (!drm_dev_enter(drm, &idx)) { 2084 ret = -ENODEV; 2085 goto out; 2086 } 2087 2088 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2089 ret = -EINVAL; 2090 goto out_dev_exit; 2091 } 2092 2093 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2094 2095 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2096 HDMI_WRITE(HDMI_MAI_CTL, 2097 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2098 VC4_HD_MAI_CTL_WHOLSMP | 2099 VC4_HD_MAI_CTL_CHALIGN | 2100 VC4_HD_MAI_CTL_ENABLE); 2101 2102 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2103 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2104 params->channels == 8) 2105 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2106 else 2107 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2108 HDMI_WRITE(HDMI_MAI_FMT, 2109 VC4_SET_FIELD(mai_sample_rate, 2110 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2111 VC4_SET_FIELD(mai_audio_format, 2112 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2113 2114 /* The B frame identifier should match the value used by alsa-lib (8) */ 2115 audio_packet_config = 2116 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2117 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2118 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2119 2120 channel_mask = GENMASK(channels - 1, 0); 2121 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2122 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2123 2124 /* Set the MAI threshold */ 2125 switch (vc4->gen) { 2126 case VC4_GEN_6_D: 2127 HDMI_WRITE(HDMI_MAI_THR, 2128 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) | 2129 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) | 2130 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) | 2131 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW)); 2132 break; 2133 case VC4_GEN_6_C: 2134 case VC4_GEN_5: 2135 HDMI_WRITE(HDMI_MAI_THR, 2136 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 2137 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 2138 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) | 2139 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW)); 2140 break; 2141 case VC4_GEN_4: 2142 HDMI_WRITE(HDMI_MAI_THR, 2143 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) | 2144 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) | 2145 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) | 2146 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW)); 2147 break; 2148 default: 2149 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen); 2150 break; 2151 } 2152 2153 HDMI_WRITE(HDMI_MAI_CONFIG, 2154 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2155 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2156 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2157 2158 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2159 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2160 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2161 2162 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2163 2164 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2165 2166 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, 2167 ¶ms->cea); 2168 if (ret) 2169 goto out_dev_exit; 2170 2171 out_dev_exit: 2172 drm_dev_exit(idx); 2173 out: 2174 mutex_unlock(&vc4_hdmi->mutex); 2175 2176 return ret; 2177 } 2178 2179 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2180 .name = "vc4-hdmi-cpu-dai-component", 2181 .legacy_dai_naming = 1, 2182 }; 2183 2184 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2185 { 2186 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2187 2188 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2189 2190 return 0; 2191 } 2192 2193 static const struct snd_soc_dai_ops vc4_snd_dai_ops = { 2194 .probe = vc4_hdmi_audio_cpu_dai_probe, 2195 }; 2196 2197 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2198 .name = "vc4-hdmi-cpu-dai", 2199 .ops = &vc4_snd_dai_ops, 2200 .playback = { 2201 .stream_name = "Playback", 2202 .channels_min = 1, 2203 .channels_max = 8, 2204 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2205 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2206 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2207 SNDRV_PCM_RATE_192000, 2208 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2209 }, 2210 }; 2211 2212 static const struct snd_dmaengine_pcm_config pcm_conf = { 2213 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2214 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2215 }; 2216 2217 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2218 uint8_t *buf, size_t len) 2219 { 2220 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2221 struct drm_connector *connector = &vc4_hdmi->connector; 2222 2223 mutex_lock(&connector->eld_mutex); 2224 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2225 mutex_unlock(&connector->eld_mutex); 2226 2227 return 0; 2228 } 2229 2230 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2231 .get_eld = vc4_hdmi_audio_get_eld, 2232 .prepare = vc4_hdmi_audio_prepare, 2233 .audio_shutdown = vc4_hdmi_audio_shutdown, 2234 .audio_startup = vc4_hdmi_audio_startup, 2235 }; 2236 2237 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2238 .ops = &vc4_hdmi_codec_ops, 2239 .max_i2s_channels = 8, 2240 .i2s = 1, 2241 }; 2242 2243 static void vc4_hdmi_audio_codec_release(void *ptr) 2244 { 2245 struct vc4_hdmi *vc4_hdmi = ptr; 2246 2247 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 2248 vc4_hdmi->audio.codec_pdev = NULL; 2249 } 2250 2251 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2252 { 2253 const struct vc4_hdmi_register *mai_data = 2254 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2255 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2256 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2257 struct device *dev = &vc4_hdmi->pdev->dev; 2258 struct platform_device *codec_pdev; 2259 const __be32 *addr; 2260 int index, len; 2261 int ret; 2262 2263 /* 2264 * ASoC makes it a bit hard to retrieve a pointer to the 2265 * vc4_hdmi structure. Registering the card will overwrite our 2266 * device drvdata with a pointer to the snd_soc_card structure, 2267 * which can then be used to retrieve whatever drvdata we want 2268 * to associate. 2269 * 2270 * However, that doesn't fly in the case where we wouldn't 2271 * register an ASoC card (because of an old DT that is missing 2272 * the dmas properties for example), then the card isn't 2273 * registered and the device drvdata wouldn't be set. 2274 * 2275 * We can deal with both cases by making sure a snd_soc_card 2276 * pointer and a vc4_hdmi structure are pointing to the same 2277 * memory address, so we can treat them indistinctly without any 2278 * issue. 2279 */ 2280 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2281 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2282 2283 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2284 dev_warn(dev, 2285 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2286 return 0; 2287 } 2288 2289 if (mai_data->reg != VC4_HD) { 2290 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2291 return -EINVAL; 2292 } 2293 2294 /* 2295 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2296 * the bus address specified in the DT, because the physical address 2297 * (the one returned by platform_get_resource()) is not appropriate 2298 * for DMA transfers. 2299 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2300 */ 2301 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2302 /* Before BCM2711, we don't have a named register range */ 2303 if (index < 0) 2304 index = 1; 2305 2306 addr = of_get_address(dev->of_node, index, NULL, NULL); 2307 if (!addr) 2308 return -EINVAL; 2309 2310 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2311 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2312 vc4_hdmi->audio.dma_data.maxburst = 2; 2313 2314 /* 2315 * NOTE: Strictly speaking, we should probably use a DRM-managed 2316 * registration there to avoid removing all the audio components 2317 * by the time the driver doesn't have any user anymore. 2318 * 2319 * However, the ASoC core uses a number of devm_kzalloc calls 2320 * when registering, even when using non-device-managed 2321 * functions (such as in snd_soc_register_component()). 2322 * 2323 * If we call snd_soc_unregister_component() in a DRM-managed 2324 * action, the device-managed actions have already been executed 2325 * and thus we would access memory that has been freed. 2326 * 2327 * Using device-managed hooks here probably leaves us open to a 2328 * bunch of issues if userspace still has a handle on the ALSA 2329 * device when the device is removed. However, this is mitigated 2330 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2331 * path to prevent the access to the device resources if it 2332 * isn't there anymore. 2333 * 2334 * Then, the vc4_hdmi structure is DRM-managed and thus only 2335 * freed whenever the last user has closed the DRM device file. 2336 * It should thus outlive ALSA in most situations. 2337 */ 2338 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2339 if (ret) { 2340 dev_err(dev, "Could not register PCM component: %d\n", ret); 2341 return ret; 2342 } 2343 2344 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2345 &vc4_hdmi_audio_cpu_dai_drv, 1); 2346 if (ret) { 2347 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2348 return ret; 2349 } 2350 2351 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2352 PLATFORM_DEVID_AUTO, 2353 &vc4_hdmi_codec_pdata, 2354 sizeof(vc4_hdmi_codec_pdata)); 2355 if (IS_ERR(codec_pdev)) { 2356 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2357 return PTR_ERR(codec_pdev); 2358 } 2359 vc4_hdmi->audio.codec_pdev = codec_pdev; 2360 2361 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi); 2362 if (ret) 2363 return ret; 2364 2365 dai_link->cpus = &vc4_hdmi->audio.cpu; 2366 dai_link->codecs = &vc4_hdmi->audio.codec; 2367 dai_link->platforms = &vc4_hdmi->audio.platform; 2368 2369 dai_link->num_cpus = 1; 2370 dai_link->num_codecs = 1; 2371 dai_link->num_platforms = 1; 2372 2373 dai_link->name = "MAI"; 2374 dai_link->stream_name = "MAI PCM"; 2375 dai_link->codecs->dai_name = "i2s-hifi"; 2376 dai_link->cpus->dai_name = dev_name(dev); 2377 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2378 dai_link->platforms->name = dev_name(dev); 2379 2380 card->dai_link = dai_link; 2381 card->num_links = 1; 2382 card->name = vc4_hdmi->variant->card_name; 2383 card->driver_name = "vc4-hdmi"; 2384 card->dev = dev; 2385 card->owner = THIS_MODULE; 2386 2387 /* 2388 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2389 * stores a pointer to the snd card object in dev->driver_data. This 2390 * means we cannot use it for something else. The hdmi back-pointer is 2391 * now stored in card->drvdata and should be retrieved with 2392 * snd_soc_card_get_drvdata() if needed. 2393 */ 2394 snd_soc_card_set_drvdata(card, vc4_hdmi); 2395 ret = devm_snd_soc_register_card(dev, card); 2396 if (ret) 2397 dev_err_probe(dev, ret, "Could not register sound card\n"); 2398 2399 return ret; 2400 2401 } 2402 2403 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2404 { 2405 struct vc4_hdmi *vc4_hdmi = priv; 2406 struct drm_connector *connector = &vc4_hdmi->connector; 2407 struct drm_device *dev = connector->dev; 2408 2409 if (dev && dev->registered) 2410 drm_connector_helper_hpd_irq_event(connector); 2411 2412 return IRQ_HANDLED; 2413 } 2414 2415 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2416 { 2417 struct drm_connector *connector = &vc4_hdmi->connector; 2418 struct platform_device *pdev = vc4_hdmi->pdev; 2419 int ret; 2420 2421 if (vc4_hdmi->variant->external_irq_controller) { 2422 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2423 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2424 2425 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2426 NULL, 2427 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2428 "vc4 hdmi hpd connected", vc4_hdmi); 2429 if (ret) 2430 return ret; 2431 2432 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2433 NULL, 2434 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2435 "vc4 hdmi hpd disconnected", vc4_hdmi); 2436 if (ret) 2437 return ret; 2438 2439 connector->polled = DRM_CONNECTOR_POLL_HPD; 2440 } 2441 2442 return 0; 2443 } 2444 2445 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2446 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2447 { 2448 struct vc4_hdmi *vc4_hdmi = priv; 2449 2450 if (vc4_hdmi->cec_rx_msg.len) 2451 cec_received_msg(vc4_hdmi->cec_adap, 2452 &vc4_hdmi->cec_rx_msg); 2453 2454 return IRQ_HANDLED; 2455 } 2456 2457 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2458 { 2459 struct vc4_hdmi *vc4_hdmi = priv; 2460 2461 if (vc4_hdmi->cec_tx_ok) { 2462 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2463 0, 0, 0, 0); 2464 } else { 2465 /* 2466 * This CEC implementation makes 1 retry, so if we 2467 * get a NACK, then that means it made 2 attempts. 2468 */ 2469 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2470 0, 2, 0, 0); 2471 } 2472 return IRQ_HANDLED; 2473 } 2474 2475 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2476 { 2477 struct vc4_hdmi *vc4_hdmi = priv; 2478 irqreturn_t ret; 2479 2480 if (vc4_hdmi->cec_irq_was_rx) 2481 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2482 else 2483 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2484 2485 return ret; 2486 } 2487 2488 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2489 { 2490 struct drm_device *dev = vc4_hdmi->connector.dev; 2491 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2492 unsigned int i; 2493 2494 lockdep_assert_held(&vc4_hdmi->hw_lock); 2495 2496 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2497 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2498 2499 if (msg->len > 16) { 2500 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2501 return; 2502 } 2503 2504 for (i = 0; i < msg->len; i += 4) { 2505 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2506 2507 msg->msg[i] = val & 0xff; 2508 msg->msg[i + 1] = (val >> 8) & 0xff; 2509 msg->msg[i + 2] = (val >> 16) & 0xff; 2510 msg->msg[i + 3] = (val >> 24) & 0xff; 2511 } 2512 } 2513 2514 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2515 { 2516 u32 cntrl1; 2517 2518 /* 2519 * We don't need to protect the register access using 2520 * drm_dev_enter() there because the interrupt handler lifetime 2521 * is tied to the device itself, and not to the DRM device. 2522 * 2523 * So when the device will be gone, one of the first thing we 2524 * will be doing will be to unregister the interrupt handler, 2525 * and then unregister the DRM device. drm_dev_enter() would 2526 * thus always succeed if we are here. 2527 */ 2528 2529 lockdep_assert_held(&vc4_hdmi->hw_lock); 2530 2531 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2532 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2533 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2534 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2535 2536 return IRQ_WAKE_THREAD; 2537 } 2538 2539 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2540 { 2541 struct vc4_hdmi *vc4_hdmi = priv; 2542 irqreturn_t ret; 2543 2544 spin_lock(&vc4_hdmi->hw_lock); 2545 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2546 spin_unlock(&vc4_hdmi->hw_lock); 2547 2548 return ret; 2549 } 2550 2551 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2552 { 2553 u32 cntrl1; 2554 2555 lockdep_assert_held(&vc4_hdmi->hw_lock); 2556 2557 /* 2558 * We don't need to protect the register access using 2559 * drm_dev_enter() there because the interrupt handler lifetime 2560 * is tied to the device itself, and not to the DRM device. 2561 * 2562 * So when the device will be gone, one of the first thing we 2563 * will be doing will be to unregister the interrupt handler, 2564 * and then unregister the DRM device. drm_dev_enter() would 2565 * thus always succeed if we are here. 2566 */ 2567 2568 vc4_hdmi->cec_rx_msg.len = 0; 2569 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2570 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2571 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2572 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2573 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2574 2575 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2576 2577 return IRQ_WAKE_THREAD; 2578 } 2579 2580 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2581 { 2582 struct vc4_hdmi *vc4_hdmi = priv; 2583 irqreturn_t ret; 2584 2585 spin_lock(&vc4_hdmi->hw_lock); 2586 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2587 spin_unlock(&vc4_hdmi->hw_lock); 2588 2589 return ret; 2590 } 2591 2592 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2593 { 2594 struct vc4_hdmi *vc4_hdmi = priv; 2595 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2596 irqreturn_t ret; 2597 u32 cntrl5; 2598 2599 /* 2600 * We don't need to protect the register access using 2601 * drm_dev_enter() there because the interrupt handler lifetime 2602 * is tied to the device itself, and not to the DRM device. 2603 * 2604 * So when the device will be gone, one of the first thing we 2605 * will be doing will be to unregister the interrupt handler, 2606 * and then unregister the DRM device. drm_dev_enter() would 2607 * thus always succeed if we are here. 2608 */ 2609 2610 if (!(stat & VC4_HDMI_CPU_CEC)) 2611 return IRQ_NONE; 2612 2613 spin_lock(&vc4_hdmi->hw_lock); 2614 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2615 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2616 if (vc4_hdmi->cec_irq_was_rx) 2617 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2618 else 2619 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2620 2621 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2622 spin_unlock(&vc4_hdmi->hw_lock); 2623 2624 return ret; 2625 } 2626 2627 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2628 { 2629 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2630 struct drm_device *drm = vc4_hdmi->connector.dev; 2631 /* clock period in microseconds */ 2632 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2633 unsigned long flags; 2634 u32 val; 2635 int ret; 2636 int idx; 2637 2638 if (!drm_dev_enter(drm, &idx)) 2639 /* 2640 * We can't return an error code, because the CEC 2641 * framework will emit WARN_ON messages at unbind 2642 * otherwise. 2643 */ 2644 return 0; 2645 2646 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2647 if (ret) { 2648 drm_dev_exit(idx); 2649 return ret; 2650 } 2651 2652 mutex_lock(&vc4_hdmi->mutex); 2653 2654 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2655 2656 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2657 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2658 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2659 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2660 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2661 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2662 2663 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2664 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2665 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2666 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2667 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2668 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2669 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2670 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2671 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2672 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2673 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2674 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2675 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2676 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2677 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2678 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2679 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2680 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2681 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2682 2683 if (!vc4_hdmi->variant->external_irq_controller) 2684 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2685 2686 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2687 2688 mutex_unlock(&vc4_hdmi->mutex); 2689 drm_dev_exit(idx); 2690 2691 return 0; 2692 } 2693 2694 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2695 { 2696 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2697 struct drm_device *drm = vc4_hdmi->connector.dev; 2698 unsigned long flags; 2699 int idx; 2700 2701 if (!drm_dev_enter(drm, &idx)) 2702 /* 2703 * We can't return an error code, because the CEC 2704 * framework will emit WARN_ON messages at unbind 2705 * otherwise. 2706 */ 2707 return 0; 2708 2709 mutex_lock(&vc4_hdmi->mutex); 2710 2711 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2712 2713 if (!vc4_hdmi->variant->external_irq_controller) 2714 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2715 2716 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2717 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2718 2719 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2720 2721 mutex_unlock(&vc4_hdmi->mutex); 2722 2723 pm_runtime_put(&vc4_hdmi->pdev->dev); 2724 2725 drm_dev_exit(idx); 2726 2727 return 0; 2728 } 2729 2730 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2731 { 2732 if (enable) 2733 return vc4_hdmi_cec_enable(adap); 2734 else 2735 return vc4_hdmi_cec_disable(adap); 2736 } 2737 2738 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2739 { 2740 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2741 struct drm_device *drm = vc4_hdmi->connector.dev; 2742 unsigned long flags; 2743 int idx; 2744 2745 if (!drm_dev_enter(drm, &idx)) 2746 /* 2747 * We can't return an error code, because the CEC 2748 * framework will emit WARN_ON messages at unbind 2749 * otherwise. 2750 */ 2751 return 0; 2752 2753 mutex_lock(&vc4_hdmi->mutex); 2754 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2755 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2756 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2757 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2758 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2759 mutex_unlock(&vc4_hdmi->mutex); 2760 2761 drm_dev_exit(idx); 2762 2763 return 0; 2764 } 2765 2766 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2767 u32 signal_free_time, struct cec_msg *msg) 2768 { 2769 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2770 struct drm_device *dev = vc4_hdmi->connector.dev; 2771 unsigned long flags; 2772 u32 val; 2773 unsigned int i; 2774 int idx; 2775 2776 if (!drm_dev_enter(dev, &idx)) 2777 return -ENODEV; 2778 2779 if (msg->len > 16) { 2780 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2781 drm_dev_exit(idx); 2782 return -ENOMEM; 2783 } 2784 2785 mutex_lock(&vc4_hdmi->mutex); 2786 2787 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2788 2789 for (i = 0; i < msg->len; i += 4) 2790 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2791 (msg->msg[i]) | 2792 (msg->msg[i + 1] << 8) | 2793 (msg->msg[i + 2] << 16) | 2794 (msg->msg[i + 3] << 24)); 2795 2796 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2797 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2798 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2799 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2800 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2801 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2802 2803 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2804 2805 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2806 mutex_unlock(&vc4_hdmi->mutex); 2807 drm_dev_exit(idx); 2808 2809 return 0; 2810 } 2811 2812 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2813 .adap_enable = vc4_hdmi_cec_adap_enable, 2814 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2815 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2816 }; 2817 2818 static void vc4_hdmi_cec_release(void *ptr) 2819 { 2820 struct vc4_hdmi *vc4_hdmi = ptr; 2821 2822 cec_unregister_adapter(vc4_hdmi->cec_adap); 2823 vc4_hdmi->cec_adap = NULL; 2824 } 2825 2826 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2827 { 2828 struct cec_connector_info conn_info; 2829 struct platform_device *pdev = vc4_hdmi->pdev; 2830 struct device *dev = &pdev->dev; 2831 int ret; 2832 2833 if (!of_property_present(dev->of_node, "interrupts")) { 2834 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2835 return 0; 2836 } 2837 2838 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2839 vc4_hdmi, 2840 vc4_hdmi->variant->card_name, 2841 CEC_CAP_DEFAULTS | 2842 CEC_CAP_CONNECTOR_INFO, 1); 2843 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2844 if (ret < 0) 2845 return ret; 2846 2847 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2848 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2849 2850 if (vc4_hdmi->variant->external_irq_controller) { 2851 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 2852 vc4_cec_irq_handler_rx_bare, 2853 vc4_cec_irq_handler_rx_thread, 0, 2854 "vc4 hdmi cec rx", vc4_hdmi); 2855 if (ret) 2856 goto err_delete_cec_adap; 2857 2858 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 2859 vc4_cec_irq_handler_tx_bare, 2860 vc4_cec_irq_handler_tx_thread, 0, 2861 "vc4 hdmi cec tx", vc4_hdmi); 2862 if (ret) 2863 goto err_delete_cec_adap; 2864 } else { 2865 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 2866 vc4_cec_irq_handler, 2867 vc4_cec_irq_handler_thread, 0, 2868 "vc4 hdmi cec", vc4_hdmi); 2869 if (ret) 2870 goto err_delete_cec_adap; 2871 } 2872 2873 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2874 if (ret < 0) 2875 goto err_delete_cec_adap; 2876 2877 /* 2878 * NOTE: Strictly speaking, we should probably use a DRM-managed 2879 * registration there to avoid removing the CEC adapter by the 2880 * time the DRM driver doesn't have any user anymore. 2881 * 2882 * However, the CEC framework already cleans up the CEC adapter 2883 * only when the last user has closed its file descriptor, so we 2884 * don't need to handle it in DRM. 2885 * 2886 * By the time the device-managed hook is executed, we will give 2887 * up our reference to the CEC adapter and therefore don't 2888 * really care when it's actually freed. 2889 * 2890 * There's still a problematic sequence: if we unregister our 2891 * CEC adapter, but the userspace keeps a handle on the CEC 2892 * adapter but not the DRM device for some reason. In such a 2893 * case, our vc4_hdmi structure will be freed, but the 2894 * cec_adapter structure will have a dangling pointer to what 2895 * used to be our HDMI controller. If we get a CEC call at that 2896 * moment, we could end up with a use-after-free. Fortunately, 2897 * the CEC framework already handles this too, by calling 2898 * cec_is_registered() in cec_ioctl() and cec_poll(). 2899 */ 2900 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi); 2901 if (ret) 2902 return ret; 2903 2904 return 0; 2905 2906 err_delete_cec_adap: 2907 cec_delete_adapter(vc4_hdmi->cec_adap); 2908 2909 return ret; 2910 } 2911 #else 2912 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2913 { 2914 return 0; 2915 } 2916 #endif 2917 2918 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 2919 { 2920 struct debugfs_reg32 *regs = ptr; 2921 2922 kfree(regs); 2923 } 2924 2925 static int vc4_hdmi_build_regset(struct drm_device *drm, 2926 struct vc4_hdmi *vc4_hdmi, 2927 struct debugfs_regset32 *regset, 2928 enum vc4_hdmi_regs reg) 2929 { 2930 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2931 struct debugfs_reg32 *regs, *new_regs; 2932 unsigned int count = 0; 2933 unsigned int i; 2934 int ret; 2935 2936 regs = kcalloc(variant->num_registers, sizeof(*regs), 2937 GFP_KERNEL); 2938 if (!regs) 2939 return -ENOMEM; 2940 2941 for (i = 0; i < variant->num_registers; i++) { 2942 const struct vc4_hdmi_register *field = &variant->registers[i]; 2943 2944 if (field->reg != reg) 2945 continue; 2946 2947 regs[count].name = field->name; 2948 regs[count].offset = field->offset; 2949 count++; 2950 } 2951 2952 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2953 if (!new_regs) 2954 return -ENOMEM; 2955 2956 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2957 regset->regs = new_regs; 2958 regset->nregs = count; 2959 2960 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 2961 if (ret) 2962 return ret; 2963 2964 return 0; 2965 } 2966 2967 static int vc4_hdmi_init_resources(struct drm_device *drm, 2968 struct vc4_hdmi *vc4_hdmi) 2969 { 2970 struct platform_device *pdev = vc4_hdmi->pdev; 2971 struct device *dev = &pdev->dev; 2972 int ret; 2973 2974 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2975 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2976 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2977 2978 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2979 if (IS_ERR(vc4_hdmi->hd_regs)) 2980 return PTR_ERR(vc4_hdmi->hd_regs); 2981 2982 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2983 if (ret) 2984 return ret; 2985 2986 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2987 if (ret) 2988 return ret; 2989 2990 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2991 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2992 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2993 if (ret != -EPROBE_DEFER) 2994 drm_err(drm, "Failed to get pixel clock\n"); 2995 return ret; 2996 } 2997 2998 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2999 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3000 drm_err(drm, "Failed to get HDMI state machine clock\n"); 3001 return PTR_ERR(vc4_hdmi->hsm_clock); 3002 } 3003 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 3004 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 3005 3006 return 0; 3007 } 3008 3009 static int vc5_hdmi_init_resources(struct drm_device *drm, 3010 struct vc4_hdmi *vc4_hdmi) 3011 { 3012 struct platform_device *pdev = vc4_hdmi->pdev; 3013 struct device *dev = &pdev->dev; 3014 struct resource *res; 3015 int ret; 3016 3017 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 3018 if (!res) 3019 return -ENODEV; 3020 3021 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 3022 resource_size(res)); 3023 if (!vc4_hdmi->hdmicore_regs) 3024 return -ENOMEM; 3025 3026 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 3027 if (!res) 3028 return -ENODEV; 3029 3030 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 3031 if (!vc4_hdmi->hd_regs) 3032 return -ENOMEM; 3033 3034 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 3035 if (!res) 3036 return -ENODEV; 3037 3038 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 3039 if (!vc4_hdmi->cec_regs) 3040 return -ENOMEM; 3041 3042 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 3043 if (!res) 3044 return -ENODEV; 3045 3046 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 3047 if (!vc4_hdmi->csc_regs) 3048 return -ENOMEM; 3049 3050 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 3051 if (!res) 3052 return -ENODEV; 3053 3054 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 3055 if (!vc4_hdmi->dvp_regs) 3056 return -ENOMEM; 3057 3058 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 3059 if (!res) 3060 return -ENODEV; 3061 3062 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 3063 if (!vc4_hdmi->phy_regs) 3064 return -ENOMEM; 3065 3066 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 3067 if (!res) 3068 return -ENODEV; 3069 3070 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 3071 if (!vc4_hdmi->ram_regs) 3072 return -ENOMEM; 3073 3074 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 3075 if (!res) 3076 return -ENODEV; 3077 3078 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 3079 if (!vc4_hdmi->rm_regs) 3080 return -ENOMEM; 3081 3082 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3083 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3084 drm_err(drm, "Failed to get HDMI state machine clock\n"); 3085 return PTR_ERR(vc4_hdmi->hsm_clock); 3086 } 3087 3088 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3089 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3090 drm_err(drm, "Failed to get pixel bvb clock\n"); 3091 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3092 } 3093 3094 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3095 if (IS_ERR(vc4_hdmi->audio_clock)) { 3096 drm_err(drm, "Failed to get audio clock\n"); 3097 return PTR_ERR(vc4_hdmi->audio_clock); 3098 } 3099 3100 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3101 if (IS_ERR(vc4_hdmi->cec_clock)) { 3102 drm_err(drm, "Failed to get CEC clock\n"); 3103 return PTR_ERR(vc4_hdmi->cec_clock); 3104 } 3105 3106 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3107 if (IS_ERR(vc4_hdmi->reset)) { 3108 drm_err(drm, "Failed to get HDMI reset line\n"); 3109 return PTR_ERR(vc4_hdmi->reset); 3110 } 3111 3112 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3113 if (ret) 3114 return ret; 3115 3116 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3117 if (ret) 3118 return ret; 3119 3120 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3121 if (ret) 3122 return ret; 3123 3124 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3125 if (ret) 3126 return ret; 3127 3128 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3129 if (ret) 3130 return ret; 3131 3132 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3133 if (ret) 3134 return ret; 3135 3136 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3137 if (ret) 3138 return ret; 3139 3140 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3141 if (ret) 3142 return ret; 3143 3144 return 0; 3145 } 3146 3147 static int vc4_hdmi_runtime_suspend(struct device *dev) 3148 { 3149 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3150 3151 clk_disable_unprepare(vc4_hdmi->audio_clock); 3152 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3153 3154 return 0; 3155 } 3156 3157 static int vc4_hdmi_runtime_resume(struct device *dev) 3158 { 3159 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3160 unsigned long __maybe_unused flags; 3161 u32 __maybe_unused value; 3162 unsigned long rate; 3163 int ret; 3164 3165 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3166 if (ret) 3167 return ret; 3168 3169 /* 3170 * Whenever the RaspberryPi boots without an HDMI monitor 3171 * plugged in, the firmware won't have initialized the HSM clock 3172 * rate and it will be reported as 0. 3173 * 3174 * If we try to access a register of the controller in such a 3175 * case, it will lead to a silent CPU stall. Let's make sure we 3176 * prevent such a case. 3177 */ 3178 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3179 if (!rate) { 3180 ret = -EINVAL; 3181 goto err_disable_clk; 3182 } 3183 3184 ret = clk_prepare_enable(vc4_hdmi->audio_clock); 3185 if (ret) 3186 goto err_disable_clk; 3187 3188 if (vc4_hdmi->variant->reset) 3189 vc4_hdmi->variant->reset(vc4_hdmi); 3190 3191 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3192 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3193 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3194 /* Set the logical address to Unregistered */ 3195 value |= VC4_HDMI_CEC_ADDR_MASK; 3196 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3197 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3198 3199 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3200 3201 if (!vc4_hdmi->variant->external_irq_controller) { 3202 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3203 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3204 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3205 } 3206 #endif 3207 3208 return 0; 3209 3210 err_disable_clk: 3211 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3212 return ret; 3213 } 3214 3215 static void vc4_hdmi_put_ddc_device(void *ptr) 3216 { 3217 struct vc4_hdmi *vc4_hdmi = ptr; 3218 3219 put_device(&vc4_hdmi->ddc->dev); 3220 } 3221 3222 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3223 { 3224 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3225 struct platform_device *pdev = to_platform_device(dev); 3226 struct drm_device *drm = dev_get_drvdata(master); 3227 struct vc4_hdmi *vc4_hdmi; 3228 struct drm_encoder *encoder; 3229 struct device_node *ddc_node; 3230 int ret; 3231 3232 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3233 if (!vc4_hdmi) 3234 return -ENOMEM; 3235 3236 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3237 if (ret) 3238 return ret; 3239 3240 spin_lock_init(&vc4_hdmi->hw_lock); 3241 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3242 3243 dev_set_drvdata(dev, vc4_hdmi); 3244 encoder = &vc4_hdmi->encoder.base; 3245 vc4_hdmi->encoder.type = variant->encoder_type; 3246 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3247 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3248 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3249 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3250 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3251 vc4_hdmi->pdev = pdev; 3252 vc4_hdmi->variant = variant; 3253 3254 /* 3255 * Since we don't know the state of the controller and its 3256 * display (if any), let's assume it's always enabled. 3257 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3258 * sure it's disabled, and avoid any inconsistency. 3259 */ 3260 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3261 vc4_hdmi->scdc_enabled = true; 3262 3263 ret = variant->init_resources(drm, vc4_hdmi); 3264 if (ret) 3265 return ret; 3266 3267 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3268 if (!ddc_node) { 3269 drm_err(drm, "Failed to find ddc node in device tree\n"); 3270 return -ENODEV; 3271 } 3272 3273 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3274 of_node_put(ddc_node); 3275 if (!vc4_hdmi->ddc) { 3276 drm_err(drm, "Failed to get ddc i2c adapter by node\n"); 3277 return -EPROBE_DEFER; 3278 } 3279 3280 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3281 if (ret) 3282 return ret; 3283 3284 /* Only use the GPIO HPD pin if present in the DT, otherwise 3285 * we'll use the HDMI core's register. 3286 */ 3287 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3288 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3289 return PTR_ERR(vc4_hdmi->hpd_gpio); 3290 } 3291 3292 vc4_hdmi->disable_wifi_frequencies = 3293 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3294 3295 ret = devm_pm_runtime_enable(dev); 3296 if (ret) 3297 return ret; 3298 3299 /* 3300 * We need to have the device powered up at this point to call 3301 * our reset hook and for the CEC init. 3302 */ 3303 ret = pm_runtime_resume_and_get(dev); 3304 if (ret) 3305 return ret; 3306 3307 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3308 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") || 3309 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") || 3310 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) && 3311 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3312 clk_prepare_enable(vc4_hdmi->pixel_clock); 3313 clk_prepare_enable(vc4_hdmi->hsm_clock); 3314 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3315 } 3316 3317 ret = drmm_encoder_init(drm, encoder, 3318 &vc4_hdmi_encoder_funcs, 3319 DRM_MODE_ENCODER_TMDS, 3320 NULL); 3321 if (ret) 3322 goto err_put_runtime_pm; 3323 3324 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3325 3326 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3327 if (ret) 3328 goto err_put_runtime_pm; 3329 3330 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3331 if (ret) 3332 goto err_put_runtime_pm; 3333 3334 ret = vc4_hdmi_cec_init(vc4_hdmi); 3335 if (ret) 3336 goto err_put_runtime_pm; 3337 3338 ret = vc4_hdmi_audio_init(vc4_hdmi); 3339 if (ret) 3340 goto err_put_runtime_pm; 3341 3342 pm_runtime_put_sync(dev); 3343 3344 return 0; 3345 3346 err_put_runtime_pm: 3347 pm_runtime_put_sync(dev); 3348 3349 return ret; 3350 } 3351 3352 static const struct component_ops vc4_hdmi_ops = { 3353 .bind = vc4_hdmi_bind, 3354 }; 3355 3356 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3357 { 3358 return component_add(&pdev->dev, &vc4_hdmi_ops); 3359 } 3360 3361 static void vc4_hdmi_dev_remove(struct platform_device *pdev) 3362 { 3363 component_del(&pdev->dev, &vc4_hdmi_ops); 3364 } 3365 3366 static const struct vc4_hdmi_variant bcm2835_variant = { 3367 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3368 .debugfs_name = "hdmi_regs", 3369 .card_name = "vc4-hdmi", 3370 .max_pixel_clock = 162000000, 3371 .registers = vc4_hdmi_fields, 3372 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3373 3374 .init_resources = vc4_hdmi_init_resources, 3375 .csc_setup = vc4_hdmi_csc_setup, 3376 .reset = vc4_hdmi_reset, 3377 .set_timings = vc4_hdmi_set_timings, 3378 .phy_init = vc4_hdmi_phy_init, 3379 .phy_disable = vc4_hdmi_phy_disable, 3380 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3381 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3382 .channel_map = vc4_hdmi_channel_map, 3383 .supports_hdr = false, 3384 }; 3385 3386 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3387 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3388 .debugfs_name = "hdmi0_regs", 3389 .card_name = "vc4-hdmi-0", 3390 .max_pixel_clock = 600000000, 3391 .registers = vc5_hdmi_hdmi0_fields, 3392 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3393 .phy_lane_mapping = { 3394 PHY_LANE_0, 3395 PHY_LANE_1, 3396 PHY_LANE_2, 3397 PHY_LANE_CK, 3398 }, 3399 .unsupported_odd_h_timings = true, 3400 .external_irq_controller = true, 3401 3402 .init_resources = vc5_hdmi_init_resources, 3403 .csc_setup = vc5_hdmi_csc_setup, 3404 .reset = vc5_hdmi_reset, 3405 .set_timings = vc5_hdmi_set_timings, 3406 .phy_init = vc5_hdmi_phy_init, 3407 .phy_disable = vc5_hdmi_phy_disable, 3408 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3409 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3410 .channel_map = vc5_hdmi_channel_map, 3411 .supports_hdr = true, 3412 .hp_detect = vc5_hdmi_hp_detect, 3413 }; 3414 3415 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3416 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3417 .debugfs_name = "hdmi1_regs", 3418 .card_name = "vc4-hdmi-1", 3419 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3420 .registers = vc5_hdmi_hdmi1_fields, 3421 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3422 .phy_lane_mapping = { 3423 PHY_LANE_1, 3424 PHY_LANE_0, 3425 PHY_LANE_CK, 3426 PHY_LANE_2, 3427 }, 3428 .unsupported_odd_h_timings = true, 3429 .external_irq_controller = true, 3430 3431 .init_resources = vc5_hdmi_init_resources, 3432 .csc_setup = vc5_hdmi_csc_setup, 3433 .reset = vc5_hdmi_reset, 3434 .set_timings = vc5_hdmi_set_timings, 3435 .phy_init = vc5_hdmi_phy_init, 3436 .phy_disable = vc5_hdmi_phy_disable, 3437 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3438 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3439 .channel_map = vc5_hdmi_channel_map, 3440 .supports_hdr = true, 3441 .hp_detect = vc5_hdmi_hp_detect, 3442 }; 3443 3444 static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = { 3445 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3446 .debugfs_name = "hdmi0_regs", 3447 .card_name = "vc4-hdmi-0", 3448 .max_pixel_clock = 600000000, 3449 .registers = vc6_hdmi_hdmi0_fields, 3450 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi0_fields), 3451 .phy_lane_mapping = { 3452 PHY_LANE_0, 3453 PHY_LANE_1, 3454 PHY_LANE_2, 3455 PHY_LANE_CK, 3456 }, 3457 .unsupported_odd_h_timings = false, 3458 .external_irq_controller = true, 3459 3460 .init_resources = vc5_hdmi_init_resources, 3461 .csc_setup = vc5_hdmi_csc_setup, 3462 .reset = vc5_hdmi_reset, 3463 .set_timings = vc5_hdmi_set_timings, 3464 .phy_init = vc6_hdmi_phy_init, 3465 .phy_disable = vc6_hdmi_phy_disable, 3466 .channel_map = vc5_hdmi_channel_map, 3467 .supports_hdr = true, 3468 .hp_detect = vc5_hdmi_hp_detect, 3469 }; 3470 3471 static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = { 3472 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3473 .debugfs_name = "hdmi1_regs", 3474 .card_name = "vc4-hdmi-1", 3475 .max_pixel_clock = 600000000, 3476 .registers = vc6_hdmi_hdmi1_fields, 3477 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi1_fields), 3478 .phy_lane_mapping = { 3479 PHY_LANE_0, 3480 PHY_LANE_1, 3481 PHY_LANE_2, 3482 PHY_LANE_CK, 3483 }, 3484 .unsupported_odd_h_timings = false, 3485 .external_irq_controller = true, 3486 3487 .init_resources = vc5_hdmi_init_resources, 3488 .csc_setup = vc5_hdmi_csc_setup, 3489 .reset = vc5_hdmi_reset, 3490 .set_timings = vc5_hdmi_set_timings, 3491 .phy_init = vc6_hdmi_phy_init, 3492 .phy_disable = vc6_hdmi_phy_disable, 3493 .channel_map = vc5_hdmi_channel_map, 3494 .supports_hdr = true, 3495 .hp_detect = vc5_hdmi_hp_detect, 3496 }; 3497 3498 static const struct of_device_id vc4_hdmi_dt_match[] = { 3499 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3500 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3501 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3502 { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant }, 3503 { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant }, 3504 {} 3505 }; 3506 3507 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3508 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3509 vc4_hdmi_runtime_resume, 3510 NULL) 3511 }; 3512 3513 struct platform_driver vc4_hdmi_driver = { 3514 .probe = vc4_hdmi_dev_probe, 3515 .remove = vc4_hdmi_dev_remove, 3516 .driver = { 3517 .name = "vc4_hdmi", 3518 .of_match_table = vc4_hdmi_dt_match, 3519 .pm = &vc4_hdmi_pm_ops, 3520 }, 3521 }; 3522