1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_audio_helper.h> 35 #include <drm/display/drm_hdmi_cec_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_hdmi_state_helper.h> 38 #include <drm/display/drm_scdc_helper.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_drv.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/drm_simple_kms_helper.h> 45 #include <linux/clk.h> 46 #include <linux/component.h> 47 #include <linux/gpio/consumer.h> 48 #include <linux/i2c.h> 49 #include <linux/of.h> 50 #include <linux/of_address.h> 51 #include <linux/pm_runtime.h> 52 #include <linux/rational.h> 53 #include <linux/reset.h> 54 #include <sound/dmaengine_pcm.h> 55 #include <sound/hdmi-codec.h> 56 #include <sound/jack.h> 57 #include <sound/pcm_drm_eld.h> 58 #include <sound/pcm_params.h> 59 #include <sound/soc.h> 60 #include "media/cec.h" 61 #include "vc4_drv.h" 62 #include "vc4_hdmi.h" 63 #include "vc4_hdmi_regs.h" 64 #include "vc4_regs.h" 65 66 #define VC5_HDMI_HORZA_HFP_SHIFT 16 67 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 68 #define VC5_HDMI_HORZA_VPOS BIT(15) 69 #define VC5_HDMI_HORZA_HPOS BIT(14) 70 #define VC5_HDMI_HORZA_HAP_SHIFT 0 71 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 72 73 #define VC5_HDMI_HORZB_HBP_SHIFT 16 74 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 75 #define VC5_HDMI_HORZB_HSP_SHIFT 0 76 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 77 78 #define VC5_HDMI_VERTA_VSP_SHIFT 24 79 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 80 #define VC5_HDMI_VERTA_VFP_SHIFT 16 81 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 82 #define VC5_HDMI_VERTA_VAL_SHIFT 0 83 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 84 85 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 86 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 87 88 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 89 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 90 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 91 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 92 93 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 94 95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 96 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 97 98 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 99 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 100 101 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 102 103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 105 106 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0) 107 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0) 108 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4) 109 110 # define VC4_HD_M_SW_RST BIT(2) 111 # define VC4_HD_M_ENABLE BIT(0) 112 113 #define HSM_MIN_CLOCK_FREQ 120000000 114 #define CEC_CLOCK_FREQ 40000 115 116 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 117 118 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 119 { 120 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 121 122 lockdep_assert_held(&vc4_hdmi->mutex); 123 124 if (!display->is_hdmi) 125 return false; 126 127 if (!display->hdmi.scdc.supported || 128 !display->hdmi.scdc.scrambling.supported) 129 return false; 130 131 return true; 132 } 133 134 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 135 unsigned int bpc, 136 enum hdmi_colorspace fmt) 137 { 138 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt); 139 140 return clock > HDMI_14_MAX_TMDS_CLK; 141 } 142 143 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 144 { 145 struct drm_debugfs_entry *entry = m->private; 146 struct vc4_hdmi *vc4_hdmi = entry->file.data; 147 struct drm_device *drm = vc4_hdmi->connector.dev; 148 struct drm_printer p = drm_seq_file_printer(m); 149 int idx; 150 151 if (!drm_dev_enter(drm, &idx)) 152 return -ENODEV; 153 154 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 155 156 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 157 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 158 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 159 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 160 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 161 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 162 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 163 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 164 165 pm_runtime_put(&vc4_hdmi->pdev->dev); 166 167 drm_dev_exit(idx); 168 169 return 0; 170 } 171 172 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 173 { 174 struct drm_device *drm = vc4_hdmi->connector.dev; 175 unsigned long flags; 176 int idx; 177 178 /* 179 * We can be called by our bind callback, when the 180 * connector->dev pointer might not be initialised yet. 181 */ 182 if (drm && !drm_dev_enter(drm, &idx)) 183 return; 184 185 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 186 187 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 188 udelay(1); 189 HDMI_WRITE(HDMI_M_CTL, 0); 190 191 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 192 193 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 194 VC4_HDMI_SW_RESET_HDMI | 195 VC4_HDMI_SW_RESET_FORMAT_DETECT); 196 197 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 198 199 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 200 201 if (drm) 202 drm_dev_exit(idx); 203 } 204 205 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 206 { 207 struct drm_device *drm = vc4_hdmi->connector.dev; 208 unsigned long flags; 209 int idx; 210 211 /* 212 * We can be called by our bind callback, when the 213 * connector->dev pointer might not be initialised yet. 214 */ 215 if (drm && !drm_dev_enter(drm, &idx)) 216 return; 217 218 reset_control_reset(vc4_hdmi->reset); 219 220 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 221 222 HDMI_WRITE(HDMI_DVP_CTL, 0); 223 224 HDMI_WRITE(HDMI_CLOCK_STOP, 225 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 226 227 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 228 229 if (drm) 230 drm_dev_exit(idx); 231 } 232 233 #ifdef CONFIG_DRM_VC4_HDMI_CEC 234 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 235 { 236 struct drm_device *drm = vc4_hdmi->connector.dev; 237 unsigned long cec_rate; 238 unsigned long flags; 239 u16 clk_cnt; 240 u32 value; 241 int idx; 242 243 /* 244 * This function is called by our runtime_resume implementation 245 * and thus at bind time, when we haven't registered our 246 * connector yet and thus don't have a pointer to the DRM 247 * device. 248 */ 249 if (drm && !drm_dev_enter(drm, &idx)) 250 return; 251 252 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 253 254 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 255 256 value = HDMI_READ(HDMI_CEC_CNTRL_1); 257 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 258 259 /* 260 * Set the clock divider: the hsm_clock rate and this divider 261 * setting will give a 40 kHz CEC clock. 262 */ 263 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 264 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 265 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 266 267 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 268 269 if (drm) 270 drm_dev_exit(idx); 271 } 272 #else 273 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 274 #endif 275 276 static int vc4_hdmi_reset_link(struct drm_connector *connector, 277 struct drm_modeset_acquire_ctx *ctx) 278 { 279 struct drm_device *drm; 280 struct vc4_hdmi *vc4_hdmi; 281 struct drm_connector_state *conn_state; 282 struct drm_crtc_state *crtc_state; 283 struct drm_crtc *crtc; 284 bool scrambling_needed; 285 u8 config; 286 int ret; 287 288 if (!connector) 289 return 0; 290 291 drm = connector->dev; 292 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 293 if (ret) 294 return ret; 295 296 conn_state = connector->state; 297 crtc = conn_state->crtc; 298 if (!crtc) 299 return 0; 300 301 ret = drm_modeset_lock(&crtc->mutex, ctx); 302 if (ret) 303 return ret; 304 305 crtc_state = crtc->state; 306 if (!crtc_state->active) 307 return 0; 308 309 vc4_hdmi = connector_to_vc4_hdmi(connector); 310 mutex_lock(&vc4_hdmi->mutex); 311 312 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 313 mutex_unlock(&vc4_hdmi->mutex); 314 return 0; 315 } 316 317 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 318 vc4_hdmi->output_bpc, 319 vc4_hdmi->output_format); 320 if (!scrambling_needed) { 321 mutex_unlock(&vc4_hdmi->mutex); 322 return 0; 323 } 324 325 if (conn_state->commit && 326 !try_wait_for_completion(&conn_state->commit->hw_done)) { 327 mutex_unlock(&vc4_hdmi->mutex); 328 return 0; 329 } 330 331 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 332 if (ret < 0) { 333 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 334 mutex_unlock(&vc4_hdmi->mutex); 335 return 0; 336 } 337 338 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 339 mutex_unlock(&vc4_hdmi->mutex); 340 return 0; 341 } 342 343 mutex_unlock(&vc4_hdmi->mutex); 344 345 /* 346 * HDMI 2.0 says that one should not send scrambled data 347 * prior to configuring the sink scrambling, and that 348 * TMDS clock/data transmission should be suspended when 349 * changing the TMDS clock rate in the sink. So let's 350 * just do a full modeset here, even though some sinks 351 * would be perfectly happy if were to just reconfigure 352 * the SCDC settings on the fly. 353 */ 354 return drm_atomic_helper_reset_crtc(crtc, ctx); 355 } 356 357 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 358 struct drm_modeset_acquire_ctx *ctx, 359 enum drm_connector_status status) 360 { 361 struct drm_connector *connector = &vc4_hdmi->connector; 362 int ret; 363 364 /* 365 * NOTE: This function should really be called with vc4_hdmi->mutex 366 * held, but doing so results in reentrancy issues since 367 * cec_s_phys_addr() might call .adap_enable, which leads to that 368 * funtion being called with our mutex held. 369 * 370 * A similar situation occurs with vc4_hdmi_reset_link() that 371 * will call into our KMS hooks if the scrambling was enabled. 372 * 373 * Concurrency isn't an issue at the moment since we don't share 374 * any state with any of the other frameworks so we can ignore 375 * the lock for now. 376 */ 377 378 drm_atomic_helper_connector_hdmi_hotplug(connector, status); 379 380 if (status != connector_status_connected) 381 return; 382 383 for (;;) { 384 ret = vc4_hdmi_reset_link(connector, ctx); 385 if (ret == -EDEADLK) { 386 drm_modeset_backoff(ctx); 387 continue; 388 } 389 390 break; 391 } 392 } 393 394 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 395 struct drm_modeset_acquire_ctx *ctx, 396 bool force) 397 { 398 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 399 enum drm_connector_status status = connector_status_disconnected; 400 int ret; 401 402 /* 403 * NOTE: This function should really take vc4_hdmi->mutex, but 404 * doing so results in reentrancy issues since 405 * vc4_hdmi_handle_hotplug() can call into other functions that 406 * would take the mutex while it's held here. 407 * 408 * Concurrency isn't an issue at the moment since we don't share 409 * any state with any of the other frameworks so we can ignore 410 * the lock for now. 411 */ 412 413 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 414 if (ret) { 415 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n", 416 ret); 417 return connector_status_unknown; 418 } 419 420 if (vc4_hdmi->hpd_gpio) { 421 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 422 status = connector_status_connected; 423 } else { 424 if (vc4_hdmi->variant->hp_detect && 425 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 426 status = connector_status_connected; 427 } 428 429 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 430 pm_runtime_put(&vc4_hdmi->pdev->dev); 431 432 return status; 433 } 434 435 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 436 { 437 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 438 int ret = 0; 439 440 ret = drm_edid_connector_add_modes(connector); 441 442 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 443 struct drm_device *drm = connector->dev; 444 const struct drm_display_mode *mode; 445 446 list_for_each_entry(mode, &connector->probed_modes, head) { 447 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) { 448 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 449 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 450 } 451 } 452 } 453 454 return ret; 455 } 456 457 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 458 struct drm_atomic_state *state) 459 { 460 struct drm_connector_state *old_state = 461 drm_atomic_get_old_connector_state(state, connector); 462 struct drm_connector_state *new_state = 463 drm_atomic_get_new_connector_state(state, connector); 464 struct drm_crtc *crtc = new_state->crtc; 465 466 if (!crtc) 467 return 0; 468 469 if (old_state->tv.margins.left != new_state->tv.margins.left || 470 old_state->tv.margins.right != new_state->tv.margins.right || 471 old_state->tv.margins.top != new_state->tv.margins.top || 472 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 473 struct drm_crtc_state *crtc_state; 474 int ret; 475 476 crtc_state = drm_atomic_get_crtc_state(state, crtc); 477 if (IS_ERR(crtc_state)) 478 return PTR_ERR(crtc_state); 479 480 /* 481 * Strictly speaking, we should be calling 482 * drm_atomic_helper_check_planes() after our call to 483 * drm_atomic_add_affected_planes(). However, the 484 * connector atomic_check is called as part of 485 * drm_atomic_helper_check_modeset() that already 486 * happens before a call to 487 * drm_atomic_helper_check_planes() in 488 * drm_atomic_helper_check(). 489 */ 490 ret = drm_atomic_add_affected_planes(state, crtc); 491 if (ret) 492 return ret; 493 } 494 495 if (old_state->colorspace != new_state->colorspace) { 496 struct drm_crtc_state *crtc_state; 497 498 crtc_state = drm_atomic_get_crtc_state(state, crtc); 499 if (IS_ERR(crtc_state)) 500 return PTR_ERR(crtc_state); 501 502 crtc_state->mode_changed = true; 503 } 504 505 return drm_atomic_helper_connector_hdmi_check(connector, state); 506 } 507 508 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 509 { 510 drm_atomic_helper_connector_reset(connector); 511 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); 512 drm_atomic_helper_connector_tv_margins_reset(connector); 513 } 514 515 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 516 .force = drm_atomic_helper_connector_hdmi_force, 517 .fill_modes = drm_helper_probe_single_connector_modes, 518 .reset = vc4_hdmi_connector_reset, 519 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 520 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 521 }; 522 523 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 524 .detect_ctx = vc4_hdmi_connector_detect_ctx, 525 .get_modes = vc4_hdmi_connector_get_modes, 526 .atomic_check = vc4_hdmi_connector_atomic_check, 527 .mode_valid = drm_hdmi_connector_mode_valid, 528 }; 529 530 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs; 531 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs; 532 533 static int vc4_hdmi_connector_init(struct drm_device *dev, 534 struct vc4_hdmi *vc4_hdmi) 535 { 536 struct drm_connector *connector = &vc4_hdmi->connector; 537 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 538 unsigned int max_bpc = 8; 539 int ret; 540 541 if (vc4_hdmi->variant->supports_hdr) 542 max_bpc = 12; 543 544 ret = drmm_connector_hdmi_init(dev, connector, 545 "Broadcom", "Videocore", 546 &vc4_hdmi_connector_funcs, 547 &vc4_hdmi_hdmi_connector_funcs, 548 DRM_MODE_CONNECTOR_HDMIA, 549 vc4_hdmi->ddc, 550 BIT(HDMI_COLORSPACE_RGB) | 551 BIT(HDMI_COLORSPACE_YUV422) | 552 BIT(HDMI_COLORSPACE_YUV444), 553 max_bpc); 554 if (ret) 555 return ret; 556 557 ret = drm_connector_hdmi_audio_init(connector, dev->dev, 558 &vc4_hdmi_audio_funcs, 559 8, 0, false, -1); 560 if (ret) 561 return ret; 562 563 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 564 565 /* 566 * Some of the properties below require access to state, like bpc. 567 * Allocate some default initial connector state with our reset helper. 568 */ 569 if (connector->funcs->reset) 570 connector->funcs->reset(connector); 571 572 /* Create and attach TV margin props to this connector. */ 573 ret = drm_mode_create_tv_margin_properties(dev); 574 if (ret) 575 return ret; 576 577 ret = drm_mode_create_hdmi_colorspace_property(connector, 0); 578 if (ret) 579 return ret; 580 581 drm_connector_attach_colorspace_property(connector); 582 drm_connector_attach_tv_margin_properties(connector); 583 584 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 585 DRM_CONNECTOR_POLL_DISCONNECT); 586 587 connector->interlace_allowed = 1; 588 connector->doublescan_allowed = 0; 589 connector->stereo_allowed = 1; 590 591 ret = drm_connector_attach_broadcast_rgb_property(connector); 592 if (ret) 593 return ret; 594 595 drm_connector_attach_encoder(connector, encoder); 596 597 return 0; 598 } 599 600 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi, 601 enum hdmi_infoframe_type type, 602 bool poll) 603 { 604 struct drm_device *drm = vc4_hdmi->connector.dev; 605 u32 packet_id = type - 0x80; 606 unsigned long flags; 607 int ret = 0; 608 int idx; 609 610 if (!drm_dev_enter(drm, &idx)) 611 return -ENODEV; 612 613 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 614 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 615 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 616 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 617 618 if (poll) { 619 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 620 BIT(packet_id)), 100); 621 } 622 623 drm_dev_exit(idx); 624 return ret; 625 } 626 627 static int vc4_hdmi_write_infoframe(struct drm_connector *connector, 628 enum hdmi_infoframe_type type, 629 const u8 *infoframe, size_t len) 630 { 631 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 632 struct drm_device *drm = connector->dev; 633 u32 packet_id = type - 0x80; 634 const struct vc4_hdmi_register *ram_packet_start = 635 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 636 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 637 u32 packet_reg_next = ram_packet_start->offset + 638 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 639 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 640 ram_packet_start->reg); 641 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 642 unsigned long flags; 643 ssize_t i; 644 int ret; 645 int idx; 646 647 if (!drm_dev_enter(drm, &idx)) 648 return 0; 649 650 if (len > sizeof(buffer)) { 651 ret = -ENOMEM; 652 goto out; 653 } 654 655 memcpy(buffer, infoframe, len); 656 657 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 658 VC4_HDMI_RAM_PACKET_ENABLE), 659 "Packet RAM has to be on to store the packet."); 660 661 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true); 662 if (ret) { 663 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret); 664 goto out; 665 } 666 667 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 668 669 for (i = 0; i < len; i += 7) { 670 writel(buffer[i + 0] << 0 | 671 buffer[i + 1] << 8 | 672 buffer[i + 2] << 16, 673 base + packet_reg); 674 packet_reg += 4; 675 676 writel(buffer[i + 3] << 0 | 677 buffer[i + 4] << 8 | 678 buffer[i + 5] << 16 | 679 buffer[i + 6] << 24, 680 base + packet_reg); 681 packet_reg += 4; 682 } 683 684 /* 685 * clear remainder of packet ram as it's included in the 686 * infoframe and triggers a checksum error on hdmi analyser 687 */ 688 for (; packet_reg < packet_reg_next; packet_reg += 4) 689 writel(0, base + packet_reg); 690 691 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 692 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 693 694 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 695 696 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 697 BIT(packet_id)), 100); 698 if (ret) 699 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret); 700 701 out: 702 drm_dev_exit(idx); 703 return ret; 704 } 705 706 #define SCRAMBLING_POLLING_DELAY_MS 1000 707 708 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 709 { 710 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 711 struct drm_connector *connector = &vc4_hdmi->connector; 712 struct drm_device *drm = connector->dev; 713 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 714 unsigned long flags; 715 int idx; 716 717 lockdep_assert_held(&vc4_hdmi->mutex); 718 719 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 720 return; 721 722 if (!vc4_hdmi_mode_needs_scrambling(mode, 723 vc4_hdmi->output_bpc, 724 vc4_hdmi->output_format)) 725 return; 726 727 if (!drm_dev_enter(drm, &idx)) 728 return; 729 730 drm_scdc_set_high_tmds_clock_ratio(connector, true); 731 drm_scdc_set_scrambling(connector, true); 732 733 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 734 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 735 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 736 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 737 738 drm_dev_exit(idx); 739 740 vc4_hdmi->scdc_enabled = true; 741 742 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 743 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 744 } 745 746 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 747 { 748 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 749 struct drm_connector *connector = &vc4_hdmi->connector; 750 struct drm_device *drm = connector->dev; 751 unsigned long flags; 752 int idx; 753 754 lockdep_assert_held(&vc4_hdmi->mutex); 755 756 if (!vc4_hdmi->scdc_enabled) 757 return; 758 759 vc4_hdmi->scdc_enabled = false; 760 761 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 762 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 763 764 if (!drm_dev_enter(drm, &idx)) 765 return; 766 767 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 768 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 769 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 770 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 771 772 drm_scdc_set_scrambling(connector, false); 773 drm_scdc_set_high_tmds_clock_ratio(connector, false); 774 775 drm_dev_exit(idx); 776 } 777 778 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 779 { 780 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 781 struct vc4_hdmi, 782 scrambling_work); 783 struct drm_connector *connector = &vc4_hdmi->connector; 784 785 if (drm_scdc_get_scrambling_status(connector)) 786 return; 787 788 drm_scdc_set_high_tmds_clock_ratio(connector, true); 789 drm_scdc_set_scrambling(connector, true); 790 791 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 792 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 793 } 794 795 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 796 struct drm_atomic_state *state) 797 { 798 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 799 struct drm_device *drm = vc4_hdmi->connector.dev; 800 struct vc4_dev *vc4 = to_vc4_dev(drm); 801 unsigned long flags; 802 int idx; 803 804 mutex_lock(&vc4_hdmi->mutex); 805 806 vc4_hdmi->packet_ram_enabled = false; 807 808 if (!drm_dev_enter(drm, &idx)) 809 goto out; 810 811 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 812 813 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 814 815 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 816 817 if (vc4->gen >= VC4_GEN_6_C) 818 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 819 VC4_HD_VID_CTL_BLANKPIX); 820 821 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 822 823 mdelay(1); 824 825 /* 826 * TODO: This should work on BCM2712, but doesn't for some 827 * reason and result in a system lockup. 828 */ 829 if (vc4->gen < VC4_GEN_6_C) { 830 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 831 HDMI_WRITE(HDMI_VID_CTL, 832 HDMI_READ(HDMI_VID_CTL) & 833 ~VC4_HD_VID_CTL_ENABLE); 834 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 835 } 836 837 vc4_hdmi_disable_scrambling(encoder); 838 839 drm_dev_exit(idx); 840 841 out: 842 mutex_unlock(&vc4_hdmi->mutex); 843 } 844 845 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 846 struct drm_atomic_state *state) 847 { 848 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 849 struct drm_device *drm = vc4_hdmi->connector.dev; 850 unsigned long flags; 851 int idx; 852 853 mutex_lock(&vc4_hdmi->mutex); 854 855 if (!drm_dev_enter(drm, &idx)) 856 goto out; 857 858 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 859 HDMI_WRITE(HDMI_VID_CTL, 860 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 861 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 862 863 if (vc4_hdmi->variant->phy_disable) 864 vc4_hdmi->variant->phy_disable(vc4_hdmi); 865 866 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 867 clk_disable_unprepare(vc4_hdmi->pixel_clock); 868 869 pm_runtime_put(&vc4_hdmi->pdev->dev); 870 871 drm_dev_exit(idx); 872 873 out: 874 mutex_unlock(&vc4_hdmi->mutex); 875 } 876 877 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 878 struct drm_connector_state *state, 879 const struct drm_display_mode *mode) 880 { 881 struct drm_device *drm = vc4_hdmi->connector.dev; 882 unsigned long flags; 883 u32 csc_ctl; 884 int idx; 885 886 if (!drm_dev_enter(drm, &idx)) 887 return; 888 889 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 890 891 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 892 VC4_HD_CSC_CTL_ORDER); 893 894 if (state->hdmi.is_limited_range) { 895 /* CEA VICs other than #1 requre limited range RGB 896 * output unless overridden by an AVI infoframe. 897 * Apply a colorspace conversion to squash 0-255 down 898 * to 16-235. The matrix here is: 899 * 900 * [ 0 0 0.8594 16] 901 * [ 0 0.8594 0 16] 902 * [ 0.8594 0 0 16] 903 * [ 0 0 0 1] 904 */ 905 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 906 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 907 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 908 VC4_HD_CSC_CTL_MODE); 909 910 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 911 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 912 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 913 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 914 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 915 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 916 } 917 918 /* The RGB order applies even when CSC is disabled. */ 919 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 920 921 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 922 923 drm_dev_exit(idx); 924 } 925 926 /* 927 * Matrices for (internal) RGB to RGB output. 928 * 929 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 930 */ 931 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = { 932 { 933 /* 934 * Full range - unity 935 * 936 * [ 1 0 0 0] 937 * [ 0 1 0 0] 938 * [ 0 0 1 0] 939 */ 940 { 0x2000, 0x0000, 0x0000, 0x0000 }, 941 { 0x0000, 0x2000, 0x0000, 0x0000 }, 942 { 0x0000, 0x0000, 0x2000, 0x0000 }, 943 }, 944 { 945 /* 946 * Limited range 947 * 948 * CEA VICs other than #1 require limited range RGB 949 * output unless overridden by an AVI infoframe. Apply a 950 * colorspace conversion to squash 0-255 down to 16-235. 951 * The matrix here is: 952 * 953 * [ 0.8594 0 0 16] 954 * [ 0 0.8594 0 16] 955 * [ 0 0 0.8594 16] 956 */ 957 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 958 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 959 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 960 }, 961 }; 962 963 /* 964 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace 965 * 966 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 967 */ 968 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = { 969 { 970 /* 971 * Full Range 972 * 973 * [ 0.299000 0.587000 0.114000 0 ] 974 * [ -0.168736 -0.331264 0.500000 128 ] 975 * [ 0.500000 -0.418688 -0.081312 128 ] 976 */ 977 { 0x0991, 0x12c9, 0x03a6, 0x0000 }, 978 { 0xfa9b, 0xf567, 0x1000, 0x2000 }, 979 { 0x1000, 0xf29b, 0xfd67, 0x2000 }, 980 }, 981 { 982 /* Limited Range 983 * 984 * [ 0.255785 0.502160 0.097523 16 ] 985 * [ -0.147644 -0.289856 0.437500 128 ] 986 * [ 0.437500 -0.366352 -0.071148 128 ] 987 */ 988 { 0x082f, 0x1012, 0x031f, 0x0400 }, 989 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 990 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 991 }, 992 }; 993 994 /* 995 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace 996 * 997 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 998 */ 999 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = { 1000 { 1001 /* 1002 * Full Range 1003 * 1004 * [ 0.212600 0.715200 0.072200 0 ] 1005 * [ -0.114572 -0.385428 0.500000 128 ] 1006 * [ 0.500000 -0.454153 -0.045847 128 ] 1007 */ 1008 { 0x06ce, 0x16e3, 0x024f, 0x0000 }, 1009 { 0xfc56, 0xf3ac, 0x1000, 0x2000 }, 1010 { 0x1000, 0xf179, 0xfe89, 0x2000 }, 1011 }, 1012 { 1013 /* 1014 * Limited Range 1015 * 1016 * [ 0.181906 0.611804 0.061758 16 ] 1017 * [ -0.100268 -0.337232 0.437500 128 ] 1018 * [ 0.437500 -0.397386 -0.040114 128 ] 1019 */ 1020 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1021 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1022 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1023 }, 1024 }; 1025 1026 /* 1027 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace 1028 * 1029 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1030 */ 1031 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = { 1032 { 1033 /* 1034 * Full Range 1035 * 1036 * [ 0.262700 0.678000 0.059300 0 ] 1037 * [ -0.139630 -0.360370 0.500000 128 ] 1038 * [ 0.500000 -0.459786 -0.040214 128 ] 1039 */ 1040 { 0x0868, 0x15b2, 0x01e6, 0x0000 }, 1041 { 0xfb89, 0xf479, 0x1000, 0x2000 }, 1042 { 0x1000, 0xf14a, 0xfeb8, 0x2000 }, 1043 }, 1044 { 1045 /* Limited Range 1046 * 1047 * [ 0.224732 0.580008 0.050729 16 ] 1048 * [ -0.122176 -0.315324 0.437500 128 ] 1049 * [ 0.437500 -0.402312 -0.035188 128 ] 1050 */ 1051 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1052 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1053 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1054 }, 1055 }; 1056 1057 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1058 const u16 coeffs[3][4]) 1059 { 1060 lockdep_assert_held(&vc4_hdmi->hw_lock); 1061 1062 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1063 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1064 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1065 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1066 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1067 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1068 } 1069 1070 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi, 1071 const u16 coeffs[3][4]) 1072 { 1073 lockdep_assert_held(&vc4_hdmi->hw_lock); 1074 1075 /* YUV444 needs the CSC matrices using the channels in a different order */ 1076 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]); 1077 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]); 1078 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]); 1079 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]); 1080 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]); 1081 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]); 1082 } 1083 1084 static const u16 1085 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4] 1086 { 1087 switch (colorspace) { 1088 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC: 1089 case DRM_MODE_COLORIMETRY_XVYCC_601: 1090 case DRM_MODE_COLORIMETRY_SYCC_601: 1091 case DRM_MODE_COLORIMETRY_OPYCC_601: 1092 case DRM_MODE_COLORIMETRY_BT601_YCC: 1093 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited]; 1094 1095 default: 1096 case DRM_MODE_COLORIMETRY_NO_DATA: 1097 case DRM_MODE_COLORIMETRY_BT709_YCC: 1098 case DRM_MODE_COLORIMETRY_XVYCC_709: 1099 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED: 1100 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT: 1101 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited]; 1102 1103 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 1104 case DRM_MODE_COLORIMETRY_BT2020_YCC: 1105 case DRM_MODE_COLORIMETRY_BT2020_RGB: 1106 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 1107 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 1108 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited]; 1109 } 1110 } 1111 1112 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1113 struct drm_connector_state *state, 1114 const struct drm_display_mode *mode) 1115 { 1116 struct drm_device *drm = vc4_hdmi->connector.dev; 1117 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0; 1118 unsigned long flags; 1119 const u16 (*csc)[4]; 1120 u32 if_cfg = 0; 1121 u32 if_xbar = 0x543210; 1122 u32 csc_chan_ctl = 0; 1123 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1124 VC5_MT_CP_CSC_CTL_MODE); 1125 int idx; 1126 1127 if (!drm_dev_enter(drm, &idx)) 1128 return; 1129 1130 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1131 1132 switch (state->hdmi.output_format) { 1133 case HDMI_COLORSPACE_YUV444: 1134 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1135 1136 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc); 1137 break; 1138 1139 case HDMI_COLORSPACE_YUV422: 1140 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1141 1142 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1143 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1144 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1145 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1146 1147 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1148 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1149 1150 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1151 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1152 1153 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc); 1154 break; 1155 1156 case HDMI_COLORSPACE_RGB: 1157 if_xbar = 0x354021; 1158 1159 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]); 1160 break; 1161 1162 default: 1163 break; 1164 } 1165 1166 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1167 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1168 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1169 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1170 1171 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1172 1173 drm_dev_exit(idx); 1174 } 1175 1176 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1177 struct drm_connector_state *state, 1178 const struct drm_display_mode *mode) 1179 { 1180 struct drm_device *drm = vc4_hdmi->connector.dev; 1181 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1182 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1183 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1184 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1185 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1186 VC4_HDMI_VERTA_VSP) | 1187 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1188 VC4_HDMI_VERTA_VFP) | 1189 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1190 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1191 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1192 interlaced, 1193 VC4_HDMI_VERTB_VBP)); 1194 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1195 VC4_SET_FIELD(mode->crtc_vtotal - 1196 mode->crtc_vsync_end, 1197 VC4_HDMI_VERTB_VBP)); 1198 unsigned long flags; 1199 u32 reg; 1200 int idx; 1201 1202 if (!drm_dev_enter(drm, &idx)) 1203 return; 1204 1205 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1206 1207 HDMI_WRITE(HDMI_HORZA, 1208 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1209 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1210 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1211 VC4_HDMI_HORZA_HAP)); 1212 1213 HDMI_WRITE(HDMI_HORZB, 1214 VC4_SET_FIELD((mode->htotal - 1215 mode->hsync_end) * pixel_rep, 1216 VC4_HDMI_HORZB_HBP) | 1217 VC4_SET_FIELD((mode->hsync_end - 1218 mode->hsync_start) * pixel_rep, 1219 VC4_HDMI_HORZB_HSP) | 1220 VC4_SET_FIELD((mode->hsync_start - 1221 mode->hdisplay) * pixel_rep, 1222 VC4_HDMI_HORZB_HFP)); 1223 1224 HDMI_WRITE(HDMI_VERTA0, verta); 1225 HDMI_WRITE(HDMI_VERTA1, verta); 1226 1227 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1228 HDMI_WRITE(HDMI_VERTB1, vertb); 1229 1230 reg = HDMI_READ(HDMI_MISC_CONTROL); 1231 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1232 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1233 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1234 1235 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1236 1237 drm_dev_exit(idx); 1238 } 1239 1240 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1241 struct drm_connector_state *state, 1242 const struct drm_display_mode *mode) 1243 { 1244 struct drm_device *drm = vc4_hdmi->connector.dev; 1245 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1246 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1247 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1248 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1249 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1250 VC5_HDMI_VERTA_VSP) | 1251 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1252 VC5_HDMI_VERTA_VFP) | 1253 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1254 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1255 VC5_HDMI_VERTB_VSPO) | 1256 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1257 interlaced, 1258 VC4_HDMI_VERTB_VBP)); 1259 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1260 VC4_SET_FIELD(mode->crtc_vtotal - 1261 mode->crtc_vsync_end, 1262 VC4_HDMI_VERTB_VBP)); 1263 unsigned long flags; 1264 unsigned char gcp; 1265 u32 reg; 1266 int idx; 1267 1268 if (!drm_dev_enter(drm, &idx)) 1269 return; 1270 1271 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1272 1273 HDMI_WRITE(HDMI_HORZA, 1274 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1275 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1276 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1277 VC5_HDMI_HORZA_HAP) | 1278 VC4_SET_FIELD((mode->hsync_start - 1279 mode->hdisplay) * pixel_rep, 1280 VC5_HDMI_HORZA_HFP)); 1281 1282 HDMI_WRITE(HDMI_HORZB, 1283 VC4_SET_FIELD((mode->htotal - 1284 mode->hsync_end) * pixel_rep, 1285 VC5_HDMI_HORZB_HBP) | 1286 VC4_SET_FIELD((mode->hsync_end - 1287 mode->hsync_start) * pixel_rep, 1288 VC5_HDMI_HORZB_HSP)); 1289 1290 HDMI_WRITE(HDMI_VERTA0, verta); 1291 HDMI_WRITE(HDMI_VERTA1, verta); 1292 1293 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1294 HDMI_WRITE(HDMI_VERTB1, vertb); 1295 1296 switch (state->hdmi.output_bpc) { 1297 case 12: 1298 gcp = 6; 1299 break; 1300 case 10: 1301 gcp = 5; 1302 break; 1303 case 8: 1304 default: 1305 gcp = 0; 1306 break; 1307 } 1308 1309 /* 1310 * YCC422 is always 36-bit and not considered deep colour so 1311 * doesn't signal in GCP. 1312 */ 1313 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) { 1314 gcp = 0; 1315 } 1316 1317 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1318 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1319 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1320 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1321 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1322 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1323 1324 reg = HDMI_READ(HDMI_GCP_WORD_1); 1325 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1326 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1327 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK; 1328 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE; 1329 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1330 1331 reg = HDMI_READ(HDMI_GCP_CONFIG); 1332 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1333 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1334 1335 reg = HDMI_READ(HDMI_MISC_CONTROL); 1336 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1337 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1338 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1339 1340 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1341 1342 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1343 1344 drm_dev_exit(idx); 1345 } 1346 1347 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1348 { 1349 struct drm_device *drm = vc4_hdmi->connector.dev; 1350 unsigned long flags; 1351 u32 drift; 1352 int ret; 1353 int idx; 1354 1355 if (!drm_dev_enter(drm, &idx)) 1356 return; 1357 1358 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1359 1360 drift = HDMI_READ(HDMI_FIFO_CTL); 1361 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1362 1363 HDMI_WRITE(HDMI_FIFO_CTL, 1364 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1365 HDMI_WRITE(HDMI_FIFO_CTL, 1366 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1367 1368 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1369 1370 usleep_range(1000, 1100); 1371 1372 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1373 1374 HDMI_WRITE(HDMI_FIFO_CTL, 1375 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1376 HDMI_WRITE(HDMI_FIFO_CTL, 1377 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1378 1379 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1380 1381 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1382 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1383 WARN_ONCE(ret, "Timeout waiting for " 1384 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1385 1386 drm_dev_exit(idx); 1387 } 1388 1389 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1390 struct drm_atomic_state *state) 1391 { 1392 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1393 struct drm_device *drm = vc4_hdmi->connector.dev; 1394 struct drm_connector *connector = &vc4_hdmi->connector; 1395 struct drm_connector_state *conn_state = 1396 drm_atomic_get_new_connector_state(state, connector); 1397 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1398 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate; 1399 unsigned long bvb_rate, hsm_rate; 1400 unsigned long flags; 1401 int ret; 1402 int idx; 1403 1404 mutex_lock(&vc4_hdmi->mutex); 1405 1406 if (!drm_dev_enter(drm, &idx)) 1407 goto out; 1408 1409 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1410 if (ret < 0) { 1411 drm_err(drm, "Failed to retain power domain: %d\n", ret); 1412 goto err_dev_exit; 1413 } 1414 1415 /* 1416 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1417 * be faster than pixel clock, infinitesimally faster, tested in 1418 * simulation. Otherwise, exact value is unimportant for HDMI 1419 * operation." This conflicts with bcm2835's vc4 documentation, which 1420 * states HSM's clock has to be at least 108% of the pixel clock. 1421 * 1422 * Real life tests reveal that vc4's firmware statement holds up, and 1423 * users are able to use pixel clocks closer to HSM's, namely for 1424 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1425 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1426 * 162MHz. 1427 * 1428 * Additionally, the AXI clock needs to be at least 25% of 1429 * pixel clock, but HSM ends up being the limiting factor. 1430 */ 1431 hsm_rate = max_t(unsigned long, 1432 HSM_MIN_CLOCK_FREQ, 1433 div_u64(tmds_char_rate, 100) * 101); 1434 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1435 if (ret) { 1436 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret); 1437 goto err_put_runtime_pm; 1438 } 1439 1440 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1441 if (ret) { 1442 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret); 1443 goto err_put_runtime_pm; 1444 } 1445 1446 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1447 if (ret) { 1448 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret); 1449 goto err_put_runtime_pm; 1450 } 1451 1452 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1453 1454 if (tmds_char_rate > 297000000) 1455 bvb_rate = 300000000; 1456 else if (tmds_char_rate > 148500000) 1457 bvb_rate = 150000000; 1458 else 1459 bvb_rate = 75000000; 1460 1461 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1462 if (ret) { 1463 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret); 1464 goto err_disable_pixel_clock; 1465 } 1466 1467 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1468 if (ret) { 1469 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret); 1470 goto err_disable_pixel_clock; 1471 } 1472 1473 if (vc4_hdmi->variant->phy_init) 1474 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state); 1475 1476 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1477 1478 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1479 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1480 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1481 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1482 1483 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1484 1485 if (vc4_hdmi->variant->set_timings) 1486 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1487 1488 drm_dev_exit(idx); 1489 1490 mutex_unlock(&vc4_hdmi->mutex); 1491 1492 return; 1493 1494 err_disable_pixel_clock: 1495 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1496 err_put_runtime_pm: 1497 pm_runtime_put(&vc4_hdmi->pdev->dev); 1498 err_dev_exit: 1499 drm_dev_exit(idx); 1500 out: 1501 mutex_unlock(&vc4_hdmi->mutex); 1502 return; 1503 } 1504 1505 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1506 struct drm_atomic_state *state) 1507 { 1508 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1509 struct drm_device *drm = vc4_hdmi->connector.dev; 1510 struct drm_connector *connector = &vc4_hdmi->connector; 1511 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1512 struct drm_connector_state *conn_state = 1513 drm_atomic_get_new_connector_state(state, connector); 1514 unsigned long flags; 1515 int idx; 1516 1517 mutex_lock(&vc4_hdmi->mutex); 1518 1519 if (!drm_dev_enter(drm, &idx)) 1520 goto out; 1521 1522 if (vc4_hdmi->variant->csc_setup) 1523 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1524 1525 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1526 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1527 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1528 1529 drm_dev_exit(idx); 1530 1531 out: 1532 mutex_unlock(&vc4_hdmi->mutex); 1533 } 1534 1535 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1536 struct drm_atomic_state *state) 1537 { 1538 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1539 struct drm_connector *connector = &vc4_hdmi->connector; 1540 struct drm_device *drm = connector->dev; 1541 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1542 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1543 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1544 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1545 unsigned long flags; 1546 int ret; 1547 int idx; 1548 1549 mutex_lock(&vc4_hdmi->mutex); 1550 1551 if (!drm_dev_enter(drm, &idx)) 1552 goto out; 1553 1554 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1555 1556 HDMI_WRITE(HDMI_VID_CTL, 1557 (HDMI_READ(HDMI_VID_CTL) & 1558 ~(VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) | 1559 VC4_HD_VID_CTL_ENABLE | 1560 VC4_HD_VID_CTL_CLRRGB | 1561 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1562 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1563 VC4_HD_VID_CTL_BLANK_INSERT_EN | 1564 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1565 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1566 1567 HDMI_WRITE(HDMI_VID_CTL, 1568 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1569 1570 if (display->is_hdmi) { 1571 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1572 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1573 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1574 1575 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1576 1577 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1578 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1579 WARN_ONCE(ret, "Timeout waiting for " 1580 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1581 } else { 1582 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1583 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1584 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1585 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1586 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1587 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1588 1589 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1590 1591 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1592 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1593 WARN_ONCE(ret, "Timeout waiting for " 1594 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1595 } 1596 1597 if (display->is_hdmi) { 1598 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1599 1600 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1601 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1602 1603 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1604 VC4_HDMI_RAM_PACKET_ENABLE); 1605 1606 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1607 vc4_hdmi->packet_ram_enabled = true; 1608 1609 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 1610 } 1611 1612 vc4_hdmi_recenter_fifo(vc4_hdmi); 1613 vc4_hdmi_enable_scrambling(encoder); 1614 1615 drm_dev_exit(idx); 1616 1617 out: 1618 mutex_unlock(&vc4_hdmi->mutex); 1619 } 1620 1621 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1622 struct drm_crtc_state *crtc_state, 1623 struct drm_connector_state *conn_state) 1624 { 1625 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1626 1627 mutex_lock(&vc4_hdmi->mutex); 1628 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1629 &crtc_state->adjusted_mode); 1630 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc; 1631 vc4_hdmi->output_format = conn_state->hdmi.output_format; 1632 mutex_unlock(&vc4_hdmi->mutex); 1633 } 1634 1635 static enum drm_mode_status 1636 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector, 1637 const struct drm_display_mode *mode, 1638 unsigned long long clock) 1639 { 1640 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1641 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 1642 1643 if (clock > vc4_hdmi->variant->max_pixel_clock) 1644 return MODE_CLOCK_HIGH; 1645 1646 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 1647 return MODE_CLOCK_HIGH; 1648 1649 /* 4096x2160@60 is not reliable without overclocking core */ 1650 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 1651 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 1652 drm_mode_vrefresh(mode) >= 50) 1653 return MODE_CLOCK_HIGH; 1654 1655 return MODE_OK; 1656 } 1657 1658 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = { 1659 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid, 1660 .write_infoframe = vc4_hdmi_write_infoframe, 1661 }; 1662 1663 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1664 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1665 1666 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1667 struct drm_crtc_state *crtc_state, 1668 struct drm_connector_state *conn_state) 1669 { 1670 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1671 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1672 unsigned long long tmds_char_rate = mode->clock * 1000; 1673 unsigned long long tmds_bit_rate; 1674 1675 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1676 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1677 /* Only try to fixup DBLCLK modes to get 480i and 576i 1678 * working. 1679 * A generic solution for all modes with odd horizontal 1680 * timing values seems impossible based on trying to 1681 * solve it for 1366x768 monitors. 1682 */ 1683 if ((mode->hsync_start - mode->hdisplay) & 1) 1684 mode->hsync_start--; 1685 if ((mode->hsync_end - mode->hsync_start) & 1) 1686 mode->hsync_end--; 1687 } 1688 1689 /* Now check whether we still have odd values remaining */ 1690 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1691 (mode->hsync_end % 2) || (mode->htotal % 2)) 1692 return -EINVAL; 1693 } 1694 1695 /* 1696 * The 1440p@60 pixel rate is in the same range than the first 1697 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1698 * bandwidth). Slightly lower the frequency to bring it out of 1699 * the WiFi range. 1700 */ 1701 tmds_bit_rate = tmds_char_rate * 10; 1702 if (vc4_hdmi->disable_wifi_frequencies && 1703 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1704 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1705 mode->clock = 238560; 1706 tmds_char_rate = mode->clock * 1000; 1707 } 1708 1709 return 0; 1710 } 1711 1712 static enum drm_mode_status 1713 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1714 const struct drm_display_mode *mode) 1715 { 1716 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1717 1718 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1719 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1720 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1721 (mode->hsync_end % 2) || (mode->htotal % 2))) 1722 return MODE_H_ILLEGAL; 1723 1724 return MODE_OK; 1725 } 1726 1727 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1728 .atomic_check = vc4_hdmi_encoder_atomic_check, 1729 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1730 .mode_valid = vc4_hdmi_encoder_mode_valid, 1731 }; 1732 1733 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 1734 { 1735 struct drm_device *drm = encoder->dev; 1736 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1737 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1738 1739 drm_debugfs_add_file(drm, variant->debugfs_name, 1740 vc4_hdmi_debugfs_regs, vc4_hdmi); 1741 1742 return 0; 1743 } 1744 1745 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 1746 .late_register = vc4_hdmi_late_register, 1747 }; 1748 1749 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1750 { 1751 int i; 1752 u32 channel_map = 0; 1753 1754 for (i = 0; i < 8; i++) { 1755 if (channel_mask & BIT(i)) 1756 channel_map |= i << (3 * i); 1757 } 1758 return channel_map; 1759 } 1760 1761 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1762 { 1763 int i; 1764 u32 channel_map = 0; 1765 1766 for (i = 0; i < 8; i++) { 1767 if (channel_mask & BIT(i)) 1768 channel_map |= i << (4 * i); 1769 } 1770 return channel_map; 1771 } 1772 1773 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1774 { 1775 struct drm_device *drm = vc4_hdmi->connector.dev; 1776 unsigned long flags; 1777 u32 hotplug; 1778 int idx; 1779 1780 if (!drm_dev_enter(drm, &idx)) 1781 return false; 1782 1783 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1784 hotplug = HDMI_READ(HDMI_HOTPLUG); 1785 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1786 1787 drm_dev_exit(idx); 1788 1789 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1790 } 1791 1792 /* HDMI audio codec callbacks */ 1793 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1794 unsigned int samplerate) 1795 { 1796 struct drm_device *drm = vc4_hdmi->connector.dev; 1797 u32 hsm_clock; 1798 unsigned long flags; 1799 unsigned long n, m; 1800 int idx; 1801 1802 if (!drm_dev_enter(drm, &idx)) 1803 return; 1804 1805 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1806 rational_best_approximation(hsm_clock, samplerate, 1807 VC4_HD_MAI_SMP_N_MASK >> 1808 VC4_HD_MAI_SMP_N_SHIFT, 1809 (VC4_HD_MAI_SMP_M_MASK >> 1810 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1811 &n, &m); 1812 1813 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1814 HDMI_WRITE(HDMI_MAI_SMP, 1815 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1816 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1817 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1818 1819 drm_dev_exit(idx); 1820 } 1821 1822 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1823 { 1824 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1825 u32 n, cts; 1826 u64 tmp; 1827 1828 lockdep_assert_held(&vc4_hdmi->mutex); 1829 lockdep_assert_held(&vc4_hdmi->hw_lock); 1830 1831 n = 128 * samplerate / 1000; 1832 tmp = (u64)(mode->clock * 1000) * n; 1833 do_div(tmp, 128 * samplerate); 1834 cts = tmp; 1835 1836 HDMI_WRITE(HDMI_CRP_CFG, 1837 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1838 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1839 1840 /* 1841 * We could get slightly more accurate clocks in some cases by 1842 * providing a CTS_1 value. The two CTS values are alternated 1843 * between based on the period fields 1844 */ 1845 HDMI_WRITE(HDMI_CTS_0, cts); 1846 HDMI_WRITE(HDMI_CTS_1, cts); 1847 } 1848 1849 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1850 { 1851 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1852 1853 return snd_soc_card_get_drvdata(card); 1854 } 1855 1856 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1857 { 1858 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1859 1860 lockdep_assert_held(&vc4_hdmi->mutex); 1861 1862 /* 1863 * If the encoder is currently in DVI mode, treat the codec DAI 1864 * as missing. 1865 */ 1866 if (!display->is_hdmi) 1867 return false; 1868 1869 return true; 1870 } 1871 1872 static int vc4_hdmi_audio_startup(struct drm_connector *connector) 1873 { 1874 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1875 struct drm_device *drm = vc4_hdmi->connector.dev; 1876 unsigned long flags; 1877 int ret = 0; 1878 int idx; 1879 1880 mutex_lock(&vc4_hdmi->mutex); 1881 1882 if (!drm_dev_enter(drm, &idx)) { 1883 ret = -ENODEV; 1884 goto out; 1885 } 1886 1887 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1888 ret = -ENOTSUPP; 1889 goto out_dev_exit; 1890 } 1891 1892 vc4_hdmi->audio.streaming = true; 1893 1894 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1895 HDMI_WRITE(HDMI_MAI_CTL, 1896 VC4_HD_MAI_CTL_RESET | 1897 VC4_HD_MAI_CTL_FLUSH | 1898 VC4_HD_MAI_CTL_DLATE | 1899 VC4_HD_MAI_CTL_ERRORE | 1900 VC4_HD_MAI_CTL_ERRORF); 1901 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1902 1903 if (vc4_hdmi->variant->phy_rng_enable) 1904 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1905 1906 out_dev_exit: 1907 drm_dev_exit(idx); 1908 out: 1909 mutex_unlock(&vc4_hdmi->mutex); 1910 1911 return ret; 1912 } 1913 1914 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1915 { 1916 struct device *dev = &vc4_hdmi->pdev->dev; 1917 unsigned long flags; 1918 int ret; 1919 1920 lockdep_assert_held(&vc4_hdmi->mutex); 1921 1922 vc4_hdmi->audio.streaming = false; 1923 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false); 1924 if (ret) 1925 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1926 1927 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1928 1929 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1930 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1931 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1932 1933 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1934 } 1935 1936 static void vc4_hdmi_audio_shutdown(struct drm_connector *connector) 1937 { 1938 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1939 struct drm_device *drm = vc4_hdmi->connector.dev; 1940 unsigned long flags; 1941 int idx; 1942 1943 mutex_lock(&vc4_hdmi->mutex); 1944 1945 if (!drm_dev_enter(drm, &idx)) 1946 goto out; 1947 1948 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1949 1950 HDMI_WRITE(HDMI_MAI_CTL, 1951 VC4_HD_MAI_CTL_DLATE | 1952 VC4_HD_MAI_CTL_ERRORE | 1953 VC4_HD_MAI_CTL_ERRORF); 1954 1955 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1956 1957 if (vc4_hdmi->variant->phy_rng_disable) 1958 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1959 1960 vc4_hdmi->audio.streaming = false; 1961 vc4_hdmi_audio_reset(vc4_hdmi); 1962 1963 drm_dev_exit(idx); 1964 1965 out: 1966 mutex_unlock(&vc4_hdmi->mutex); 1967 } 1968 1969 static int sample_rate_to_mai_fmt(int samplerate) 1970 { 1971 switch (samplerate) { 1972 case 8000: 1973 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1974 case 11025: 1975 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1976 case 12000: 1977 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1978 case 16000: 1979 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1980 case 22050: 1981 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1982 case 24000: 1983 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1984 case 32000: 1985 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1986 case 44100: 1987 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1988 case 48000: 1989 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1990 case 64000: 1991 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1992 case 88200: 1993 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1994 case 96000: 1995 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1996 case 128000: 1997 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 1998 case 176400: 1999 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2000 case 192000: 2001 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2002 default: 2003 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2004 } 2005 } 2006 2007 /* HDMI audio codec callbacks */ 2008 static int vc4_hdmi_audio_prepare(struct drm_connector *connector, 2009 struct hdmi_codec_daifmt *daifmt, 2010 struct hdmi_codec_params *params) 2011 { 2012 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2013 struct drm_device *drm = vc4_hdmi->connector.dev; 2014 struct vc4_dev *vc4 = to_vc4_dev(drm); 2015 unsigned int sample_rate = params->sample_rate; 2016 unsigned int channels = params->channels; 2017 unsigned long flags; 2018 u32 audio_packet_config, channel_mask; 2019 u32 channel_map; 2020 u32 mai_audio_format; 2021 u32 mai_sample_rate; 2022 int ret = 0; 2023 int idx; 2024 2025 dev_dbg(&vc4_hdmi->pdev->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2026 sample_rate, params->sample_width, channels); 2027 2028 mutex_lock(&vc4_hdmi->mutex); 2029 2030 if (!drm_dev_enter(drm, &idx)) { 2031 ret = -ENODEV; 2032 goto out; 2033 } 2034 2035 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2036 ret = -EINVAL; 2037 goto out_dev_exit; 2038 } 2039 2040 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2041 2042 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2043 HDMI_WRITE(HDMI_MAI_CTL, 2044 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2045 VC4_HD_MAI_CTL_WHOLSMP | 2046 VC4_HD_MAI_CTL_CHALIGN | 2047 VC4_HD_MAI_CTL_ENABLE); 2048 2049 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2050 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2051 params->channels == 8) 2052 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2053 else 2054 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2055 HDMI_WRITE(HDMI_MAI_FMT, 2056 VC4_SET_FIELD(mai_sample_rate, 2057 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2058 VC4_SET_FIELD(mai_audio_format, 2059 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2060 2061 /* The B frame identifier should match the value used by alsa-lib (8) */ 2062 audio_packet_config = 2063 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2064 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2065 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2066 2067 channel_mask = GENMASK(channels - 1, 0); 2068 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2069 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2070 2071 /* Set the MAI threshold */ 2072 switch (vc4->gen) { 2073 case VC4_GEN_6_D: 2074 HDMI_WRITE(HDMI_MAI_THR, 2075 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) | 2076 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) | 2077 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) | 2078 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW)); 2079 break; 2080 case VC4_GEN_6_C: 2081 case VC4_GEN_5: 2082 HDMI_WRITE(HDMI_MAI_THR, 2083 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 2084 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 2085 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) | 2086 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW)); 2087 break; 2088 case VC4_GEN_4: 2089 HDMI_WRITE(HDMI_MAI_THR, 2090 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) | 2091 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) | 2092 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) | 2093 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW)); 2094 break; 2095 default: 2096 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen); 2097 break; 2098 } 2099 2100 HDMI_WRITE(HDMI_MAI_CONFIG, 2101 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2102 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2103 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2104 2105 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2106 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2107 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2108 2109 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2110 2111 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2112 2113 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, 2114 ¶ms->cea); 2115 if (ret) 2116 goto out_dev_exit; 2117 2118 out_dev_exit: 2119 drm_dev_exit(idx); 2120 out: 2121 mutex_unlock(&vc4_hdmi->mutex); 2122 2123 return ret; 2124 } 2125 2126 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2127 .name = "vc4-hdmi-cpu-dai-component", 2128 .legacy_dai_naming = 1, 2129 }; 2130 2131 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2132 { 2133 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2134 2135 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2136 2137 return 0; 2138 } 2139 2140 static const struct snd_soc_dai_ops vc4_snd_dai_ops = { 2141 .probe = vc4_hdmi_audio_cpu_dai_probe, 2142 }; 2143 2144 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2145 .name = "vc4-hdmi-cpu-dai", 2146 .ops = &vc4_snd_dai_ops, 2147 .playback = { 2148 .stream_name = "Playback", 2149 .channels_min = 1, 2150 .channels_max = 8, 2151 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2152 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2153 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2154 SNDRV_PCM_RATE_192000, 2155 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2156 }, 2157 }; 2158 2159 static const struct snd_dmaengine_pcm_config pcm_conf = { 2160 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2161 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2162 }; 2163 2164 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs = { 2165 .startup = vc4_hdmi_audio_startup, 2166 .prepare = vc4_hdmi_audio_prepare, 2167 .shutdown = vc4_hdmi_audio_shutdown, 2168 }; 2169 2170 static int vc4_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd) 2171 { 2172 struct vc4_hdmi *vc4_hdmi = snd_soc_card_get_drvdata(rtd->card); 2173 struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component; 2174 int ret; 2175 2176 ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT, 2177 &vc4_hdmi->hdmi_jack); 2178 if (ret) { 2179 dev_err(rtd->dev, "HDMI Jack creation failed: %d\n", ret); 2180 return ret; 2181 } 2182 2183 return snd_soc_component_set_jack(component, &vc4_hdmi->hdmi_jack, NULL); 2184 } 2185 2186 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2187 { 2188 const struct vc4_hdmi_register *mai_data = 2189 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2190 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2191 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2192 struct device *dev = &vc4_hdmi->pdev->dev; 2193 const __be32 *addr; 2194 int index, len; 2195 int ret; 2196 2197 /* 2198 * ASoC makes it a bit hard to retrieve a pointer to the 2199 * vc4_hdmi structure. Registering the card will overwrite our 2200 * device drvdata with a pointer to the snd_soc_card structure, 2201 * which can then be used to retrieve whatever drvdata we want 2202 * to associate. 2203 * 2204 * However, that doesn't fly in the case where we wouldn't 2205 * register an ASoC card (because of an old DT that is missing 2206 * the dmas properties for example), then the card isn't 2207 * registered and the device drvdata wouldn't be set. 2208 * 2209 * We can deal with both cases by making sure a snd_soc_card 2210 * pointer and a vc4_hdmi structure are pointing to the same 2211 * memory address, so we can treat them indistinctly without any 2212 * issue. 2213 */ 2214 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2215 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2216 2217 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2218 dev_warn(dev, 2219 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2220 return 0; 2221 } 2222 2223 if (mai_data->reg != VC4_HD) { 2224 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2225 return -EINVAL; 2226 } 2227 2228 /* 2229 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2230 * the bus address specified in the DT, because the physical address 2231 * (the one returned by platform_get_resource()) is not appropriate 2232 * for DMA transfers. 2233 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2234 */ 2235 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2236 /* Before BCM2711, we don't have a named register range */ 2237 if (index < 0) 2238 index = 1; 2239 2240 addr = of_get_address(dev->of_node, index, NULL, NULL); 2241 if (!addr) 2242 return -EINVAL; 2243 2244 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2245 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2246 vc4_hdmi->audio.dma_data.maxburst = 2; 2247 2248 /* 2249 * NOTE: Strictly speaking, we should probably use a DRM-managed 2250 * registration there to avoid removing all the audio components 2251 * by the time the driver doesn't have any user anymore. 2252 * 2253 * However, the ASoC core uses a number of devm_kzalloc calls 2254 * when registering, even when using non-device-managed 2255 * functions (such as in snd_soc_register_component()). 2256 * 2257 * If we call snd_soc_unregister_component() in a DRM-managed 2258 * action, the device-managed actions have already been executed 2259 * and thus we would access memory that has been freed. 2260 * 2261 * Using device-managed hooks here probably leaves us open to a 2262 * bunch of issues if userspace still has a handle on the ALSA 2263 * device when the device is removed. However, this is mitigated 2264 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2265 * path to prevent the access to the device resources if it 2266 * isn't there anymore. 2267 * 2268 * Then, the vc4_hdmi structure is DRM-managed and thus only 2269 * freed whenever the last user has closed the DRM device file. 2270 * It should thus outlive ALSA in most situations. 2271 */ 2272 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2273 if (ret) { 2274 dev_err(dev, "Could not register PCM component: %d\n", ret); 2275 return ret; 2276 } 2277 2278 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2279 &vc4_hdmi_audio_cpu_dai_drv, 1); 2280 if (ret) { 2281 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2282 return ret; 2283 } 2284 2285 ret = drm_connector_hdmi_audio_init(&vc4_hdmi->connector, dev, 2286 &vc4_hdmi_audio_funcs, 8, 0, false, 2287 -1); 2288 if (ret) 2289 return ret; 2290 2291 dai_link->cpus = &vc4_hdmi->audio.cpu; 2292 dai_link->codecs = &vc4_hdmi->audio.codec; 2293 dai_link->platforms = &vc4_hdmi->audio.platform; 2294 2295 dai_link->num_cpus = 1; 2296 dai_link->num_codecs = 1; 2297 dai_link->num_platforms = 1; 2298 2299 dai_link->name = "MAI"; 2300 dai_link->stream_name = "MAI PCM"; 2301 dai_link->codecs->dai_name = "i2s-hifi"; 2302 dai_link->cpus->dai_name = dev_name(dev); 2303 dai_link->codecs->name = dev_name(&vc4_hdmi->connector.hdmi_audio.codec_pdev->dev); 2304 dai_link->platforms->name = dev_name(dev); 2305 dai_link->init = vc4_hdmi_codec_init; 2306 2307 card->dai_link = dai_link; 2308 card->num_links = 1; 2309 card->name = vc4_hdmi->variant->card_name; 2310 card->driver_name = "vc4-hdmi"; 2311 card->dev = dev; 2312 card->owner = THIS_MODULE; 2313 2314 /* 2315 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2316 * stores a pointer to the snd card object in dev->driver_data. This 2317 * means we cannot use it for something else. The hdmi back-pointer is 2318 * now stored in card->drvdata and should be retrieved with 2319 * snd_soc_card_get_drvdata() if needed. 2320 */ 2321 snd_soc_card_set_drvdata(card, vc4_hdmi); 2322 ret = devm_snd_soc_register_card(dev, card); 2323 if (ret) 2324 dev_err_probe(dev, ret, "Could not register sound card\n"); 2325 2326 return ret; 2327 2328 } 2329 2330 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2331 { 2332 struct vc4_hdmi *vc4_hdmi = priv; 2333 struct drm_connector *connector = &vc4_hdmi->connector; 2334 struct drm_device *dev = connector->dev; 2335 2336 if (dev && dev->registered) 2337 drm_connector_helper_hpd_irq_event(connector); 2338 2339 return IRQ_HANDLED; 2340 } 2341 2342 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2343 { 2344 struct drm_connector *connector = &vc4_hdmi->connector; 2345 struct platform_device *pdev = vc4_hdmi->pdev; 2346 int ret; 2347 2348 if (vc4_hdmi->variant->external_irq_controller) { 2349 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2350 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2351 2352 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2353 NULL, 2354 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2355 "vc4 hdmi hpd connected", vc4_hdmi); 2356 if (ret) 2357 return ret; 2358 2359 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2360 NULL, 2361 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2362 "vc4 hdmi hpd disconnected", vc4_hdmi); 2363 if (ret) 2364 return ret; 2365 2366 connector->polled = DRM_CONNECTOR_POLL_HPD; 2367 } 2368 2369 return 0; 2370 } 2371 2372 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2373 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2374 { 2375 struct vc4_hdmi *vc4_hdmi = priv; 2376 2377 if (vc4_hdmi->cec_rx_msg.len) 2378 drm_connector_hdmi_cec_received_msg(&vc4_hdmi->connector, 2379 &vc4_hdmi->cec_rx_msg); 2380 2381 return IRQ_HANDLED; 2382 } 2383 2384 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2385 { 2386 struct vc4_hdmi *vc4_hdmi = priv; 2387 2388 if (vc4_hdmi->cec_tx_ok) { 2389 drm_connector_hdmi_cec_transmit_done(&vc4_hdmi->connector, 2390 CEC_TX_STATUS_OK, 2391 0, 0, 0, 0); 2392 } else { 2393 /* 2394 * This CEC implementation makes 1 retry, so if we 2395 * get a NACK, then that means it made 2 attempts. 2396 */ 2397 drm_connector_hdmi_cec_transmit_done(&vc4_hdmi->connector, 2398 CEC_TX_STATUS_NACK, 2399 0, 2, 0, 0); 2400 } 2401 return IRQ_HANDLED; 2402 } 2403 2404 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2405 { 2406 struct vc4_hdmi *vc4_hdmi = priv; 2407 irqreturn_t ret; 2408 2409 if (vc4_hdmi->cec_irq_was_rx) 2410 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2411 else 2412 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2413 2414 return ret; 2415 } 2416 2417 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2418 { 2419 struct drm_device *dev = vc4_hdmi->connector.dev; 2420 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2421 unsigned int i; 2422 2423 lockdep_assert_held(&vc4_hdmi->hw_lock); 2424 2425 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2426 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2427 2428 if (msg->len > 16) { 2429 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2430 return; 2431 } 2432 2433 for (i = 0; i < msg->len; i += 4) { 2434 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2435 2436 msg->msg[i] = val & 0xff; 2437 msg->msg[i + 1] = (val >> 8) & 0xff; 2438 msg->msg[i + 2] = (val >> 16) & 0xff; 2439 msg->msg[i + 3] = (val >> 24) & 0xff; 2440 } 2441 } 2442 2443 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2444 { 2445 u32 cntrl1; 2446 2447 /* 2448 * We don't need to protect the register access using 2449 * drm_dev_enter() there because the interrupt handler lifetime 2450 * is tied to the device itself, and not to the DRM device. 2451 * 2452 * So when the device will be gone, one of the first thing we 2453 * will be doing will be to unregister the interrupt handler, 2454 * and then unregister the DRM device. drm_dev_enter() would 2455 * thus always succeed if we are here. 2456 */ 2457 2458 lockdep_assert_held(&vc4_hdmi->hw_lock); 2459 2460 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2461 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2462 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2463 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2464 2465 return IRQ_WAKE_THREAD; 2466 } 2467 2468 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2469 { 2470 struct vc4_hdmi *vc4_hdmi = priv; 2471 irqreturn_t ret; 2472 2473 spin_lock(&vc4_hdmi->hw_lock); 2474 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2475 spin_unlock(&vc4_hdmi->hw_lock); 2476 2477 return ret; 2478 } 2479 2480 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2481 { 2482 u32 cntrl1; 2483 2484 lockdep_assert_held(&vc4_hdmi->hw_lock); 2485 2486 /* 2487 * We don't need to protect the register access using 2488 * drm_dev_enter() there because the interrupt handler lifetime 2489 * is tied to the device itself, and not to the DRM device. 2490 * 2491 * So when the device will be gone, one of the first thing we 2492 * will be doing will be to unregister the interrupt handler, 2493 * and then unregister the DRM device. drm_dev_enter() would 2494 * thus always succeed if we are here. 2495 */ 2496 2497 vc4_hdmi->cec_rx_msg.len = 0; 2498 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2499 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2500 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2501 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2502 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2503 2504 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2505 2506 return IRQ_WAKE_THREAD; 2507 } 2508 2509 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2510 { 2511 struct vc4_hdmi *vc4_hdmi = priv; 2512 irqreturn_t ret; 2513 2514 spin_lock(&vc4_hdmi->hw_lock); 2515 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2516 spin_unlock(&vc4_hdmi->hw_lock); 2517 2518 return ret; 2519 } 2520 2521 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2522 { 2523 struct vc4_hdmi *vc4_hdmi = priv; 2524 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2525 irqreturn_t ret; 2526 u32 cntrl5; 2527 2528 /* 2529 * We don't need to protect the register access using 2530 * drm_dev_enter() there because the interrupt handler lifetime 2531 * is tied to the device itself, and not to the DRM device. 2532 * 2533 * So when the device will be gone, one of the first thing we 2534 * will be doing will be to unregister the interrupt handler, 2535 * and then unregister the DRM device. drm_dev_enter() would 2536 * thus always succeed if we are here. 2537 */ 2538 2539 if (!(stat & VC4_HDMI_CPU_CEC)) 2540 return IRQ_NONE; 2541 2542 spin_lock(&vc4_hdmi->hw_lock); 2543 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2544 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2545 if (vc4_hdmi->cec_irq_was_rx) 2546 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2547 else 2548 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2549 2550 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2551 spin_unlock(&vc4_hdmi->hw_lock); 2552 2553 return ret; 2554 } 2555 2556 static int vc4_hdmi_cec_enable(struct drm_connector *connector) 2557 { 2558 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2559 struct drm_device *drm = vc4_hdmi->connector.dev; 2560 /* clock period in microseconds */ 2561 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2562 unsigned long flags; 2563 u32 val; 2564 int ret; 2565 int idx; 2566 2567 if (!drm_dev_enter(drm, &idx)) 2568 /* 2569 * We can't return an error code, because the CEC 2570 * framework will emit WARN_ON messages at unbind 2571 * otherwise. 2572 */ 2573 return 0; 2574 2575 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2576 if (ret) { 2577 drm_dev_exit(idx); 2578 return ret; 2579 } 2580 2581 mutex_lock(&vc4_hdmi->mutex); 2582 2583 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2584 2585 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2586 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2587 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2588 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2589 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2590 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2591 2592 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2593 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2594 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2595 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2596 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2597 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2598 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2599 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2600 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2601 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2602 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2603 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2604 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2605 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2606 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2607 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2608 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2609 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2610 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2611 2612 if (!vc4_hdmi->variant->external_irq_controller) 2613 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2614 2615 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2616 2617 mutex_unlock(&vc4_hdmi->mutex); 2618 drm_dev_exit(idx); 2619 2620 return 0; 2621 } 2622 2623 static int vc4_hdmi_cec_disable(struct drm_connector *connector) 2624 { 2625 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2626 struct drm_device *drm = vc4_hdmi->connector.dev; 2627 unsigned long flags; 2628 int idx; 2629 2630 if (!drm_dev_enter(drm, &idx)) 2631 /* 2632 * We can't return an error code, because the CEC 2633 * framework will emit WARN_ON messages at unbind 2634 * otherwise. 2635 */ 2636 return 0; 2637 2638 mutex_lock(&vc4_hdmi->mutex); 2639 2640 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2641 2642 if (!vc4_hdmi->variant->external_irq_controller) 2643 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2644 2645 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2646 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2647 2648 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2649 2650 mutex_unlock(&vc4_hdmi->mutex); 2651 2652 pm_runtime_put(&vc4_hdmi->pdev->dev); 2653 2654 drm_dev_exit(idx); 2655 2656 return 0; 2657 } 2658 2659 static int vc4_hdmi_cec_adap_enable(struct drm_connector *connector, bool enable) 2660 { 2661 if (enable) 2662 return vc4_hdmi_cec_enable(connector); 2663 else 2664 return vc4_hdmi_cec_disable(connector); 2665 } 2666 2667 static int vc4_hdmi_cec_adap_log_addr(struct drm_connector *connector, u8 log_addr) 2668 { 2669 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2670 struct drm_device *drm = vc4_hdmi->connector.dev; 2671 unsigned long flags; 2672 int idx; 2673 2674 if (!drm_dev_enter(drm, &idx)) 2675 /* 2676 * We can't return an error code, because the CEC 2677 * framework will emit WARN_ON messages at unbind 2678 * otherwise. 2679 */ 2680 return 0; 2681 2682 mutex_lock(&vc4_hdmi->mutex); 2683 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2684 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2685 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2686 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2687 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2688 mutex_unlock(&vc4_hdmi->mutex); 2689 2690 drm_dev_exit(idx); 2691 2692 return 0; 2693 } 2694 2695 static int vc4_hdmi_cec_adap_transmit(struct drm_connector *connector, u8 attempts, 2696 u32 signal_free_time, struct cec_msg *msg) 2697 { 2698 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2699 struct drm_device *dev = vc4_hdmi->connector.dev; 2700 unsigned long flags; 2701 u32 val; 2702 unsigned int i; 2703 int idx; 2704 2705 if (!drm_dev_enter(dev, &idx)) 2706 return -ENODEV; 2707 2708 if (msg->len > 16) { 2709 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2710 drm_dev_exit(idx); 2711 return -ENOMEM; 2712 } 2713 2714 mutex_lock(&vc4_hdmi->mutex); 2715 2716 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2717 2718 for (i = 0; i < msg->len; i += 4) 2719 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2720 (msg->msg[i]) | 2721 (msg->msg[i + 1] << 8) | 2722 (msg->msg[i + 2] << 16) | 2723 (msg->msg[i + 3] << 24)); 2724 2725 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2726 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2727 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2728 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2729 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2730 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2731 2732 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2733 2734 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2735 mutex_unlock(&vc4_hdmi->mutex); 2736 drm_dev_exit(idx); 2737 2738 return 0; 2739 } 2740 2741 static int vc4_hdmi_cec_init(struct drm_connector *connector) 2742 { 2743 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2744 struct platform_device *pdev = vc4_hdmi->pdev; 2745 struct device *dev = &pdev->dev; 2746 int ret; 2747 2748 if (vc4_hdmi->variant->external_irq_controller) { 2749 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 2750 vc4_cec_irq_handler_rx_bare, 2751 vc4_cec_irq_handler_rx_thread, 0, 2752 "vc4 hdmi cec rx", vc4_hdmi); 2753 if (ret) 2754 return ret; 2755 2756 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 2757 vc4_cec_irq_handler_tx_bare, 2758 vc4_cec_irq_handler_tx_thread, 0, 2759 "vc4 hdmi cec tx", vc4_hdmi); 2760 if (ret) 2761 return ret; 2762 } else { 2763 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 2764 vc4_cec_irq_handler, 2765 vc4_cec_irq_handler_thread, 0, 2766 "vc4 hdmi cec", vc4_hdmi); 2767 if (ret) 2768 return ret; 2769 } 2770 2771 return 0; 2772 } 2773 2774 static const struct drm_connector_hdmi_cec_funcs vc4_hdmi_cec_funcs = { 2775 .init = vc4_hdmi_cec_init, 2776 .enable = vc4_hdmi_cec_adap_enable, 2777 .log_addr = vc4_hdmi_cec_adap_log_addr, 2778 .transmit = vc4_hdmi_cec_adap_transmit, 2779 }; 2780 2781 static int vc4_hdmi_cec_register(struct vc4_hdmi *vc4_hdmi) 2782 { 2783 struct platform_device *pdev = vc4_hdmi->pdev; 2784 struct device *dev = &pdev->dev; 2785 2786 if (!of_property_present(dev->of_node, "interrupts")) { 2787 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2788 return 0; 2789 } 2790 2791 /* 2792 * NOTE: the CEC adapter will be unregistered by drmm cleanup from 2793 * drm_managed_release(), which is called from drm_dev_release() 2794 * during device unbind. 2795 * 2796 * However, the CEC framework already cleans up the CEC adapter 2797 * only when the last user has closed its file descriptor, so we 2798 * don't need to handle it in DRM. 2799 * 2800 * There's still a problematic sequence: if we unregister our 2801 * CEC adapter, but the userspace keeps a handle on the CEC 2802 * adapter but not the DRM device for some reason. In such a 2803 * case, our vc4_hdmi structure will be freed, but the 2804 * cec_adapter structure will have a dangling pointer to what 2805 * used to be our HDMI controller. If we get a CEC call at that 2806 * moment, we could end up with a use-after-free. Fortunately, 2807 * the CEC framework already handles this too, by calling 2808 * cec_is_registered() in cec_ioctl() and cec_poll(). 2809 */ 2810 return drmm_connector_hdmi_cec_register(&vc4_hdmi->connector, 2811 &vc4_hdmi_cec_funcs, 2812 vc4_hdmi->variant->card_name, 2813 1, 2814 &pdev->dev); 2815 } 2816 #else 2817 static int vc4_hdmi_cec_register(struct vc4_hdmi *vc4_hdmi) 2818 { 2819 return 0; 2820 } 2821 #endif 2822 2823 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 2824 { 2825 struct debugfs_reg32 *regs = ptr; 2826 2827 kfree(regs); 2828 } 2829 2830 static int vc4_hdmi_build_regset(struct drm_device *drm, 2831 struct vc4_hdmi *vc4_hdmi, 2832 struct debugfs_regset32 *regset, 2833 enum vc4_hdmi_regs reg) 2834 { 2835 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2836 struct debugfs_reg32 *regs, *new_regs; 2837 unsigned int count = 0; 2838 unsigned int i; 2839 int ret; 2840 2841 regs = kcalloc(variant->num_registers, sizeof(*regs), 2842 GFP_KERNEL); 2843 if (!regs) 2844 return -ENOMEM; 2845 2846 for (i = 0; i < variant->num_registers; i++) { 2847 const struct vc4_hdmi_register *field = &variant->registers[i]; 2848 2849 if (field->reg != reg) 2850 continue; 2851 2852 regs[count].name = field->name; 2853 regs[count].offset = field->offset; 2854 count++; 2855 } 2856 2857 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2858 if (!new_regs) 2859 return -ENOMEM; 2860 2861 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2862 regset->regs = new_regs; 2863 regset->nregs = count; 2864 2865 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 2866 if (ret) 2867 return ret; 2868 2869 return 0; 2870 } 2871 2872 static int vc4_hdmi_init_resources(struct drm_device *drm, 2873 struct vc4_hdmi *vc4_hdmi) 2874 { 2875 struct platform_device *pdev = vc4_hdmi->pdev; 2876 struct device *dev = &pdev->dev; 2877 int ret; 2878 2879 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2880 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2881 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2882 2883 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2884 if (IS_ERR(vc4_hdmi->hd_regs)) 2885 return PTR_ERR(vc4_hdmi->hd_regs); 2886 2887 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2888 if (ret) 2889 return ret; 2890 2891 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2892 if (ret) 2893 return ret; 2894 2895 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2896 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2897 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2898 if (ret != -EPROBE_DEFER) 2899 drm_err(drm, "Failed to get pixel clock\n"); 2900 return ret; 2901 } 2902 2903 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2904 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2905 drm_err(drm, "Failed to get HDMI state machine clock\n"); 2906 return PTR_ERR(vc4_hdmi->hsm_clock); 2907 } 2908 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2909 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2910 2911 return 0; 2912 } 2913 2914 static int vc5_hdmi_init_resources(struct drm_device *drm, 2915 struct vc4_hdmi *vc4_hdmi) 2916 { 2917 struct platform_device *pdev = vc4_hdmi->pdev; 2918 struct device *dev = &pdev->dev; 2919 struct resource *res; 2920 int ret; 2921 2922 vc4_hdmi->hdmicore_regs = devm_platform_ioremap_resource_byname(pdev, 2923 "hdmi"); 2924 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2925 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2926 2927 /* This is shared between both HDMI controllers. Cannot 2928 * claim for both instances. Lets not convert to using 2929 * devm_platform_ioremap_resource_byname() like 2930 * the rest 2931 */ 2932 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2933 if (!res) 2934 return -ENODEV; 2935 2936 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2937 if (!vc4_hdmi->hd_regs) 2938 return -ENOMEM; 2939 2940 vc4_hdmi->cec_regs = devm_platform_ioremap_resource_byname(pdev, 2941 "cec"); 2942 if (IS_ERR(vc4_hdmi->cec_regs)) 2943 return PTR_ERR(vc4_hdmi->cec_regs); 2944 2945 vc4_hdmi->csc_regs = devm_platform_ioremap_resource_byname(pdev, 2946 "csc"); 2947 if (IS_ERR(vc4_hdmi->csc_regs)) 2948 return PTR_ERR(vc4_hdmi->csc_regs); 2949 2950 vc4_hdmi->dvp_regs = devm_platform_ioremap_resource_byname(pdev, 2951 "dvp"); 2952 if (IS_ERR(vc4_hdmi->dvp_regs)) 2953 return PTR_ERR(vc4_hdmi->dvp_regs); 2954 2955 vc4_hdmi->phy_regs = devm_platform_ioremap_resource_byname(pdev, 2956 "phy"); 2957 2958 if (IS_ERR(vc4_hdmi->phy_regs)) 2959 return PTR_ERR(vc4_hdmi->phy_regs); 2960 2961 vc4_hdmi->ram_regs = devm_platform_ioremap_resource_byname(pdev, 2962 "packet"); 2963 if (IS_ERR(vc4_hdmi->ram_regs)) 2964 return PTR_ERR(vc4_hdmi->ram_regs); 2965 2966 vc4_hdmi->rm_regs = devm_platform_ioremap_resource_byname(pdev, "rm"); 2967 if (IS_ERR(vc4_hdmi->rm_regs)) 2968 return PTR_ERR(vc4_hdmi->rm_regs); 2969 2970 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2971 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2972 drm_err(drm, "Failed to get HDMI state machine clock\n"); 2973 return PTR_ERR(vc4_hdmi->hsm_clock); 2974 } 2975 2976 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2977 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2978 drm_err(drm, "Failed to get pixel bvb clock\n"); 2979 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2980 } 2981 2982 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2983 if (IS_ERR(vc4_hdmi->audio_clock)) { 2984 drm_err(drm, "Failed to get audio clock\n"); 2985 return PTR_ERR(vc4_hdmi->audio_clock); 2986 } 2987 2988 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2989 if (IS_ERR(vc4_hdmi->cec_clock)) { 2990 drm_err(drm, "Failed to get CEC clock\n"); 2991 return PTR_ERR(vc4_hdmi->cec_clock); 2992 } 2993 2994 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2995 if (IS_ERR(vc4_hdmi->reset)) { 2996 drm_err(drm, "Failed to get HDMI reset line\n"); 2997 return PTR_ERR(vc4_hdmi->reset); 2998 } 2999 3000 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3001 if (ret) 3002 return ret; 3003 3004 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3005 if (ret) 3006 return ret; 3007 3008 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3009 if (ret) 3010 return ret; 3011 3012 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3013 if (ret) 3014 return ret; 3015 3016 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3017 if (ret) 3018 return ret; 3019 3020 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3021 if (ret) 3022 return ret; 3023 3024 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3025 if (ret) 3026 return ret; 3027 3028 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3029 if (ret) 3030 return ret; 3031 3032 return 0; 3033 } 3034 3035 static int vc4_hdmi_runtime_suspend(struct device *dev) 3036 { 3037 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3038 3039 clk_disable_unprepare(vc4_hdmi->audio_clock); 3040 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3041 3042 return 0; 3043 } 3044 3045 static int vc4_hdmi_runtime_resume(struct device *dev) 3046 { 3047 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3048 unsigned long __maybe_unused flags; 3049 u32 __maybe_unused value; 3050 unsigned long rate; 3051 int ret; 3052 3053 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3054 if (ret) 3055 return ret; 3056 3057 /* 3058 * Whenever the RaspberryPi boots without an HDMI monitor 3059 * plugged in, the firmware won't have initialized the HSM clock 3060 * rate and it will be reported as 0. 3061 * 3062 * If we try to access a register of the controller in such a 3063 * case, it will lead to a silent CPU stall. Let's make sure we 3064 * prevent such a case. 3065 */ 3066 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3067 if (!rate) { 3068 ret = -EINVAL; 3069 goto err_disable_clk; 3070 } 3071 3072 ret = clk_prepare_enable(vc4_hdmi->audio_clock); 3073 if (ret) 3074 goto err_disable_clk; 3075 3076 if (vc4_hdmi->variant->reset) 3077 vc4_hdmi->variant->reset(vc4_hdmi); 3078 3079 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3080 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3081 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3082 /* Set the logical address to Unregistered */ 3083 value |= VC4_HDMI_CEC_ADDR_MASK; 3084 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3085 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3086 3087 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3088 3089 if (!vc4_hdmi->variant->external_irq_controller) { 3090 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3091 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3092 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3093 } 3094 #endif 3095 3096 return 0; 3097 3098 err_disable_clk: 3099 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3100 return ret; 3101 } 3102 3103 static void vc4_hdmi_put_ddc_device(void *ptr) 3104 { 3105 struct vc4_hdmi *vc4_hdmi = ptr; 3106 3107 put_device(&vc4_hdmi->ddc->dev); 3108 } 3109 3110 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3111 { 3112 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3113 struct platform_device *pdev = to_platform_device(dev); 3114 struct drm_device *drm = dev_get_drvdata(master); 3115 struct vc4_hdmi *vc4_hdmi; 3116 struct drm_encoder *encoder; 3117 struct device_node *ddc_node; 3118 int ret; 3119 3120 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3121 if (!vc4_hdmi) 3122 return -ENOMEM; 3123 3124 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3125 if (ret) 3126 return ret; 3127 3128 spin_lock_init(&vc4_hdmi->hw_lock); 3129 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3130 3131 dev_set_drvdata(dev, vc4_hdmi); 3132 encoder = &vc4_hdmi->encoder.base; 3133 vc4_hdmi->encoder.type = variant->encoder_type; 3134 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3135 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3136 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3137 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3138 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3139 vc4_hdmi->pdev = pdev; 3140 vc4_hdmi->variant = variant; 3141 3142 /* 3143 * Since we don't know the state of the controller and its 3144 * display (if any), let's assume it's always enabled. 3145 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3146 * sure it's disabled, and avoid any inconsistency. 3147 */ 3148 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3149 vc4_hdmi->scdc_enabled = true; 3150 3151 ret = variant->init_resources(drm, vc4_hdmi); 3152 if (ret) 3153 return ret; 3154 3155 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3156 if (!ddc_node) { 3157 drm_err(drm, "Failed to find ddc node in device tree\n"); 3158 return -ENODEV; 3159 } 3160 3161 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3162 of_node_put(ddc_node); 3163 if (!vc4_hdmi->ddc) { 3164 drm_err(drm, "Failed to get ddc i2c adapter by node\n"); 3165 return -EPROBE_DEFER; 3166 } 3167 3168 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3169 if (ret) 3170 return ret; 3171 3172 /* Only use the GPIO HPD pin if present in the DT, otherwise 3173 * we'll use the HDMI core's register. 3174 */ 3175 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3176 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3177 return PTR_ERR(vc4_hdmi->hpd_gpio); 3178 } 3179 3180 vc4_hdmi->disable_wifi_frequencies = 3181 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3182 3183 ret = devm_pm_runtime_enable(dev); 3184 if (ret) 3185 return ret; 3186 3187 /* 3188 * We need to have the device powered up at this point to call 3189 * our reset hook and for the CEC init. 3190 */ 3191 ret = pm_runtime_resume_and_get(dev); 3192 if (ret) 3193 return ret; 3194 3195 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3196 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") || 3197 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") || 3198 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) && 3199 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3200 clk_prepare_enable(vc4_hdmi->pixel_clock); 3201 clk_prepare_enable(vc4_hdmi->hsm_clock); 3202 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3203 } 3204 3205 ret = drmm_encoder_init(drm, encoder, 3206 &vc4_hdmi_encoder_funcs, 3207 DRM_MODE_ENCODER_TMDS, 3208 NULL); 3209 if (ret) 3210 goto err_put_runtime_pm; 3211 3212 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3213 3214 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3215 if (ret) 3216 goto err_put_runtime_pm; 3217 3218 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3219 if (ret) 3220 goto err_put_runtime_pm; 3221 3222 ret = vc4_hdmi_cec_register(vc4_hdmi); 3223 if (ret) 3224 goto err_put_runtime_pm; 3225 3226 ret = vc4_hdmi_audio_init(vc4_hdmi); 3227 if (ret) 3228 goto err_put_runtime_pm; 3229 3230 pm_runtime_put_sync(dev); 3231 3232 return 0; 3233 3234 err_put_runtime_pm: 3235 pm_runtime_put_sync(dev); 3236 3237 return ret; 3238 } 3239 3240 static const struct component_ops vc4_hdmi_ops = { 3241 .bind = vc4_hdmi_bind, 3242 }; 3243 3244 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3245 { 3246 return component_add(&pdev->dev, &vc4_hdmi_ops); 3247 } 3248 3249 static void vc4_hdmi_dev_remove(struct platform_device *pdev) 3250 { 3251 component_del(&pdev->dev, &vc4_hdmi_ops); 3252 } 3253 3254 static const struct vc4_hdmi_variant bcm2835_variant = { 3255 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3256 .debugfs_name = "hdmi_regs", 3257 .card_name = "vc4-hdmi", 3258 .max_pixel_clock = 162000000, 3259 .registers = vc4_hdmi_fields, 3260 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3261 3262 .init_resources = vc4_hdmi_init_resources, 3263 .csc_setup = vc4_hdmi_csc_setup, 3264 .reset = vc4_hdmi_reset, 3265 .set_timings = vc4_hdmi_set_timings, 3266 .phy_init = vc4_hdmi_phy_init, 3267 .phy_disable = vc4_hdmi_phy_disable, 3268 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3269 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3270 .channel_map = vc4_hdmi_channel_map, 3271 .supports_hdr = false, 3272 }; 3273 3274 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3275 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3276 .debugfs_name = "hdmi0_regs", 3277 .card_name = "vc4-hdmi-0", 3278 .max_pixel_clock = 600000000, 3279 .registers = vc5_hdmi_hdmi0_fields, 3280 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3281 .phy_lane_mapping = { 3282 PHY_LANE_0, 3283 PHY_LANE_1, 3284 PHY_LANE_2, 3285 PHY_LANE_CK, 3286 }, 3287 .unsupported_odd_h_timings = true, 3288 .external_irq_controller = true, 3289 3290 .init_resources = vc5_hdmi_init_resources, 3291 .csc_setup = vc5_hdmi_csc_setup, 3292 .reset = vc5_hdmi_reset, 3293 .set_timings = vc5_hdmi_set_timings, 3294 .phy_init = vc5_hdmi_phy_init, 3295 .phy_disable = vc5_hdmi_phy_disable, 3296 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3297 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3298 .channel_map = vc5_hdmi_channel_map, 3299 .supports_hdr = true, 3300 .hp_detect = vc5_hdmi_hp_detect, 3301 }; 3302 3303 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3304 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3305 .debugfs_name = "hdmi1_regs", 3306 .card_name = "vc4-hdmi-1", 3307 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3308 .registers = vc5_hdmi_hdmi1_fields, 3309 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3310 .phy_lane_mapping = { 3311 PHY_LANE_1, 3312 PHY_LANE_0, 3313 PHY_LANE_CK, 3314 PHY_LANE_2, 3315 }, 3316 .unsupported_odd_h_timings = true, 3317 .external_irq_controller = true, 3318 3319 .init_resources = vc5_hdmi_init_resources, 3320 .csc_setup = vc5_hdmi_csc_setup, 3321 .reset = vc5_hdmi_reset, 3322 .set_timings = vc5_hdmi_set_timings, 3323 .phy_init = vc5_hdmi_phy_init, 3324 .phy_disable = vc5_hdmi_phy_disable, 3325 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3326 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3327 .channel_map = vc5_hdmi_channel_map, 3328 .supports_hdr = true, 3329 .hp_detect = vc5_hdmi_hp_detect, 3330 }; 3331 3332 static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = { 3333 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3334 .debugfs_name = "hdmi0_regs", 3335 .card_name = "vc4-hdmi-0", 3336 .max_pixel_clock = 600000000, 3337 .registers = vc6_hdmi_hdmi0_fields, 3338 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi0_fields), 3339 .phy_lane_mapping = { 3340 PHY_LANE_0, 3341 PHY_LANE_1, 3342 PHY_LANE_2, 3343 PHY_LANE_CK, 3344 }, 3345 .unsupported_odd_h_timings = false, 3346 .external_irq_controller = true, 3347 3348 .init_resources = vc5_hdmi_init_resources, 3349 .csc_setup = vc5_hdmi_csc_setup, 3350 .reset = vc5_hdmi_reset, 3351 .set_timings = vc5_hdmi_set_timings, 3352 .phy_init = vc6_hdmi_phy_init, 3353 .phy_disable = vc6_hdmi_phy_disable, 3354 .channel_map = vc5_hdmi_channel_map, 3355 .supports_hdr = true, 3356 .hp_detect = vc5_hdmi_hp_detect, 3357 }; 3358 3359 static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = { 3360 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3361 .debugfs_name = "hdmi1_regs", 3362 .card_name = "vc4-hdmi-1", 3363 .max_pixel_clock = 600000000, 3364 .registers = vc6_hdmi_hdmi1_fields, 3365 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi1_fields), 3366 .phy_lane_mapping = { 3367 PHY_LANE_0, 3368 PHY_LANE_1, 3369 PHY_LANE_2, 3370 PHY_LANE_CK, 3371 }, 3372 .unsupported_odd_h_timings = false, 3373 .external_irq_controller = true, 3374 3375 .init_resources = vc5_hdmi_init_resources, 3376 .csc_setup = vc5_hdmi_csc_setup, 3377 .reset = vc5_hdmi_reset, 3378 .set_timings = vc5_hdmi_set_timings, 3379 .phy_init = vc6_hdmi_phy_init, 3380 .phy_disable = vc6_hdmi_phy_disable, 3381 .channel_map = vc5_hdmi_channel_map, 3382 .supports_hdr = true, 3383 .hp_detect = vc5_hdmi_hp_detect, 3384 }; 3385 3386 static const struct of_device_id vc4_hdmi_dt_match[] = { 3387 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3388 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3389 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3390 { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant }, 3391 { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant }, 3392 {} 3393 }; 3394 3395 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3396 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3397 vc4_hdmi_runtime_resume, 3398 NULL) 3399 }; 3400 3401 struct platform_driver vc4_hdmi_driver = { 3402 .probe = vc4_hdmi_dev_probe, 3403 .remove = vc4_hdmi_dev_remove, 3404 .driver = { 3405 .name = "vc4_hdmi", 3406 .of_match_table = vc4_hdmi_dt_match, 3407 .pm = &vc4_hdmi_pm_ops, 3408 }, 3409 }; 3410