1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_audio_helper.h> 35 #include <drm/display/drm_hdmi_cec_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_hdmi_state_helper.h> 38 #include <drm/display/drm_scdc_helper.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_drv.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/drm_simple_kms_helper.h> 45 #include <linux/clk.h> 46 #include <linux/component.h> 47 #include <linux/gpio/consumer.h> 48 #include <linux/i2c.h> 49 #include <linux/of.h> 50 #include <linux/of_address.h> 51 #include <linux/pm_runtime.h> 52 #include <linux/rational.h> 53 #include <linux/reset.h> 54 #include <sound/dmaengine_pcm.h> 55 #include <sound/hdmi-codec.h> 56 #include <sound/jack.h> 57 #include <sound/pcm_drm_eld.h> 58 #include <sound/pcm_params.h> 59 #include <sound/soc.h> 60 #include "media/cec.h" 61 #include "vc4_drv.h" 62 #include "vc4_hdmi.h" 63 #include "vc4_hdmi_regs.h" 64 #include "vc4_regs.h" 65 66 #define VC5_HDMI_HORZA_HFP_SHIFT 16 67 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 68 #define VC5_HDMI_HORZA_VPOS BIT(15) 69 #define VC5_HDMI_HORZA_HPOS BIT(14) 70 #define VC5_HDMI_HORZA_HAP_SHIFT 0 71 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 72 73 #define VC5_HDMI_HORZB_HBP_SHIFT 16 74 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 75 #define VC5_HDMI_HORZB_HSP_SHIFT 0 76 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 77 78 #define VC5_HDMI_VERTA_VSP_SHIFT 24 79 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 80 #define VC5_HDMI_VERTA_VFP_SHIFT 16 81 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 82 #define VC5_HDMI_VERTA_VAL_SHIFT 0 83 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 84 85 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 86 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 87 88 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 89 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 90 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 91 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 92 93 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 94 95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 96 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 97 98 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 99 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 100 101 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 102 103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 105 106 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0) 107 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0) 108 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4) 109 110 # define VC4_HD_M_SW_RST BIT(2) 111 # define VC4_HD_M_ENABLE BIT(0) 112 113 #define HSM_MIN_CLOCK_FREQ 120000000 114 #define CEC_CLOCK_FREQ 40000 115 116 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 117 118 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 119 { 120 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 121 122 lockdep_assert_held(&vc4_hdmi->mutex); 123 124 if (!display->is_hdmi) 125 return false; 126 127 if (!display->hdmi.scdc.supported || 128 !display->hdmi.scdc.scrambling.supported) 129 return false; 130 131 return true; 132 } 133 134 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 135 unsigned int bpc, 136 enum hdmi_colorspace fmt) 137 { 138 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt); 139 140 return clock > HDMI_14_MAX_TMDS_CLK; 141 } 142 143 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 144 { 145 struct drm_debugfs_entry *entry = m->private; 146 struct vc4_hdmi *vc4_hdmi = entry->file.data; 147 struct drm_device *drm = vc4_hdmi->connector.dev; 148 struct drm_printer p = drm_seq_file_printer(m); 149 int idx; 150 151 if (!drm_dev_enter(drm, &idx)) 152 return -ENODEV; 153 154 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 155 156 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 157 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 158 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 159 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 160 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 161 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 162 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 163 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 164 165 pm_runtime_put(&vc4_hdmi->pdev->dev); 166 167 drm_dev_exit(idx); 168 169 return 0; 170 } 171 172 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 173 { 174 struct drm_device *drm = vc4_hdmi->connector.dev; 175 unsigned long flags; 176 int idx; 177 178 /* 179 * We can be called by our bind callback, when the 180 * connector->dev pointer might not be initialised yet. 181 */ 182 if (drm && !drm_dev_enter(drm, &idx)) 183 return; 184 185 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 186 187 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 188 udelay(1); 189 HDMI_WRITE(HDMI_M_CTL, 0); 190 191 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 192 193 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 194 VC4_HDMI_SW_RESET_HDMI | 195 VC4_HDMI_SW_RESET_FORMAT_DETECT); 196 197 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 198 199 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 200 201 if (drm) 202 drm_dev_exit(idx); 203 } 204 205 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 206 { 207 struct drm_device *drm = vc4_hdmi->connector.dev; 208 unsigned long flags; 209 int idx; 210 211 /* 212 * We can be called by our bind callback, when the 213 * connector->dev pointer might not be initialised yet. 214 */ 215 if (drm && !drm_dev_enter(drm, &idx)) 216 return; 217 218 reset_control_reset(vc4_hdmi->reset); 219 220 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 221 222 HDMI_WRITE(HDMI_DVP_CTL, 0); 223 224 HDMI_WRITE(HDMI_CLOCK_STOP, 225 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 226 227 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 228 229 if (drm) 230 drm_dev_exit(idx); 231 } 232 233 #ifdef CONFIG_DRM_VC4_HDMI_CEC 234 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 235 { 236 struct drm_device *drm = vc4_hdmi->connector.dev; 237 unsigned long cec_rate; 238 unsigned long flags; 239 u16 clk_cnt; 240 u32 value; 241 int idx; 242 243 /* 244 * This function is called by our runtime_resume implementation 245 * and thus at bind time, when we haven't registered our 246 * connector yet and thus don't have a pointer to the DRM 247 * device. 248 */ 249 if (drm && !drm_dev_enter(drm, &idx)) 250 return; 251 252 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 253 254 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 255 256 value = HDMI_READ(HDMI_CEC_CNTRL_1); 257 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 258 259 /* 260 * Set the clock divider: the hsm_clock rate and this divider 261 * setting will give a 40 kHz CEC clock. 262 */ 263 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 264 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 265 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 266 267 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 268 269 if (drm) 270 drm_dev_exit(idx); 271 } 272 #else 273 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 274 #endif 275 276 static int vc4_hdmi_reset_link(struct drm_connector *connector, 277 struct drm_modeset_acquire_ctx *ctx) 278 { 279 struct drm_device *drm; 280 struct vc4_hdmi *vc4_hdmi; 281 struct drm_connector_state *conn_state; 282 struct drm_crtc_state *crtc_state; 283 struct drm_crtc *crtc; 284 bool scrambling_needed; 285 u8 config; 286 int ret; 287 288 if (!connector) 289 return 0; 290 291 drm = connector->dev; 292 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 293 if (ret) 294 return ret; 295 296 conn_state = connector->state; 297 crtc = conn_state->crtc; 298 if (!crtc) 299 return 0; 300 301 ret = drm_modeset_lock(&crtc->mutex, ctx); 302 if (ret) 303 return ret; 304 305 crtc_state = crtc->state; 306 if (!crtc_state->active) 307 return 0; 308 309 vc4_hdmi = connector_to_vc4_hdmi(connector); 310 mutex_lock(&vc4_hdmi->mutex); 311 312 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 313 mutex_unlock(&vc4_hdmi->mutex); 314 return 0; 315 } 316 317 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 318 vc4_hdmi->output_bpc, 319 vc4_hdmi->output_format); 320 if (!scrambling_needed) { 321 mutex_unlock(&vc4_hdmi->mutex); 322 return 0; 323 } 324 325 if (conn_state->commit && 326 !try_wait_for_completion(&conn_state->commit->hw_done)) { 327 mutex_unlock(&vc4_hdmi->mutex); 328 return 0; 329 } 330 331 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 332 if (ret < 0) { 333 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 334 mutex_unlock(&vc4_hdmi->mutex); 335 return 0; 336 } 337 338 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 339 mutex_unlock(&vc4_hdmi->mutex); 340 return 0; 341 } 342 343 mutex_unlock(&vc4_hdmi->mutex); 344 345 /* 346 * HDMI 2.0 says that one should not send scrambled data 347 * prior to configuring the sink scrambling, and that 348 * TMDS clock/data transmission should be suspended when 349 * changing the TMDS clock rate in the sink. So let's 350 * just do a full modeset here, even though some sinks 351 * would be perfectly happy if were to just reconfigure 352 * the SCDC settings on the fly. 353 */ 354 return drm_atomic_helper_reset_crtc(crtc, ctx); 355 } 356 357 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 358 struct drm_modeset_acquire_ctx *ctx, 359 enum drm_connector_status status) 360 { 361 struct drm_connector *connector = &vc4_hdmi->connector; 362 int ret; 363 364 /* 365 * NOTE: This function should really be called with vc4_hdmi->mutex 366 * held, but doing so results in reentrancy issues since 367 * cec_s_phys_addr() might call .adap_enable, which leads to that 368 * funtion being called with our mutex held. 369 * 370 * A similar situation occurs with vc4_hdmi_reset_link() that 371 * will call into our KMS hooks if the scrambling was enabled. 372 * 373 * Concurrency isn't an issue at the moment since we don't share 374 * any state with any of the other frameworks so we can ignore 375 * the lock for now. 376 */ 377 378 drm_atomic_helper_connector_hdmi_hotplug(connector, status); 379 380 if (status != connector_status_connected) 381 return; 382 383 for (;;) { 384 ret = vc4_hdmi_reset_link(connector, ctx); 385 if (ret == -EDEADLK) { 386 drm_modeset_backoff(ctx); 387 continue; 388 } 389 390 break; 391 } 392 } 393 394 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 395 struct drm_modeset_acquire_ctx *ctx, 396 bool force) 397 { 398 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 399 enum drm_connector_status status = connector_status_disconnected; 400 int ret; 401 402 /* 403 * NOTE: This function should really take vc4_hdmi->mutex, but 404 * doing so results in reentrancy issues since 405 * vc4_hdmi_handle_hotplug() can call into other functions that 406 * would take the mutex while it's held here. 407 * 408 * Concurrency isn't an issue at the moment since we don't share 409 * any state with any of the other frameworks so we can ignore 410 * the lock for now. 411 */ 412 413 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 414 if (ret) { 415 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n", 416 ret); 417 return connector_status_unknown; 418 } 419 420 if (vc4_hdmi->hpd_gpio) { 421 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 422 status = connector_status_connected; 423 } else { 424 if (vc4_hdmi->variant->hp_detect && 425 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 426 status = connector_status_connected; 427 } 428 429 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 430 pm_runtime_put(&vc4_hdmi->pdev->dev); 431 432 return status; 433 } 434 435 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 436 { 437 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 438 int ret = 0; 439 440 ret = drm_edid_connector_add_modes(connector); 441 442 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 443 struct drm_device *drm = connector->dev; 444 const struct drm_display_mode *mode; 445 446 list_for_each_entry(mode, &connector->probed_modes, head) { 447 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) { 448 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 449 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 450 } 451 } 452 } 453 454 return ret; 455 } 456 457 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 458 struct drm_atomic_state *state) 459 { 460 struct drm_connector_state *old_state = 461 drm_atomic_get_old_connector_state(state, connector); 462 struct drm_connector_state *new_state = 463 drm_atomic_get_new_connector_state(state, connector); 464 struct drm_crtc *crtc = new_state->crtc; 465 466 if (!crtc) 467 return 0; 468 469 if (old_state->tv.margins.left != new_state->tv.margins.left || 470 old_state->tv.margins.right != new_state->tv.margins.right || 471 old_state->tv.margins.top != new_state->tv.margins.top || 472 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 473 struct drm_crtc_state *crtc_state; 474 int ret; 475 476 crtc_state = drm_atomic_get_crtc_state(state, crtc); 477 if (IS_ERR(crtc_state)) 478 return PTR_ERR(crtc_state); 479 480 /* 481 * Strictly speaking, we should be calling 482 * drm_atomic_helper_check_planes() after our call to 483 * drm_atomic_add_affected_planes(). However, the 484 * connector atomic_check is called as part of 485 * drm_atomic_helper_check_modeset() that already 486 * happens before a call to 487 * drm_atomic_helper_check_planes() in 488 * drm_atomic_helper_check(). 489 */ 490 ret = drm_atomic_add_affected_planes(state, crtc); 491 if (ret) 492 return ret; 493 } 494 495 if (old_state->colorspace != new_state->colorspace) { 496 struct drm_crtc_state *crtc_state; 497 498 crtc_state = drm_atomic_get_crtc_state(state, crtc); 499 if (IS_ERR(crtc_state)) 500 return PTR_ERR(crtc_state); 501 502 crtc_state->mode_changed = true; 503 } 504 505 return drm_atomic_helper_connector_hdmi_check(connector, state); 506 } 507 508 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 509 { 510 drm_atomic_helper_connector_reset(connector); 511 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); 512 drm_atomic_helper_connector_tv_margins_reset(connector); 513 } 514 515 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 516 .force = drm_atomic_helper_connector_hdmi_force, 517 .fill_modes = drm_helper_probe_single_connector_modes, 518 .reset = vc4_hdmi_connector_reset, 519 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 520 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 521 }; 522 523 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 524 .detect_ctx = vc4_hdmi_connector_detect_ctx, 525 .get_modes = vc4_hdmi_connector_get_modes, 526 .atomic_check = vc4_hdmi_connector_atomic_check, 527 .mode_valid = drm_hdmi_connector_mode_valid, 528 }; 529 530 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs; 531 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs; 532 533 static int vc4_hdmi_connector_init(struct drm_device *dev, 534 struct vc4_hdmi *vc4_hdmi) 535 { 536 struct drm_connector *connector = &vc4_hdmi->connector; 537 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 538 unsigned int max_bpc = 8; 539 int ret; 540 541 if (vc4_hdmi->variant->supports_hdr) 542 max_bpc = 12; 543 544 ret = drmm_connector_hdmi_init(dev, connector, 545 "Broadcom", "Videocore", 546 &vc4_hdmi_connector_funcs, 547 &vc4_hdmi_hdmi_connector_funcs, 548 DRM_MODE_CONNECTOR_HDMIA, 549 vc4_hdmi->ddc, 550 BIT(HDMI_COLORSPACE_RGB) | 551 BIT(HDMI_COLORSPACE_YUV422) | 552 BIT(HDMI_COLORSPACE_YUV444), 553 max_bpc); 554 if (ret) 555 return ret; 556 557 ret = drm_connector_hdmi_audio_init(connector, dev->dev, 558 &vc4_hdmi_audio_funcs, 559 8, 0, false, -1); 560 if (ret) 561 return ret; 562 563 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 564 565 /* 566 * Some of the properties below require access to state, like bpc. 567 * Allocate some default initial connector state with our reset helper. 568 */ 569 if (connector->funcs->reset) 570 connector->funcs->reset(connector); 571 572 /* Create and attach TV margin props to this connector. */ 573 ret = drm_mode_create_tv_margin_properties(dev); 574 if (ret) 575 return ret; 576 577 ret = drm_mode_create_hdmi_colorspace_property(connector, 0); 578 if (ret) 579 return ret; 580 581 drm_connector_attach_colorspace_property(connector); 582 drm_connector_attach_tv_margin_properties(connector); 583 584 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 585 DRM_CONNECTOR_POLL_DISCONNECT); 586 587 connector->interlace_allowed = 1; 588 connector->doublescan_allowed = 0; 589 connector->stereo_allowed = 1; 590 591 ret = drm_connector_attach_broadcast_rgb_property(connector); 592 if (ret) 593 return ret; 594 595 drm_connector_attach_encoder(connector, encoder); 596 597 return 0; 598 } 599 600 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi, 601 enum hdmi_infoframe_type type, 602 bool poll) 603 { 604 struct drm_device *drm = vc4_hdmi->connector.dev; 605 u32 packet_id = type - 0x80; 606 unsigned long flags; 607 int ret = 0; 608 int idx; 609 610 if (!drm_dev_enter(drm, &idx)) 611 return -ENODEV; 612 613 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 614 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 615 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 616 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 617 618 if (poll) { 619 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 620 BIT(packet_id)), 100); 621 } 622 623 drm_dev_exit(idx); 624 return ret; 625 } 626 627 static int vc4_hdmi_clear_infoframe(struct drm_connector *connector, 628 enum hdmi_infoframe_type type) 629 { 630 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 631 struct drm_device *drm = connector->dev; 632 int ret; 633 int idx; 634 635 if (!drm_dev_enter(drm, &idx)) 636 return 0; 637 638 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 639 VC4_HDMI_RAM_PACKET_ENABLE), 640 "Packet RAM has to be on to store the packet."); 641 642 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true); 643 if (ret) 644 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret); 645 646 drm_dev_exit(idx); 647 648 return ret; 649 } 650 651 static int vc4_hdmi_write_infoframe(struct drm_connector *connector, 652 enum hdmi_infoframe_type type, 653 const u8 *infoframe, size_t len) 654 { 655 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 656 struct drm_device *drm = connector->dev; 657 u32 packet_id = type - 0x80; 658 const struct vc4_hdmi_register *ram_packet_start = 659 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 660 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 661 u32 packet_reg_next = ram_packet_start->offset + 662 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 663 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 664 ram_packet_start->reg); 665 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 666 unsigned long flags; 667 ssize_t i; 668 int ret; 669 int idx; 670 671 if (!drm_dev_enter(drm, &idx)) 672 return 0; 673 674 if (len > sizeof(buffer)) { 675 ret = -ENOMEM; 676 goto out; 677 } 678 679 memcpy(buffer, infoframe, len); 680 681 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 682 VC4_HDMI_RAM_PACKET_ENABLE), 683 "Packet RAM has to be on to store the packet."); 684 685 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true); 686 if (ret) { 687 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret); 688 goto out; 689 } 690 691 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 692 693 for (i = 0; i < len; i += 7) { 694 writel(buffer[i + 0] << 0 | 695 buffer[i + 1] << 8 | 696 buffer[i + 2] << 16, 697 base + packet_reg); 698 packet_reg += 4; 699 700 writel(buffer[i + 3] << 0 | 701 buffer[i + 4] << 8 | 702 buffer[i + 5] << 16 | 703 buffer[i + 6] << 24, 704 base + packet_reg); 705 packet_reg += 4; 706 } 707 708 /* 709 * clear remainder of packet ram as it's included in the 710 * infoframe and triggers a checksum error on hdmi analyser 711 */ 712 for (; packet_reg < packet_reg_next; packet_reg += 4) 713 writel(0, base + packet_reg); 714 715 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 716 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 717 718 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 719 720 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 721 BIT(packet_id)), 100); 722 if (ret) 723 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret); 724 725 out: 726 drm_dev_exit(idx); 727 return ret; 728 } 729 730 static int vc4_hdmi_clear_avi_infoframe(struct drm_connector *connector) 731 { 732 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_AVI); 733 } 734 735 static int vc4_hdmi_clear_hdmi_infoframe(struct drm_connector *connector) 736 { 737 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_VENDOR); 738 } 739 740 static int vc4_hdmi_clear_audio_infoframe(struct drm_connector *connector) 741 { 742 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_AUDIO); 743 } 744 745 static int vc4_hdmi_clear_hdr_drm_infoframe(struct drm_connector *connector) 746 { 747 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_DRM); 748 } 749 750 static int vc4_hdmi_clear_spd_infoframe(struct drm_connector *connector) 751 { 752 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_SPD); 753 } 754 755 static int vc4_hdmi_write_avi_infoframe(struct drm_connector *connector, 756 const u8 *buffer, size_t len) 757 { 758 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_AVI, 759 buffer, len); 760 } 761 762 static int vc4_hdmi_write_hdmi_infoframe(struct drm_connector *connector, 763 const u8 *buffer, size_t len) 764 { 765 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_VENDOR, 766 buffer, len); 767 } 768 769 static int vc4_hdmi_write_audio_infoframe(struct drm_connector *connector, 770 const u8 *buffer, size_t len) 771 { 772 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_AUDIO, 773 buffer, len); 774 } 775 776 static int vc4_hdmi_write_hdr_drm_infoframe(struct drm_connector *connector, 777 const u8 *buffer, size_t len) 778 { 779 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_DRM, 780 buffer, len); 781 } 782 783 static int vc4_hdmi_write_spd_infoframe(struct drm_connector *connector, 784 const u8 *buffer, size_t len) 785 { 786 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_SPD, 787 buffer, len); 788 } 789 790 #define SCRAMBLING_POLLING_DELAY_MS 1000 791 792 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 793 { 794 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 795 struct drm_connector *connector = &vc4_hdmi->connector; 796 struct drm_device *drm = connector->dev; 797 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 798 unsigned long flags; 799 int idx; 800 801 lockdep_assert_held(&vc4_hdmi->mutex); 802 803 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 804 return; 805 806 if (!vc4_hdmi_mode_needs_scrambling(mode, 807 vc4_hdmi->output_bpc, 808 vc4_hdmi->output_format)) 809 return; 810 811 if (!drm_dev_enter(drm, &idx)) 812 return; 813 814 drm_scdc_set_high_tmds_clock_ratio(connector, true); 815 drm_scdc_set_scrambling(connector, true); 816 817 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 818 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 819 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 820 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 821 822 drm_dev_exit(idx); 823 824 vc4_hdmi->scdc_enabled = true; 825 826 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 827 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 828 } 829 830 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 831 { 832 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 833 struct drm_connector *connector = &vc4_hdmi->connector; 834 struct drm_device *drm = connector->dev; 835 unsigned long flags; 836 int idx; 837 838 lockdep_assert_held(&vc4_hdmi->mutex); 839 840 if (!vc4_hdmi->scdc_enabled) 841 return; 842 843 vc4_hdmi->scdc_enabled = false; 844 845 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 846 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 847 848 if (!drm_dev_enter(drm, &idx)) 849 return; 850 851 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 852 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 853 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 854 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 855 856 drm_scdc_set_scrambling(connector, false); 857 drm_scdc_set_high_tmds_clock_ratio(connector, false); 858 859 drm_dev_exit(idx); 860 } 861 862 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 863 { 864 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 865 struct vc4_hdmi, 866 scrambling_work); 867 struct drm_connector *connector = &vc4_hdmi->connector; 868 869 if (drm_scdc_get_scrambling_status(connector)) 870 return; 871 872 drm_scdc_set_high_tmds_clock_ratio(connector, true); 873 drm_scdc_set_scrambling(connector, true); 874 875 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 876 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 877 } 878 879 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 880 struct drm_atomic_state *state) 881 { 882 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 883 struct drm_device *drm = vc4_hdmi->connector.dev; 884 struct vc4_dev *vc4 = to_vc4_dev(drm); 885 unsigned long flags; 886 int idx; 887 888 mutex_lock(&vc4_hdmi->mutex); 889 890 vc4_hdmi->packet_ram_enabled = false; 891 892 if (!drm_dev_enter(drm, &idx)) 893 goto out; 894 895 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 896 897 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 898 899 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 900 901 if (vc4->gen >= VC4_GEN_6_C) 902 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 903 VC4_HD_VID_CTL_BLANKPIX); 904 905 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 906 907 mdelay(1); 908 909 /* 910 * TODO: This should work on BCM2712, but doesn't for some 911 * reason and result in a system lockup. 912 */ 913 if (vc4->gen < VC4_GEN_6_C) { 914 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 915 HDMI_WRITE(HDMI_VID_CTL, 916 HDMI_READ(HDMI_VID_CTL) & 917 ~VC4_HD_VID_CTL_ENABLE); 918 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 919 } 920 921 vc4_hdmi_disable_scrambling(encoder); 922 923 drm_dev_exit(idx); 924 925 out: 926 mutex_unlock(&vc4_hdmi->mutex); 927 } 928 929 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 930 struct drm_atomic_state *state) 931 { 932 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 933 struct drm_device *drm = vc4_hdmi->connector.dev; 934 unsigned long flags; 935 int ret; 936 int idx; 937 938 mutex_lock(&vc4_hdmi->mutex); 939 940 if (!drm_dev_enter(drm, &idx)) 941 goto out; 942 943 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 944 HDMI_WRITE(HDMI_VID_CTL, 945 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 946 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 947 948 if (vc4_hdmi->variant->phy_disable) 949 vc4_hdmi->variant->phy_disable(vc4_hdmi); 950 951 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 952 clk_disable_unprepare(vc4_hdmi->pixel_clock); 953 954 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 955 if (ret < 0) 956 drm_err(drm, "Failed to release power domain: %d\n", ret); 957 958 drm_dev_exit(idx); 959 960 out: 961 mutex_unlock(&vc4_hdmi->mutex); 962 } 963 964 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 965 struct drm_connector_state *state, 966 const struct drm_display_mode *mode) 967 { 968 struct drm_device *drm = vc4_hdmi->connector.dev; 969 unsigned long flags; 970 u32 csc_ctl; 971 int idx; 972 973 if (!drm_dev_enter(drm, &idx)) 974 return; 975 976 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 977 978 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 979 VC4_HD_CSC_CTL_ORDER); 980 981 if (state->hdmi.is_limited_range) { 982 /* CEA VICs other than #1 requre limited range RGB 983 * output unless overridden by an AVI infoframe. 984 * Apply a colorspace conversion to squash 0-255 down 985 * to 16-235. The matrix here is: 986 * 987 * [ 0 0 0.8594 16] 988 * [ 0 0.8594 0 16] 989 * [ 0.8594 0 0 16] 990 * [ 0 0 0 1] 991 */ 992 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 993 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 994 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 995 VC4_HD_CSC_CTL_MODE); 996 997 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 998 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 999 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 1000 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 1001 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 1002 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 1003 } 1004 1005 /* The RGB order applies even when CSC is disabled. */ 1006 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1007 1008 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1009 1010 drm_dev_exit(idx); 1011 } 1012 1013 /* 1014 * Matrices for (internal) RGB to RGB output. 1015 * 1016 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1017 */ 1018 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = { 1019 { 1020 /* 1021 * Full range - unity 1022 * 1023 * [ 1 0 0 0] 1024 * [ 0 1 0 0] 1025 * [ 0 0 1 0] 1026 */ 1027 { 0x2000, 0x0000, 0x0000, 0x0000 }, 1028 { 0x0000, 0x2000, 0x0000, 0x0000 }, 1029 { 0x0000, 0x0000, 0x2000, 0x0000 }, 1030 }, 1031 { 1032 /* 1033 * Limited range 1034 * 1035 * CEA VICs other than #1 require limited range RGB 1036 * output unless overridden by an AVI infoframe. Apply a 1037 * colorspace conversion to squash 0-255 down to 16-235. 1038 * The matrix here is: 1039 * 1040 * [ 0.8594 0 0 16] 1041 * [ 0 0.8594 0 16] 1042 * [ 0 0 0.8594 16] 1043 */ 1044 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 1045 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 1046 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 1047 }, 1048 }; 1049 1050 /* 1051 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace 1052 * 1053 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1054 */ 1055 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = { 1056 { 1057 /* 1058 * Full Range 1059 * 1060 * [ 0.299000 0.587000 0.114000 0 ] 1061 * [ -0.168736 -0.331264 0.500000 128 ] 1062 * [ 0.500000 -0.418688 -0.081312 128 ] 1063 */ 1064 { 0x0991, 0x12c9, 0x03a6, 0x0000 }, 1065 { 0xfa9b, 0xf567, 0x1000, 0x2000 }, 1066 { 0x1000, 0xf29b, 0xfd67, 0x2000 }, 1067 }, 1068 { 1069 /* Limited Range 1070 * 1071 * [ 0.255785 0.502160 0.097523 16 ] 1072 * [ -0.147644 -0.289856 0.437500 128 ] 1073 * [ 0.437500 -0.366352 -0.071148 128 ] 1074 */ 1075 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1076 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1077 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1078 }, 1079 }; 1080 1081 /* 1082 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace 1083 * 1084 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1085 */ 1086 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = { 1087 { 1088 /* 1089 * Full Range 1090 * 1091 * [ 0.212600 0.715200 0.072200 0 ] 1092 * [ -0.114572 -0.385428 0.500000 128 ] 1093 * [ 0.500000 -0.454153 -0.045847 128 ] 1094 */ 1095 { 0x06ce, 0x16e3, 0x024f, 0x0000 }, 1096 { 0xfc56, 0xf3ac, 0x1000, 0x2000 }, 1097 { 0x1000, 0xf179, 0xfe89, 0x2000 }, 1098 }, 1099 { 1100 /* 1101 * Limited Range 1102 * 1103 * [ 0.181906 0.611804 0.061758 16 ] 1104 * [ -0.100268 -0.337232 0.437500 128 ] 1105 * [ 0.437500 -0.397386 -0.040114 128 ] 1106 */ 1107 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1108 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1109 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1110 }, 1111 }; 1112 1113 /* 1114 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace 1115 * 1116 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1117 */ 1118 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = { 1119 { 1120 /* 1121 * Full Range 1122 * 1123 * [ 0.262700 0.678000 0.059300 0 ] 1124 * [ -0.139630 -0.360370 0.500000 128 ] 1125 * [ 0.500000 -0.459786 -0.040214 128 ] 1126 */ 1127 { 0x0868, 0x15b2, 0x01e6, 0x0000 }, 1128 { 0xfb89, 0xf479, 0x1000, 0x2000 }, 1129 { 0x1000, 0xf14a, 0xfeb8, 0x2000 }, 1130 }, 1131 { 1132 /* Limited Range 1133 * 1134 * [ 0.224732 0.580008 0.050729 16 ] 1135 * [ -0.122176 -0.315324 0.437500 128 ] 1136 * [ 0.437500 -0.402312 -0.035188 128 ] 1137 */ 1138 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1139 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1140 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1141 }, 1142 }; 1143 1144 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1145 const u16 coeffs[3][4]) 1146 { 1147 lockdep_assert_held(&vc4_hdmi->hw_lock); 1148 1149 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1150 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1151 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1152 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1153 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1154 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1155 } 1156 1157 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi, 1158 const u16 coeffs[3][4]) 1159 { 1160 lockdep_assert_held(&vc4_hdmi->hw_lock); 1161 1162 /* YUV444 needs the CSC matrices using the channels in a different order */ 1163 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]); 1164 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]); 1165 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]); 1166 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]); 1167 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]); 1168 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]); 1169 } 1170 1171 static const u16 1172 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4] 1173 { 1174 switch (colorspace) { 1175 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC: 1176 case DRM_MODE_COLORIMETRY_XVYCC_601: 1177 case DRM_MODE_COLORIMETRY_SYCC_601: 1178 case DRM_MODE_COLORIMETRY_OPYCC_601: 1179 case DRM_MODE_COLORIMETRY_BT601_YCC: 1180 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited]; 1181 1182 default: 1183 case DRM_MODE_COLORIMETRY_NO_DATA: 1184 case DRM_MODE_COLORIMETRY_BT709_YCC: 1185 case DRM_MODE_COLORIMETRY_XVYCC_709: 1186 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED: 1187 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT: 1188 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited]; 1189 1190 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 1191 case DRM_MODE_COLORIMETRY_BT2020_YCC: 1192 case DRM_MODE_COLORIMETRY_BT2020_RGB: 1193 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 1194 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 1195 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited]; 1196 } 1197 } 1198 1199 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1200 struct drm_connector_state *state, 1201 const struct drm_display_mode *mode) 1202 { 1203 struct drm_device *drm = vc4_hdmi->connector.dev; 1204 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0; 1205 unsigned long flags; 1206 const u16 (*csc)[4]; 1207 u32 if_cfg = 0; 1208 u32 if_xbar = 0x543210; 1209 u32 csc_chan_ctl = 0; 1210 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1211 VC5_MT_CP_CSC_CTL_MODE); 1212 int idx; 1213 1214 if (!drm_dev_enter(drm, &idx)) 1215 return; 1216 1217 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1218 1219 switch (state->hdmi.output_format) { 1220 case HDMI_COLORSPACE_YUV444: 1221 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1222 1223 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc); 1224 break; 1225 1226 case HDMI_COLORSPACE_YUV422: 1227 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1228 1229 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1230 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1231 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1232 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1233 1234 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1235 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1236 1237 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1238 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1239 1240 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc); 1241 break; 1242 1243 case HDMI_COLORSPACE_RGB: 1244 if_xbar = 0x354021; 1245 1246 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]); 1247 break; 1248 1249 default: 1250 break; 1251 } 1252 1253 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1254 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1255 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1256 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1257 1258 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1259 1260 drm_dev_exit(idx); 1261 } 1262 1263 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1264 struct drm_connector_state *state, 1265 const struct drm_display_mode *mode) 1266 { 1267 struct drm_device *drm = vc4_hdmi->connector.dev; 1268 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1269 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1270 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1271 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1272 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1273 VC4_HDMI_VERTA_VSP) | 1274 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1275 VC4_HDMI_VERTA_VFP) | 1276 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1277 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1278 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1279 interlaced, 1280 VC4_HDMI_VERTB_VBP)); 1281 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1282 VC4_SET_FIELD(mode->crtc_vtotal - 1283 mode->crtc_vsync_end, 1284 VC4_HDMI_VERTB_VBP)); 1285 unsigned long flags; 1286 u32 reg; 1287 int idx; 1288 1289 if (!drm_dev_enter(drm, &idx)) 1290 return; 1291 1292 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1293 1294 HDMI_WRITE(HDMI_HORZA, 1295 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1296 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1297 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1298 VC4_HDMI_HORZA_HAP)); 1299 1300 HDMI_WRITE(HDMI_HORZB, 1301 VC4_SET_FIELD((mode->htotal - 1302 mode->hsync_end) * pixel_rep, 1303 VC4_HDMI_HORZB_HBP) | 1304 VC4_SET_FIELD((mode->hsync_end - 1305 mode->hsync_start) * pixel_rep, 1306 VC4_HDMI_HORZB_HSP) | 1307 VC4_SET_FIELD((mode->hsync_start - 1308 mode->hdisplay) * pixel_rep, 1309 VC4_HDMI_HORZB_HFP)); 1310 1311 HDMI_WRITE(HDMI_VERTA0, verta); 1312 HDMI_WRITE(HDMI_VERTA1, verta); 1313 1314 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1315 HDMI_WRITE(HDMI_VERTB1, vertb); 1316 1317 reg = HDMI_READ(HDMI_MISC_CONTROL); 1318 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1319 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1320 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1321 1322 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1323 1324 drm_dev_exit(idx); 1325 } 1326 1327 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1328 struct drm_connector_state *state, 1329 const struct drm_display_mode *mode) 1330 { 1331 struct drm_device *drm = vc4_hdmi->connector.dev; 1332 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1333 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1334 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1335 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1336 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1337 VC5_HDMI_VERTA_VSP) | 1338 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1339 VC5_HDMI_VERTA_VFP) | 1340 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1341 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1342 VC5_HDMI_VERTB_VSPO) | 1343 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1344 interlaced, 1345 VC4_HDMI_VERTB_VBP)); 1346 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1347 VC4_SET_FIELD(mode->crtc_vtotal - 1348 mode->crtc_vsync_end, 1349 VC4_HDMI_VERTB_VBP)); 1350 unsigned long flags; 1351 unsigned char gcp; 1352 u32 reg; 1353 int idx; 1354 1355 if (!drm_dev_enter(drm, &idx)) 1356 return; 1357 1358 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1359 1360 HDMI_WRITE(HDMI_HORZA, 1361 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1362 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1363 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1364 VC5_HDMI_HORZA_HAP) | 1365 VC4_SET_FIELD((mode->hsync_start - 1366 mode->hdisplay) * pixel_rep, 1367 VC5_HDMI_HORZA_HFP)); 1368 1369 HDMI_WRITE(HDMI_HORZB, 1370 VC4_SET_FIELD((mode->htotal - 1371 mode->hsync_end) * pixel_rep, 1372 VC5_HDMI_HORZB_HBP) | 1373 VC4_SET_FIELD((mode->hsync_end - 1374 mode->hsync_start) * pixel_rep, 1375 VC5_HDMI_HORZB_HSP)); 1376 1377 HDMI_WRITE(HDMI_VERTA0, verta); 1378 HDMI_WRITE(HDMI_VERTA1, verta); 1379 1380 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1381 HDMI_WRITE(HDMI_VERTB1, vertb); 1382 1383 switch (state->hdmi.output_bpc) { 1384 case 12: 1385 gcp = 6; 1386 break; 1387 case 10: 1388 gcp = 5; 1389 break; 1390 case 8: 1391 default: 1392 gcp = 0; 1393 break; 1394 } 1395 1396 /* 1397 * YCC422 is always 36-bit and not considered deep colour so 1398 * doesn't signal in GCP. 1399 */ 1400 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) { 1401 gcp = 0; 1402 } 1403 1404 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1405 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1406 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1407 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1408 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1409 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1410 1411 reg = HDMI_READ(HDMI_GCP_WORD_1); 1412 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1413 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1414 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK; 1415 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE; 1416 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1417 1418 reg = HDMI_READ(HDMI_GCP_CONFIG); 1419 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1420 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1421 1422 reg = HDMI_READ(HDMI_MISC_CONTROL); 1423 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1424 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1425 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1426 1427 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1428 1429 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1430 1431 drm_dev_exit(idx); 1432 } 1433 1434 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1435 { 1436 struct drm_device *drm = vc4_hdmi->connector.dev; 1437 unsigned long flags; 1438 u32 drift; 1439 int ret; 1440 int idx; 1441 1442 if (!drm_dev_enter(drm, &idx)) 1443 return; 1444 1445 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1446 1447 drift = HDMI_READ(HDMI_FIFO_CTL); 1448 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1449 1450 HDMI_WRITE(HDMI_FIFO_CTL, 1451 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1452 HDMI_WRITE(HDMI_FIFO_CTL, 1453 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1454 1455 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1456 1457 usleep_range(1000, 1100); 1458 1459 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1460 1461 HDMI_WRITE(HDMI_FIFO_CTL, 1462 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1463 HDMI_WRITE(HDMI_FIFO_CTL, 1464 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1465 1466 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1467 1468 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1469 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1470 WARN_ONCE(ret, "Timeout waiting for " 1471 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1472 1473 drm_dev_exit(idx); 1474 } 1475 1476 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1477 struct drm_atomic_state *state) 1478 { 1479 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1480 struct drm_device *drm = vc4_hdmi->connector.dev; 1481 struct drm_connector *connector = &vc4_hdmi->connector; 1482 struct drm_connector_state *conn_state = 1483 drm_atomic_get_new_connector_state(state, connector); 1484 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1485 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate; 1486 unsigned long bvb_rate, hsm_rate; 1487 unsigned long flags; 1488 int ret; 1489 int idx; 1490 1491 mutex_lock(&vc4_hdmi->mutex); 1492 1493 if (!drm_dev_enter(drm, &idx)) 1494 goto out; 1495 1496 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1497 if (ret < 0) { 1498 drm_err(drm, "Failed to retain power domain: %d\n", ret); 1499 goto err_dev_exit; 1500 } 1501 1502 /* 1503 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1504 * be faster than pixel clock, infinitesimally faster, tested in 1505 * simulation. Otherwise, exact value is unimportant for HDMI 1506 * operation." This conflicts with bcm2835's vc4 documentation, which 1507 * states HSM's clock has to be at least 108% of the pixel clock. 1508 * 1509 * Real life tests reveal that vc4's firmware statement holds up, and 1510 * users are able to use pixel clocks closer to HSM's, namely for 1511 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1512 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1513 * 162MHz. 1514 * 1515 * Additionally, the AXI clock needs to be at least 25% of 1516 * pixel clock, but HSM ends up being the limiting factor. 1517 */ 1518 hsm_rate = max_t(unsigned long, 1519 HSM_MIN_CLOCK_FREQ, 1520 div_u64(tmds_char_rate, 100) * 101); 1521 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1522 if (ret) { 1523 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret); 1524 goto err_put_runtime_pm; 1525 } 1526 1527 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1528 if (ret) { 1529 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret); 1530 goto err_put_runtime_pm; 1531 } 1532 1533 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1534 if (ret) { 1535 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret); 1536 goto err_put_runtime_pm; 1537 } 1538 1539 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1540 1541 if (tmds_char_rate > 297000000) 1542 bvb_rate = 300000000; 1543 else if (tmds_char_rate > 148500000) 1544 bvb_rate = 150000000; 1545 else 1546 bvb_rate = 75000000; 1547 1548 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1549 if (ret) { 1550 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret); 1551 goto err_disable_pixel_clock; 1552 } 1553 1554 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1555 if (ret) { 1556 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret); 1557 goto err_disable_pixel_clock; 1558 } 1559 1560 if (vc4_hdmi->variant->phy_init) 1561 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state); 1562 1563 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1564 1565 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1566 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1567 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1568 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1569 1570 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1571 1572 if (vc4_hdmi->variant->set_timings) 1573 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1574 1575 drm_dev_exit(idx); 1576 1577 mutex_unlock(&vc4_hdmi->mutex); 1578 1579 return; 1580 1581 err_disable_pixel_clock: 1582 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1583 err_put_runtime_pm: 1584 pm_runtime_put(&vc4_hdmi->pdev->dev); 1585 err_dev_exit: 1586 drm_dev_exit(idx); 1587 out: 1588 mutex_unlock(&vc4_hdmi->mutex); 1589 return; 1590 } 1591 1592 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1593 struct drm_atomic_state *state) 1594 { 1595 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1596 struct drm_device *drm = vc4_hdmi->connector.dev; 1597 struct drm_connector *connector = &vc4_hdmi->connector; 1598 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1599 struct drm_connector_state *conn_state = 1600 drm_atomic_get_new_connector_state(state, connector); 1601 unsigned long flags; 1602 int idx; 1603 1604 mutex_lock(&vc4_hdmi->mutex); 1605 1606 if (!drm_dev_enter(drm, &idx)) 1607 goto out; 1608 1609 if (vc4_hdmi->variant->csc_setup) 1610 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1611 1612 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1613 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1614 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1615 1616 drm_dev_exit(idx); 1617 1618 out: 1619 mutex_unlock(&vc4_hdmi->mutex); 1620 } 1621 1622 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1623 struct drm_atomic_state *state) 1624 { 1625 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1626 struct drm_connector *connector = &vc4_hdmi->connector; 1627 struct drm_device *drm = connector->dev; 1628 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1629 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1630 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1631 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1632 unsigned long flags; 1633 int ret; 1634 int idx; 1635 1636 mutex_lock(&vc4_hdmi->mutex); 1637 1638 if (!drm_dev_enter(drm, &idx)) 1639 goto out; 1640 1641 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1642 1643 HDMI_WRITE(HDMI_VID_CTL, 1644 (HDMI_READ(HDMI_VID_CTL) & 1645 ~(VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) | 1646 VC4_HD_VID_CTL_ENABLE | 1647 VC4_HD_VID_CTL_CLRRGB | 1648 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1649 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1650 VC4_HD_VID_CTL_BLANK_INSERT_EN | 1651 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1652 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1653 1654 HDMI_WRITE(HDMI_VID_CTL, 1655 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1656 1657 if (display->is_hdmi) { 1658 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1659 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1660 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1661 1662 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1663 1664 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1665 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1666 WARN_ONCE(ret, "Timeout waiting for " 1667 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1668 } else { 1669 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1670 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1671 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1672 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1673 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1674 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1675 1676 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1677 1678 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1679 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1680 WARN_ONCE(ret, "Timeout waiting for " 1681 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1682 } 1683 1684 if (display->is_hdmi) { 1685 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1686 1687 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1688 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1689 1690 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1691 VC4_HDMI_RAM_PACKET_ENABLE); 1692 1693 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1694 vc4_hdmi->packet_ram_enabled = true; 1695 1696 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 1697 } 1698 1699 vc4_hdmi_recenter_fifo(vc4_hdmi); 1700 vc4_hdmi_enable_scrambling(encoder); 1701 1702 drm_dev_exit(idx); 1703 1704 out: 1705 mutex_unlock(&vc4_hdmi->mutex); 1706 } 1707 1708 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1709 struct drm_crtc_state *crtc_state, 1710 struct drm_connector_state *conn_state) 1711 { 1712 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1713 1714 mutex_lock(&vc4_hdmi->mutex); 1715 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1716 &crtc_state->adjusted_mode); 1717 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc; 1718 vc4_hdmi->output_format = conn_state->hdmi.output_format; 1719 mutex_unlock(&vc4_hdmi->mutex); 1720 } 1721 1722 static enum drm_mode_status 1723 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector, 1724 const struct drm_display_mode *mode, 1725 unsigned long long clock) 1726 { 1727 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1728 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 1729 1730 if (clock > vc4_hdmi->variant->max_pixel_clock) 1731 return MODE_CLOCK_HIGH; 1732 1733 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 1734 return MODE_CLOCK_HIGH; 1735 1736 /* 4096x2160@60 is not reliable without overclocking core */ 1737 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 1738 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 1739 drm_mode_vrefresh(mode) >= 50) 1740 return MODE_CLOCK_HIGH; 1741 1742 return MODE_OK; 1743 } 1744 1745 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = { 1746 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid, 1747 .avi = { 1748 .clear_infoframe = vc4_hdmi_clear_avi_infoframe, 1749 .write_infoframe = vc4_hdmi_write_avi_infoframe, 1750 }, 1751 .hdmi = { 1752 .clear_infoframe = vc4_hdmi_clear_hdmi_infoframe, 1753 .write_infoframe = vc4_hdmi_write_hdmi_infoframe, 1754 }, 1755 .audio = { 1756 .clear_infoframe = vc4_hdmi_clear_audio_infoframe, 1757 .write_infoframe = vc4_hdmi_write_audio_infoframe, 1758 }, 1759 .hdr_drm = { 1760 .clear_infoframe = vc4_hdmi_clear_hdr_drm_infoframe, 1761 .write_infoframe = vc4_hdmi_write_hdr_drm_infoframe, 1762 }, 1763 .spd = { 1764 .clear_infoframe = vc4_hdmi_clear_spd_infoframe, 1765 .write_infoframe = vc4_hdmi_write_spd_infoframe, 1766 }, 1767 }; 1768 1769 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1770 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1771 1772 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1773 struct drm_crtc_state *crtc_state, 1774 struct drm_connector_state *conn_state) 1775 { 1776 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1777 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1778 unsigned long long tmds_char_rate = mode->clock * 1000; 1779 unsigned long long tmds_bit_rate; 1780 1781 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1782 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1783 /* Only try to fixup DBLCLK modes to get 480i and 576i 1784 * working. 1785 * A generic solution for all modes with odd horizontal 1786 * timing values seems impossible based on trying to 1787 * solve it for 1366x768 monitors. 1788 */ 1789 if ((mode->hsync_start - mode->hdisplay) & 1) 1790 mode->hsync_start--; 1791 if ((mode->hsync_end - mode->hsync_start) & 1) 1792 mode->hsync_end--; 1793 } 1794 1795 /* Now check whether we still have odd values remaining */ 1796 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1797 (mode->hsync_end % 2) || (mode->htotal % 2)) 1798 return -EINVAL; 1799 } 1800 1801 /* 1802 * The 1440p@60 pixel rate is in the same range than the first 1803 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1804 * bandwidth). Slightly lower the frequency to bring it out of 1805 * the WiFi range. 1806 */ 1807 tmds_bit_rate = tmds_char_rate * 10; 1808 if (vc4_hdmi->disable_wifi_frequencies && 1809 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1810 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1811 mode->clock = 238560; 1812 tmds_char_rate = mode->clock * 1000; 1813 } 1814 1815 return 0; 1816 } 1817 1818 static enum drm_mode_status 1819 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1820 const struct drm_display_mode *mode) 1821 { 1822 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1823 1824 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1825 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1826 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1827 (mode->hsync_end % 2) || (mode->htotal % 2))) 1828 return MODE_H_ILLEGAL; 1829 1830 return MODE_OK; 1831 } 1832 1833 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1834 .atomic_check = vc4_hdmi_encoder_atomic_check, 1835 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1836 .mode_valid = vc4_hdmi_encoder_mode_valid, 1837 }; 1838 1839 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 1840 { 1841 struct drm_device *drm = encoder->dev; 1842 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1843 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1844 1845 drm_debugfs_add_file(drm, variant->debugfs_name, 1846 vc4_hdmi_debugfs_regs, vc4_hdmi); 1847 1848 return 0; 1849 } 1850 1851 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 1852 .late_register = vc4_hdmi_late_register, 1853 }; 1854 1855 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1856 { 1857 int i; 1858 u32 channel_map = 0; 1859 1860 for (i = 0; i < 8; i++) { 1861 if (channel_mask & BIT(i)) 1862 channel_map |= i << (3 * i); 1863 } 1864 return channel_map; 1865 } 1866 1867 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1868 { 1869 int i; 1870 u32 channel_map = 0; 1871 1872 for (i = 0; i < 8; i++) { 1873 if (channel_mask & BIT(i)) 1874 channel_map |= i << (4 * i); 1875 } 1876 return channel_map; 1877 } 1878 1879 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1880 { 1881 struct drm_device *drm = vc4_hdmi->connector.dev; 1882 unsigned long flags; 1883 u32 hotplug; 1884 int idx; 1885 1886 if (!drm_dev_enter(drm, &idx)) 1887 return false; 1888 1889 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1890 hotplug = HDMI_READ(HDMI_HOTPLUG); 1891 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1892 1893 drm_dev_exit(idx); 1894 1895 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1896 } 1897 1898 /* HDMI audio codec callbacks */ 1899 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1900 unsigned int samplerate) 1901 { 1902 struct drm_device *drm = vc4_hdmi->connector.dev; 1903 u32 hsm_clock; 1904 unsigned long flags; 1905 unsigned long n, m; 1906 int idx; 1907 1908 if (!drm_dev_enter(drm, &idx)) 1909 return; 1910 1911 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1912 rational_best_approximation(hsm_clock, samplerate, 1913 VC4_HD_MAI_SMP_N_MASK >> 1914 VC4_HD_MAI_SMP_N_SHIFT, 1915 (VC4_HD_MAI_SMP_M_MASK >> 1916 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1917 &n, &m); 1918 1919 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1920 HDMI_WRITE(HDMI_MAI_SMP, 1921 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1922 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1923 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1924 1925 drm_dev_exit(idx); 1926 } 1927 1928 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1929 { 1930 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1931 u32 n, cts; 1932 u64 tmp; 1933 1934 lockdep_assert_held(&vc4_hdmi->mutex); 1935 lockdep_assert_held(&vc4_hdmi->hw_lock); 1936 1937 n = 128 * samplerate / 1000; 1938 tmp = (u64)(mode->clock * 1000) * n; 1939 do_div(tmp, 128 * samplerate); 1940 cts = tmp; 1941 1942 HDMI_WRITE(HDMI_CRP_CFG, 1943 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1944 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1945 1946 /* 1947 * We could get slightly more accurate clocks in some cases by 1948 * providing a CTS_1 value. The two CTS values are alternated 1949 * between based on the period fields 1950 */ 1951 HDMI_WRITE(HDMI_CTS_0, cts); 1952 HDMI_WRITE(HDMI_CTS_1, cts); 1953 } 1954 1955 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1956 { 1957 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1958 1959 return snd_soc_card_get_drvdata(card); 1960 } 1961 1962 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1963 { 1964 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1965 1966 lockdep_assert_held(&vc4_hdmi->mutex); 1967 1968 /* 1969 * If the encoder is currently in DVI mode, treat the codec DAI 1970 * as missing. 1971 */ 1972 if (!display->is_hdmi) 1973 return false; 1974 1975 return true; 1976 } 1977 1978 static int vc4_hdmi_audio_startup(struct drm_connector *connector) 1979 { 1980 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1981 struct drm_device *drm = vc4_hdmi->connector.dev; 1982 unsigned long flags; 1983 int ret = 0; 1984 int idx; 1985 1986 mutex_lock(&vc4_hdmi->mutex); 1987 1988 if (!drm_dev_enter(drm, &idx)) { 1989 ret = -ENODEV; 1990 goto out; 1991 } 1992 1993 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1994 ret = -ENOTSUPP; 1995 goto out_dev_exit; 1996 } 1997 1998 vc4_hdmi->audio.streaming = true; 1999 2000 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2001 HDMI_WRITE(HDMI_MAI_CTL, 2002 VC4_HD_MAI_CTL_RESET | 2003 VC4_HD_MAI_CTL_FLUSH | 2004 VC4_HD_MAI_CTL_DLATE | 2005 VC4_HD_MAI_CTL_ERRORE | 2006 VC4_HD_MAI_CTL_ERRORF); 2007 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2008 2009 if (vc4_hdmi->variant->phy_rng_enable) 2010 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 2011 2012 out_dev_exit: 2013 drm_dev_exit(idx); 2014 out: 2015 mutex_unlock(&vc4_hdmi->mutex); 2016 2017 return ret; 2018 } 2019 2020 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 2021 { 2022 struct device *dev = &vc4_hdmi->pdev->dev; 2023 unsigned long flags; 2024 int ret; 2025 2026 lockdep_assert_held(&vc4_hdmi->mutex); 2027 2028 vc4_hdmi->audio.streaming = false; 2029 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false); 2030 if (ret) 2031 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 2032 2033 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2034 2035 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 2036 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 2037 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 2038 2039 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2040 } 2041 2042 static void vc4_hdmi_audio_shutdown(struct drm_connector *connector) 2043 { 2044 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2045 struct drm_device *drm = vc4_hdmi->connector.dev; 2046 unsigned long flags; 2047 int idx; 2048 2049 mutex_lock(&vc4_hdmi->mutex); 2050 2051 if (!drm_dev_enter(drm, &idx)) 2052 goto out; 2053 2054 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2055 2056 HDMI_WRITE(HDMI_MAI_CTL, 2057 VC4_HD_MAI_CTL_DLATE | 2058 VC4_HD_MAI_CTL_ERRORE | 2059 VC4_HD_MAI_CTL_ERRORF); 2060 2061 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2062 2063 if (vc4_hdmi->variant->phy_rng_disable) 2064 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 2065 2066 vc4_hdmi->audio.streaming = false; 2067 vc4_hdmi_audio_reset(vc4_hdmi); 2068 2069 drm_dev_exit(idx); 2070 2071 out: 2072 mutex_unlock(&vc4_hdmi->mutex); 2073 } 2074 2075 static int sample_rate_to_mai_fmt(int samplerate) 2076 { 2077 switch (samplerate) { 2078 case 8000: 2079 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2080 case 11025: 2081 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2082 case 12000: 2083 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2084 case 16000: 2085 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2086 case 22050: 2087 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2088 case 24000: 2089 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2090 case 32000: 2091 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2092 case 44100: 2093 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2094 case 48000: 2095 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2096 case 64000: 2097 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2098 case 88200: 2099 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2100 case 96000: 2101 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2102 case 128000: 2103 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2104 case 176400: 2105 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2106 case 192000: 2107 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2108 default: 2109 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2110 } 2111 } 2112 2113 /* HDMI audio codec callbacks */ 2114 static int vc4_hdmi_audio_prepare(struct drm_connector *connector, 2115 struct hdmi_codec_daifmt *daifmt, 2116 struct hdmi_codec_params *params) 2117 { 2118 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2119 struct drm_device *drm = vc4_hdmi->connector.dev; 2120 struct vc4_dev *vc4 = to_vc4_dev(drm); 2121 unsigned int sample_rate = params->sample_rate; 2122 unsigned int channels = params->channels; 2123 unsigned long flags; 2124 u32 audio_packet_config, channel_mask; 2125 u32 channel_map; 2126 u32 mai_audio_format; 2127 u32 mai_sample_rate; 2128 int ret = 0; 2129 int idx; 2130 2131 dev_dbg(&vc4_hdmi->pdev->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2132 sample_rate, params->sample_width, channels); 2133 2134 mutex_lock(&vc4_hdmi->mutex); 2135 2136 if (!drm_dev_enter(drm, &idx)) { 2137 ret = -ENODEV; 2138 goto out; 2139 } 2140 2141 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2142 ret = -EINVAL; 2143 goto out_dev_exit; 2144 } 2145 2146 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2147 2148 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2149 HDMI_WRITE(HDMI_MAI_CTL, 2150 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2151 VC4_HD_MAI_CTL_WHOLSMP | 2152 VC4_HD_MAI_CTL_CHALIGN | 2153 VC4_HD_MAI_CTL_ENABLE); 2154 2155 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2156 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2157 params->channels == 8) 2158 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2159 else 2160 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2161 HDMI_WRITE(HDMI_MAI_FMT, 2162 VC4_SET_FIELD(mai_sample_rate, 2163 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2164 VC4_SET_FIELD(mai_audio_format, 2165 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2166 2167 /* The B frame identifier should match the value used by alsa-lib (8) */ 2168 audio_packet_config = 2169 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2170 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2171 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2172 2173 channel_mask = GENMASK(channels - 1, 0); 2174 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2175 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2176 2177 /* Set the MAI threshold */ 2178 switch (vc4->gen) { 2179 case VC4_GEN_6_D: 2180 HDMI_WRITE(HDMI_MAI_THR, 2181 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) | 2182 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) | 2183 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) | 2184 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW)); 2185 break; 2186 case VC4_GEN_6_C: 2187 case VC4_GEN_5: 2188 HDMI_WRITE(HDMI_MAI_THR, 2189 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 2190 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 2191 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) | 2192 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW)); 2193 break; 2194 case VC4_GEN_4: 2195 HDMI_WRITE(HDMI_MAI_THR, 2196 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) | 2197 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) | 2198 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) | 2199 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW)); 2200 break; 2201 default: 2202 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen); 2203 break; 2204 } 2205 2206 HDMI_WRITE(HDMI_MAI_CONFIG, 2207 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2208 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2209 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2210 2211 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2212 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2213 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2214 2215 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2216 2217 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2218 2219 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, 2220 ¶ms->cea); 2221 if (ret) 2222 goto out_dev_exit; 2223 2224 out_dev_exit: 2225 drm_dev_exit(idx); 2226 out: 2227 mutex_unlock(&vc4_hdmi->mutex); 2228 2229 return ret; 2230 } 2231 2232 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2233 .name = "vc4-hdmi-cpu-dai-component", 2234 .legacy_dai_naming = 1, 2235 }; 2236 2237 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2238 { 2239 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2240 2241 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2242 2243 return 0; 2244 } 2245 2246 static const struct snd_soc_dai_ops vc4_snd_dai_ops = { 2247 .probe = vc4_hdmi_audio_cpu_dai_probe, 2248 }; 2249 2250 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2251 .name = "vc4-hdmi-cpu-dai", 2252 .ops = &vc4_snd_dai_ops, 2253 .playback = { 2254 .stream_name = "Playback", 2255 .channels_min = 1, 2256 .channels_max = 8, 2257 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2258 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2259 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2260 SNDRV_PCM_RATE_192000, 2261 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2262 }, 2263 }; 2264 2265 static const struct snd_dmaengine_pcm_config pcm_conf = { 2266 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2267 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2268 }; 2269 2270 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs = { 2271 .startup = vc4_hdmi_audio_startup, 2272 .prepare = vc4_hdmi_audio_prepare, 2273 .shutdown = vc4_hdmi_audio_shutdown, 2274 }; 2275 2276 static int vc4_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd) 2277 { 2278 struct vc4_hdmi *vc4_hdmi = snd_soc_card_get_drvdata(rtd->card); 2279 struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component; 2280 int ret; 2281 2282 ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT, 2283 &vc4_hdmi->hdmi_jack); 2284 if (ret) { 2285 dev_err(rtd->dev, "HDMI Jack creation failed: %d\n", ret); 2286 return ret; 2287 } 2288 2289 return snd_soc_component_set_jack(component, &vc4_hdmi->hdmi_jack, NULL); 2290 } 2291 2292 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2293 { 2294 const struct vc4_hdmi_register *mai_data = 2295 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2296 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2297 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2298 struct device *dev = &vc4_hdmi->pdev->dev; 2299 const __be32 *addr; 2300 int index, len; 2301 int ret; 2302 2303 /* 2304 * ASoC makes it a bit hard to retrieve a pointer to the 2305 * vc4_hdmi structure. Registering the card will overwrite our 2306 * device drvdata with a pointer to the snd_soc_card structure, 2307 * which can then be used to retrieve whatever drvdata we want 2308 * to associate. 2309 * 2310 * However, that doesn't fly in the case where we wouldn't 2311 * register an ASoC card (because of an old DT that is missing 2312 * the dmas properties for example), then the card isn't 2313 * registered and the device drvdata wouldn't be set. 2314 * 2315 * We can deal with both cases by making sure a snd_soc_card 2316 * pointer and a vc4_hdmi structure are pointing to the same 2317 * memory address, so we can treat them indistinctly without any 2318 * issue. 2319 */ 2320 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2321 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2322 2323 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2324 dev_warn(dev, 2325 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2326 return 0; 2327 } 2328 2329 if (mai_data->reg != VC4_HD) { 2330 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2331 return -EINVAL; 2332 } 2333 2334 /* 2335 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2336 * the bus address specified in the DT, because the physical address 2337 * (the one returned by platform_get_resource()) is not appropriate 2338 * for DMA transfers. 2339 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2340 */ 2341 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2342 /* Before BCM2711, we don't have a named register range */ 2343 if (index < 0) 2344 index = 1; 2345 2346 addr = of_get_address(dev->of_node, index, NULL, NULL); 2347 if (!addr) 2348 return -EINVAL; 2349 2350 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2351 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2352 vc4_hdmi->audio.dma_data.maxburst = 2; 2353 2354 /* 2355 * NOTE: Strictly speaking, we should probably use a DRM-managed 2356 * registration there to avoid removing all the audio components 2357 * by the time the driver doesn't have any user anymore. 2358 * 2359 * However, the ASoC core uses a number of devm_kzalloc calls 2360 * when registering, even when using non-device-managed 2361 * functions (such as in snd_soc_register_component()). 2362 * 2363 * If we call snd_soc_unregister_component() in a DRM-managed 2364 * action, the device-managed actions have already been executed 2365 * and thus we would access memory that has been freed. 2366 * 2367 * Using device-managed hooks here probably leaves us open to a 2368 * bunch of issues if userspace still has a handle on the ALSA 2369 * device when the device is removed. However, this is mitigated 2370 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2371 * path to prevent the access to the device resources if it 2372 * isn't there anymore. 2373 * 2374 * Then, the vc4_hdmi structure is DRM-managed and thus only 2375 * freed whenever the last user has closed the DRM device file. 2376 * It should thus outlive ALSA in most situations. 2377 */ 2378 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2379 if (ret) { 2380 dev_err(dev, "Could not register PCM component: %d\n", ret); 2381 return ret; 2382 } 2383 2384 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2385 &vc4_hdmi_audio_cpu_dai_drv, 1); 2386 if (ret) { 2387 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2388 return ret; 2389 } 2390 2391 ret = drm_connector_hdmi_audio_init(&vc4_hdmi->connector, dev, 2392 &vc4_hdmi_audio_funcs, 8, 0, false, 2393 -1); 2394 if (ret) 2395 return ret; 2396 2397 dai_link->cpus = &vc4_hdmi->audio.cpu; 2398 dai_link->codecs = &vc4_hdmi->audio.codec; 2399 dai_link->platforms = &vc4_hdmi->audio.platform; 2400 2401 dai_link->num_cpus = 1; 2402 dai_link->num_codecs = 1; 2403 dai_link->num_platforms = 1; 2404 2405 dai_link->name = "MAI"; 2406 dai_link->stream_name = "MAI PCM"; 2407 dai_link->codecs->dai_name = "i2s-hifi"; 2408 dai_link->cpus->dai_name = dev_name(dev); 2409 dai_link->codecs->name = dev_name(&vc4_hdmi->connector.hdmi_audio.codec_pdev->dev); 2410 dai_link->platforms->name = dev_name(dev); 2411 dai_link->init = vc4_hdmi_codec_init; 2412 2413 card->dai_link = dai_link; 2414 card->num_links = 1; 2415 card->name = vc4_hdmi->variant->card_name; 2416 card->driver_name = "vc4-hdmi"; 2417 card->dev = dev; 2418 card->owner = THIS_MODULE; 2419 2420 /* 2421 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2422 * stores a pointer to the snd card object in dev->driver_data. This 2423 * means we cannot use it for something else. The hdmi back-pointer is 2424 * now stored in card->drvdata and should be retrieved with 2425 * snd_soc_card_get_drvdata() if needed. 2426 */ 2427 snd_soc_card_set_drvdata(card, vc4_hdmi); 2428 ret = devm_snd_soc_register_card(dev, card); 2429 if (ret) 2430 dev_err_probe(dev, ret, "Could not register sound card\n"); 2431 2432 return ret; 2433 2434 } 2435 2436 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2437 { 2438 struct vc4_hdmi *vc4_hdmi = priv; 2439 struct drm_connector *connector = &vc4_hdmi->connector; 2440 struct drm_device *dev = connector->dev; 2441 2442 if (dev && dev->registered) 2443 drm_connector_helper_hpd_irq_event(connector); 2444 2445 return IRQ_HANDLED; 2446 } 2447 2448 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2449 { 2450 struct drm_connector *connector = &vc4_hdmi->connector; 2451 struct platform_device *pdev = vc4_hdmi->pdev; 2452 int ret; 2453 2454 if (vc4_hdmi->variant->external_irq_controller) { 2455 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2456 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2457 2458 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2459 NULL, 2460 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2461 "vc4 hdmi hpd connected", vc4_hdmi); 2462 if (ret) 2463 return ret; 2464 2465 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2466 NULL, 2467 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2468 "vc4 hdmi hpd disconnected", vc4_hdmi); 2469 if (ret) 2470 return ret; 2471 2472 connector->polled = DRM_CONNECTOR_POLL_HPD; 2473 } 2474 2475 return 0; 2476 } 2477 2478 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2479 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2480 { 2481 struct vc4_hdmi *vc4_hdmi = priv; 2482 2483 if (vc4_hdmi->cec_rx_msg.len) 2484 drm_connector_hdmi_cec_received_msg(&vc4_hdmi->connector, 2485 &vc4_hdmi->cec_rx_msg); 2486 2487 return IRQ_HANDLED; 2488 } 2489 2490 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2491 { 2492 struct vc4_hdmi *vc4_hdmi = priv; 2493 2494 if (vc4_hdmi->cec_tx_ok) { 2495 drm_connector_hdmi_cec_transmit_done(&vc4_hdmi->connector, 2496 CEC_TX_STATUS_OK, 2497 0, 0, 0, 0); 2498 } else { 2499 /* 2500 * This CEC implementation makes 1 retry, so if we 2501 * get a NACK, then that means it made 2 attempts. 2502 */ 2503 drm_connector_hdmi_cec_transmit_done(&vc4_hdmi->connector, 2504 CEC_TX_STATUS_NACK, 2505 0, 2, 0, 0); 2506 } 2507 return IRQ_HANDLED; 2508 } 2509 2510 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2511 { 2512 struct vc4_hdmi *vc4_hdmi = priv; 2513 irqreturn_t ret; 2514 2515 if (vc4_hdmi->cec_irq_was_rx) 2516 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2517 else 2518 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2519 2520 return ret; 2521 } 2522 2523 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2524 { 2525 struct drm_device *dev = vc4_hdmi->connector.dev; 2526 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2527 unsigned int i; 2528 2529 lockdep_assert_held(&vc4_hdmi->hw_lock); 2530 2531 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2532 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2533 2534 if (msg->len > 16) { 2535 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2536 return; 2537 } 2538 2539 for (i = 0; i < msg->len; i += 4) { 2540 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2541 2542 msg->msg[i] = val & 0xff; 2543 msg->msg[i + 1] = (val >> 8) & 0xff; 2544 msg->msg[i + 2] = (val >> 16) & 0xff; 2545 msg->msg[i + 3] = (val >> 24) & 0xff; 2546 } 2547 } 2548 2549 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2550 { 2551 u32 cntrl1; 2552 2553 /* 2554 * We don't need to protect the register access using 2555 * drm_dev_enter() there because the interrupt handler lifetime 2556 * is tied to the device itself, and not to the DRM device. 2557 * 2558 * So when the device will be gone, one of the first thing we 2559 * will be doing will be to unregister the interrupt handler, 2560 * and then unregister the DRM device. drm_dev_enter() would 2561 * thus always succeed if we are here. 2562 */ 2563 2564 lockdep_assert_held(&vc4_hdmi->hw_lock); 2565 2566 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2567 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2568 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2569 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2570 2571 return IRQ_WAKE_THREAD; 2572 } 2573 2574 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2575 { 2576 struct vc4_hdmi *vc4_hdmi = priv; 2577 irqreturn_t ret; 2578 2579 spin_lock(&vc4_hdmi->hw_lock); 2580 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2581 spin_unlock(&vc4_hdmi->hw_lock); 2582 2583 return ret; 2584 } 2585 2586 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2587 { 2588 u32 cntrl1; 2589 2590 lockdep_assert_held(&vc4_hdmi->hw_lock); 2591 2592 /* 2593 * We don't need to protect the register access using 2594 * drm_dev_enter() there because the interrupt handler lifetime 2595 * is tied to the device itself, and not to the DRM device. 2596 * 2597 * So when the device will be gone, one of the first thing we 2598 * will be doing will be to unregister the interrupt handler, 2599 * and then unregister the DRM device. drm_dev_enter() would 2600 * thus always succeed if we are here. 2601 */ 2602 2603 vc4_hdmi->cec_rx_msg.len = 0; 2604 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2605 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2606 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2607 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2608 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2609 2610 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2611 2612 return IRQ_WAKE_THREAD; 2613 } 2614 2615 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2616 { 2617 struct vc4_hdmi *vc4_hdmi = priv; 2618 irqreturn_t ret; 2619 2620 spin_lock(&vc4_hdmi->hw_lock); 2621 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2622 spin_unlock(&vc4_hdmi->hw_lock); 2623 2624 return ret; 2625 } 2626 2627 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2628 { 2629 struct vc4_hdmi *vc4_hdmi = priv; 2630 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2631 irqreturn_t ret; 2632 u32 cntrl5; 2633 2634 /* 2635 * We don't need to protect the register access using 2636 * drm_dev_enter() there because the interrupt handler lifetime 2637 * is tied to the device itself, and not to the DRM device. 2638 * 2639 * So when the device will be gone, one of the first thing we 2640 * will be doing will be to unregister the interrupt handler, 2641 * and then unregister the DRM device. drm_dev_enter() would 2642 * thus always succeed if we are here. 2643 */ 2644 2645 if (!(stat & VC4_HDMI_CPU_CEC)) 2646 return IRQ_NONE; 2647 2648 spin_lock(&vc4_hdmi->hw_lock); 2649 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2650 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2651 if (vc4_hdmi->cec_irq_was_rx) 2652 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2653 else 2654 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2655 2656 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2657 spin_unlock(&vc4_hdmi->hw_lock); 2658 2659 return ret; 2660 } 2661 2662 static int vc4_hdmi_cec_enable(struct drm_connector *connector) 2663 { 2664 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2665 struct drm_device *drm = vc4_hdmi->connector.dev; 2666 /* clock period in microseconds */ 2667 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2668 unsigned long flags; 2669 u32 val; 2670 int ret; 2671 int idx; 2672 2673 if (!drm_dev_enter(drm, &idx)) 2674 /* 2675 * We can't return an error code, because the CEC 2676 * framework will emit WARN_ON messages at unbind 2677 * otherwise. 2678 */ 2679 return 0; 2680 2681 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2682 if (ret) { 2683 drm_dev_exit(idx); 2684 return ret; 2685 } 2686 2687 mutex_lock(&vc4_hdmi->mutex); 2688 2689 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2690 2691 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2692 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2693 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2694 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2695 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2696 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2697 2698 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2699 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2700 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2701 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2702 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2703 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2704 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2705 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2706 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2707 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2708 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2709 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2710 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2711 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2712 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2713 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2714 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2715 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2716 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2717 2718 if (!vc4_hdmi->variant->external_irq_controller) 2719 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2720 2721 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2722 2723 mutex_unlock(&vc4_hdmi->mutex); 2724 drm_dev_exit(idx); 2725 2726 return 0; 2727 } 2728 2729 static int vc4_hdmi_cec_disable(struct drm_connector *connector) 2730 { 2731 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2732 struct drm_device *drm = vc4_hdmi->connector.dev; 2733 unsigned long flags; 2734 int idx; 2735 2736 if (!drm_dev_enter(drm, &idx)) 2737 /* 2738 * We can't return an error code, because the CEC 2739 * framework will emit WARN_ON messages at unbind 2740 * otherwise. 2741 */ 2742 return 0; 2743 2744 mutex_lock(&vc4_hdmi->mutex); 2745 2746 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2747 2748 if (!vc4_hdmi->variant->external_irq_controller) 2749 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2750 2751 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2752 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2753 2754 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2755 2756 mutex_unlock(&vc4_hdmi->mutex); 2757 2758 pm_runtime_put(&vc4_hdmi->pdev->dev); 2759 2760 drm_dev_exit(idx); 2761 2762 return 0; 2763 } 2764 2765 static int vc4_hdmi_cec_adap_enable(struct drm_connector *connector, bool enable) 2766 { 2767 if (enable) 2768 return vc4_hdmi_cec_enable(connector); 2769 else 2770 return vc4_hdmi_cec_disable(connector); 2771 } 2772 2773 static int vc4_hdmi_cec_adap_log_addr(struct drm_connector *connector, u8 log_addr) 2774 { 2775 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2776 struct drm_device *drm = vc4_hdmi->connector.dev; 2777 unsigned long flags; 2778 int idx; 2779 2780 if (!drm_dev_enter(drm, &idx)) 2781 /* 2782 * We can't return an error code, because the CEC 2783 * framework will emit WARN_ON messages at unbind 2784 * otherwise. 2785 */ 2786 return 0; 2787 2788 mutex_lock(&vc4_hdmi->mutex); 2789 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2790 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2791 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2792 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2793 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2794 mutex_unlock(&vc4_hdmi->mutex); 2795 2796 drm_dev_exit(idx); 2797 2798 return 0; 2799 } 2800 2801 static int vc4_hdmi_cec_adap_transmit(struct drm_connector *connector, u8 attempts, 2802 u32 signal_free_time, struct cec_msg *msg) 2803 { 2804 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2805 struct drm_device *dev = vc4_hdmi->connector.dev; 2806 unsigned long flags; 2807 u32 val; 2808 unsigned int i; 2809 int idx; 2810 2811 if (!drm_dev_enter(dev, &idx)) 2812 return -ENODEV; 2813 2814 if (msg->len > 16) { 2815 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2816 drm_dev_exit(idx); 2817 return -ENOMEM; 2818 } 2819 2820 mutex_lock(&vc4_hdmi->mutex); 2821 2822 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2823 2824 for (i = 0; i < msg->len; i += 4) 2825 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2826 (msg->msg[i]) | 2827 (msg->msg[i + 1] << 8) | 2828 (msg->msg[i + 2] << 16) | 2829 (msg->msg[i + 3] << 24)); 2830 2831 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2832 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2833 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2834 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2835 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2836 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2837 2838 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2839 2840 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2841 mutex_unlock(&vc4_hdmi->mutex); 2842 drm_dev_exit(idx); 2843 2844 return 0; 2845 } 2846 2847 static int vc4_hdmi_cec_init(struct drm_connector *connector) 2848 { 2849 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2850 struct platform_device *pdev = vc4_hdmi->pdev; 2851 struct device *dev = &pdev->dev; 2852 int ret; 2853 2854 if (vc4_hdmi->variant->external_irq_controller) { 2855 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 2856 vc4_cec_irq_handler_rx_bare, 2857 vc4_cec_irq_handler_rx_thread, 0, 2858 "vc4 hdmi cec rx", vc4_hdmi); 2859 if (ret) 2860 return ret; 2861 2862 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 2863 vc4_cec_irq_handler_tx_bare, 2864 vc4_cec_irq_handler_tx_thread, 0, 2865 "vc4 hdmi cec tx", vc4_hdmi); 2866 if (ret) 2867 return ret; 2868 } else { 2869 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 2870 vc4_cec_irq_handler, 2871 vc4_cec_irq_handler_thread, 0, 2872 "vc4 hdmi cec", vc4_hdmi); 2873 if (ret) 2874 return ret; 2875 } 2876 2877 return 0; 2878 } 2879 2880 static const struct drm_connector_hdmi_cec_funcs vc4_hdmi_cec_funcs = { 2881 .init = vc4_hdmi_cec_init, 2882 .enable = vc4_hdmi_cec_adap_enable, 2883 .log_addr = vc4_hdmi_cec_adap_log_addr, 2884 .transmit = vc4_hdmi_cec_adap_transmit, 2885 }; 2886 2887 static int vc4_hdmi_cec_register(struct vc4_hdmi *vc4_hdmi) 2888 { 2889 struct platform_device *pdev = vc4_hdmi->pdev; 2890 struct device *dev = &pdev->dev; 2891 2892 if (!of_property_present(dev->of_node, "interrupts")) { 2893 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2894 return 0; 2895 } 2896 2897 /* 2898 * NOTE: the CEC adapter will be unregistered by drmm cleanup from 2899 * drm_managed_release(), which is called from drm_dev_release() 2900 * during device unbind. 2901 * 2902 * However, the CEC framework already cleans up the CEC adapter 2903 * only when the last user has closed its file descriptor, so we 2904 * don't need to handle it in DRM. 2905 * 2906 * There's still a problematic sequence: if we unregister our 2907 * CEC adapter, but the userspace keeps a handle on the CEC 2908 * adapter but not the DRM device for some reason. In such a 2909 * case, our vc4_hdmi structure will be freed, but the 2910 * cec_adapter structure will have a dangling pointer to what 2911 * used to be our HDMI controller. If we get a CEC call at that 2912 * moment, we could end up with a use-after-free. Fortunately, 2913 * the CEC framework already handles this too, by calling 2914 * cec_is_registered() in cec_ioctl() and cec_poll(). 2915 */ 2916 return drmm_connector_hdmi_cec_register(&vc4_hdmi->connector, 2917 &vc4_hdmi_cec_funcs, 2918 vc4_hdmi->variant->card_name, 2919 1, 2920 &pdev->dev); 2921 } 2922 #else 2923 static int vc4_hdmi_cec_register(struct vc4_hdmi *vc4_hdmi) 2924 { 2925 return 0; 2926 } 2927 #endif 2928 2929 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 2930 { 2931 struct debugfs_reg32 *regs = ptr; 2932 2933 kfree(regs); 2934 } 2935 2936 static int vc4_hdmi_build_regset(struct drm_device *drm, 2937 struct vc4_hdmi *vc4_hdmi, 2938 struct debugfs_regset32 *regset, 2939 enum vc4_hdmi_regs reg) 2940 { 2941 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2942 struct debugfs_reg32 *regs, *new_regs; 2943 unsigned int count = 0; 2944 unsigned int i; 2945 int ret; 2946 2947 regs = kcalloc(variant->num_registers, sizeof(*regs), 2948 GFP_KERNEL); 2949 if (!regs) 2950 return -ENOMEM; 2951 2952 for (i = 0; i < variant->num_registers; i++) { 2953 const struct vc4_hdmi_register *field = &variant->registers[i]; 2954 2955 if (field->reg != reg) 2956 continue; 2957 2958 regs[count].name = field->name; 2959 regs[count].offset = field->offset; 2960 count++; 2961 } 2962 2963 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2964 if (!new_regs) 2965 return -ENOMEM; 2966 2967 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2968 regset->regs = new_regs; 2969 regset->nregs = count; 2970 2971 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 2972 if (ret) 2973 return ret; 2974 2975 return 0; 2976 } 2977 2978 static int vc4_hdmi_init_resources(struct drm_device *drm, 2979 struct vc4_hdmi *vc4_hdmi) 2980 { 2981 struct platform_device *pdev = vc4_hdmi->pdev; 2982 struct device *dev = &pdev->dev; 2983 int ret; 2984 2985 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2986 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2987 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2988 2989 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2990 if (IS_ERR(vc4_hdmi->hd_regs)) 2991 return PTR_ERR(vc4_hdmi->hd_regs); 2992 2993 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2994 if (ret) 2995 return ret; 2996 2997 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2998 if (ret) 2999 return ret; 3000 3001 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 3002 if (IS_ERR(vc4_hdmi->pixel_clock)) { 3003 ret = PTR_ERR(vc4_hdmi->pixel_clock); 3004 if (ret != -EPROBE_DEFER) 3005 drm_err(drm, "Failed to get pixel clock\n"); 3006 return ret; 3007 } 3008 3009 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3010 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3011 drm_err(drm, "Failed to get HDMI state machine clock\n"); 3012 return PTR_ERR(vc4_hdmi->hsm_clock); 3013 } 3014 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 3015 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 3016 3017 return 0; 3018 } 3019 3020 static int vc5_hdmi_init_resources(struct drm_device *drm, 3021 struct vc4_hdmi *vc4_hdmi) 3022 { 3023 struct platform_device *pdev = vc4_hdmi->pdev; 3024 struct device *dev = &pdev->dev; 3025 struct resource *res; 3026 int ret; 3027 3028 vc4_hdmi->hdmicore_regs = devm_platform_ioremap_resource_byname(pdev, 3029 "hdmi"); 3030 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 3031 return PTR_ERR(vc4_hdmi->hdmicore_regs); 3032 3033 /* This is shared between both HDMI controllers. Cannot 3034 * claim for both instances. Lets not convert to using 3035 * devm_platform_ioremap_resource_byname() like 3036 * the rest 3037 */ 3038 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 3039 if (!res) 3040 return -ENODEV; 3041 3042 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 3043 if (!vc4_hdmi->hd_regs) 3044 return -ENOMEM; 3045 3046 vc4_hdmi->cec_regs = devm_platform_ioremap_resource_byname(pdev, 3047 "cec"); 3048 if (IS_ERR(vc4_hdmi->cec_regs)) 3049 return PTR_ERR(vc4_hdmi->cec_regs); 3050 3051 vc4_hdmi->csc_regs = devm_platform_ioremap_resource_byname(pdev, 3052 "csc"); 3053 if (IS_ERR(vc4_hdmi->csc_regs)) 3054 return PTR_ERR(vc4_hdmi->csc_regs); 3055 3056 vc4_hdmi->dvp_regs = devm_platform_ioremap_resource_byname(pdev, 3057 "dvp"); 3058 if (IS_ERR(vc4_hdmi->dvp_regs)) 3059 return PTR_ERR(vc4_hdmi->dvp_regs); 3060 3061 vc4_hdmi->phy_regs = devm_platform_ioremap_resource_byname(pdev, 3062 "phy"); 3063 3064 if (IS_ERR(vc4_hdmi->phy_regs)) 3065 return PTR_ERR(vc4_hdmi->phy_regs); 3066 3067 vc4_hdmi->ram_regs = devm_platform_ioremap_resource_byname(pdev, 3068 "packet"); 3069 if (IS_ERR(vc4_hdmi->ram_regs)) 3070 return PTR_ERR(vc4_hdmi->ram_regs); 3071 3072 vc4_hdmi->rm_regs = devm_platform_ioremap_resource_byname(pdev, "rm"); 3073 if (IS_ERR(vc4_hdmi->rm_regs)) 3074 return PTR_ERR(vc4_hdmi->rm_regs); 3075 3076 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3077 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3078 drm_err(drm, "Failed to get HDMI state machine clock\n"); 3079 return PTR_ERR(vc4_hdmi->hsm_clock); 3080 } 3081 3082 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3083 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3084 drm_err(drm, "Failed to get pixel bvb clock\n"); 3085 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3086 } 3087 3088 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3089 if (IS_ERR(vc4_hdmi->audio_clock)) { 3090 drm_err(drm, "Failed to get audio clock\n"); 3091 return PTR_ERR(vc4_hdmi->audio_clock); 3092 } 3093 3094 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3095 if (IS_ERR(vc4_hdmi->cec_clock)) { 3096 drm_err(drm, "Failed to get CEC clock\n"); 3097 return PTR_ERR(vc4_hdmi->cec_clock); 3098 } 3099 3100 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3101 if (IS_ERR(vc4_hdmi->reset)) { 3102 drm_err(drm, "Failed to get HDMI reset line\n"); 3103 return PTR_ERR(vc4_hdmi->reset); 3104 } 3105 3106 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3107 if (ret) 3108 return ret; 3109 3110 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3111 if (ret) 3112 return ret; 3113 3114 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3115 if (ret) 3116 return ret; 3117 3118 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3119 if (ret) 3120 return ret; 3121 3122 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3123 if (ret) 3124 return ret; 3125 3126 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3127 if (ret) 3128 return ret; 3129 3130 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3131 if (ret) 3132 return ret; 3133 3134 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3135 if (ret) 3136 return ret; 3137 3138 return 0; 3139 } 3140 3141 static int vc4_hdmi_runtime_suspend(struct device *dev) 3142 { 3143 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3144 3145 clk_disable_unprepare(vc4_hdmi->audio_clock); 3146 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3147 3148 return 0; 3149 } 3150 3151 static int vc4_hdmi_runtime_resume(struct device *dev) 3152 { 3153 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3154 unsigned long __maybe_unused flags; 3155 u32 __maybe_unused value; 3156 unsigned long rate; 3157 int ret; 3158 3159 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3160 if (ret) 3161 return ret; 3162 3163 /* 3164 * Whenever the RaspberryPi boots without an HDMI monitor 3165 * plugged in, the firmware won't have initialized the HSM clock 3166 * rate and it will be reported as 0. 3167 * 3168 * If we try to access a register of the controller in such a 3169 * case, it will lead to a silent CPU stall. Let's make sure we 3170 * prevent such a case. 3171 */ 3172 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3173 if (!rate) { 3174 ret = -EINVAL; 3175 goto err_disable_clk; 3176 } 3177 3178 ret = clk_prepare_enable(vc4_hdmi->audio_clock); 3179 if (ret) 3180 goto err_disable_clk; 3181 3182 if (vc4_hdmi->variant->reset) 3183 vc4_hdmi->variant->reset(vc4_hdmi); 3184 3185 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3186 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3187 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3188 /* Set the logical address to Unregistered */ 3189 value |= VC4_HDMI_CEC_ADDR_MASK; 3190 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3191 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3192 3193 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3194 3195 if (!vc4_hdmi->variant->external_irq_controller) { 3196 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3197 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3198 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3199 } 3200 #endif 3201 3202 return 0; 3203 3204 err_disable_clk: 3205 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3206 return ret; 3207 } 3208 3209 static void vc4_hdmi_put_ddc_device(void *ptr) 3210 { 3211 struct vc4_hdmi *vc4_hdmi = ptr; 3212 3213 put_device(&vc4_hdmi->ddc->dev); 3214 } 3215 3216 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3217 { 3218 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3219 struct platform_device *pdev = to_platform_device(dev); 3220 struct drm_device *drm = dev_get_drvdata(master); 3221 struct vc4_hdmi *vc4_hdmi; 3222 struct drm_encoder *encoder; 3223 struct device_node *ddc_node; 3224 int ret; 3225 3226 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3227 if (!vc4_hdmi) 3228 return -ENOMEM; 3229 3230 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3231 if (ret) 3232 return ret; 3233 3234 spin_lock_init(&vc4_hdmi->hw_lock); 3235 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3236 3237 dev_set_drvdata(dev, vc4_hdmi); 3238 encoder = &vc4_hdmi->encoder.base; 3239 vc4_hdmi->encoder.type = variant->encoder_type; 3240 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3241 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3242 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3243 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3244 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3245 vc4_hdmi->pdev = pdev; 3246 vc4_hdmi->variant = variant; 3247 3248 /* 3249 * Since we don't know the state of the controller and its 3250 * display (if any), let's assume it's always enabled. 3251 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3252 * sure it's disabled, and avoid any inconsistency. 3253 */ 3254 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3255 vc4_hdmi->scdc_enabled = true; 3256 3257 ret = variant->init_resources(drm, vc4_hdmi); 3258 if (ret) 3259 return ret; 3260 3261 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3262 if (!ddc_node) { 3263 drm_err(drm, "Failed to find ddc node in device tree\n"); 3264 return -ENODEV; 3265 } 3266 3267 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3268 of_node_put(ddc_node); 3269 if (!vc4_hdmi->ddc) { 3270 drm_err(drm, "Failed to get ddc i2c adapter by node\n"); 3271 return -EPROBE_DEFER; 3272 } 3273 3274 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3275 if (ret) 3276 return ret; 3277 3278 /* Only use the GPIO HPD pin if present in the DT, otherwise 3279 * we'll use the HDMI core's register. 3280 */ 3281 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3282 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3283 return PTR_ERR(vc4_hdmi->hpd_gpio); 3284 } 3285 3286 vc4_hdmi->disable_wifi_frequencies = 3287 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3288 3289 ret = devm_pm_runtime_enable(dev); 3290 if (ret) 3291 return ret; 3292 3293 /* 3294 * We need to have the device powered up at this point to call 3295 * our reset hook and for the CEC init. 3296 */ 3297 ret = pm_runtime_resume_and_get(dev); 3298 if (ret) 3299 return ret; 3300 3301 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3302 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") || 3303 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") || 3304 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) && 3305 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3306 clk_prepare_enable(vc4_hdmi->pixel_clock); 3307 clk_prepare_enable(vc4_hdmi->hsm_clock); 3308 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3309 } 3310 3311 ret = drmm_encoder_init(drm, encoder, 3312 &vc4_hdmi_encoder_funcs, 3313 DRM_MODE_ENCODER_TMDS, 3314 NULL); 3315 if (ret) 3316 goto err_put_runtime_pm; 3317 3318 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3319 3320 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3321 if (ret) 3322 goto err_put_runtime_pm; 3323 3324 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3325 if (ret) 3326 goto err_put_runtime_pm; 3327 3328 ret = vc4_hdmi_cec_register(vc4_hdmi); 3329 if (ret) 3330 goto err_put_runtime_pm; 3331 3332 ret = vc4_hdmi_audio_init(vc4_hdmi); 3333 if (ret) 3334 goto err_put_runtime_pm; 3335 3336 pm_runtime_put_sync(dev); 3337 3338 return 0; 3339 3340 err_put_runtime_pm: 3341 pm_runtime_put_sync(dev); 3342 3343 return ret; 3344 } 3345 3346 static const struct component_ops vc4_hdmi_ops = { 3347 .bind = vc4_hdmi_bind, 3348 }; 3349 3350 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3351 { 3352 return component_add(&pdev->dev, &vc4_hdmi_ops); 3353 } 3354 3355 static void vc4_hdmi_dev_remove(struct platform_device *pdev) 3356 { 3357 component_del(&pdev->dev, &vc4_hdmi_ops); 3358 } 3359 3360 static const struct vc4_hdmi_variant bcm2835_variant = { 3361 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3362 .debugfs_name = "hdmi_regs", 3363 .card_name = "vc4-hdmi", 3364 .max_pixel_clock = 162000000, 3365 .registers = vc4_hdmi_fields, 3366 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3367 3368 .init_resources = vc4_hdmi_init_resources, 3369 .csc_setup = vc4_hdmi_csc_setup, 3370 .reset = vc4_hdmi_reset, 3371 .set_timings = vc4_hdmi_set_timings, 3372 .phy_init = vc4_hdmi_phy_init, 3373 .phy_disable = vc4_hdmi_phy_disable, 3374 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3375 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3376 .channel_map = vc4_hdmi_channel_map, 3377 .supports_hdr = false, 3378 }; 3379 3380 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3381 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3382 .debugfs_name = "hdmi0_regs", 3383 .card_name = "vc4-hdmi-0", 3384 .max_pixel_clock = 600000000, 3385 .registers = vc5_hdmi_hdmi0_fields, 3386 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3387 .phy_lane_mapping = { 3388 PHY_LANE_0, 3389 PHY_LANE_1, 3390 PHY_LANE_2, 3391 PHY_LANE_CK, 3392 }, 3393 .unsupported_odd_h_timings = true, 3394 .external_irq_controller = true, 3395 3396 .init_resources = vc5_hdmi_init_resources, 3397 .csc_setup = vc5_hdmi_csc_setup, 3398 .reset = vc5_hdmi_reset, 3399 .set_timings = vc5_hdmi_set_timings, 3400 .phy_init = vc5_hdmi_phy_init, 3401 .phy_disable = vc5_hdmi_phy_disable, 3402 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3403 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3404 .channel_map = vc5_hdmi_channel_map, 3405 .supports_hdr = true, 3406 .hp_detect = vc5_hdmi_hp_detect, 3407 }; 3408 3409 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3410 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3411 .debugfs_name = "hdmi1_regs", 3412 .card_name = "vc4-hdmi-1", 3413 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3414 .registers = vc5_hdmi_hdmi1_fields, 3415 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3416 .phy_lane_mapping = { 3417 PHY_LANE_1, 3418 PHY_LANE_0, 3419 PHY_LANE_CK, 3420 PHY_LANE_2, 3421 }, 3422 .unsupported_odd_h_timings = true, 3423 .external_irq_controller = true, 3424 3425 .init_resources = vc5_hdmi_init_resources, 3426 .csc_setup = vc5_hdmi_csc_setup, 3427 .reset = vc5_hdmi_reset, 3428 .set_timings = vc5_hdmi_set_timings, 3429 .phy_init = vc5_hdmi_phy_init, 3430 .phy_disable = vc5_hdmi_phy_disable, 3431 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3432 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3433 .channel_map = vc5_hdmi_channel_map, 3434 .supports_hdr = true, 3435 .hp_detect = vc5_hdmi_hp_detect, 3436 }; 3437 3438 static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = { 3439 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3440 .debugfs_name = "hdmi0_regs", 3441 .card_name = "vc4-hdmi-0", 3442 .max_pixel_clock = 600000000, 3443 .registers = vc6_hdmi_hdmi0_fields, 3444 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi0_fields), 3445 .phy_lane_mapping = { 3446 PHY_LANE_0, 3447 PHY_LANE_1, 3448 PHY_LANE_2, 3449 PHY_LANE_CK, 3450 }, 3451 .unsupported_odd_h_timings = false, 3452 .external_irq_controller = true, 3453 3454 .init_resources = vc5_hdmi_init_resources, 3455 .csc_setup = vc5_hdmi_csc_setup, 3456 .reset = vc5_hdmi_reset, 3457 .set_timings = vc5_hdmi_set_timings, 3458 .phy_init = vc6_hdmi_phy_init, 3459 .phy_disable = vc6_hdmi_phy_disable, 3460 .channel_map = vc5_hdmi_channel_map, 3461 .supports_hdr = true, 3462 .hp_detect = vc5_hdmi_hp_detect, 3463 }; 3464 3465 static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = { 3466 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3467 .debugfs_name = "hdmi1_regs", 3468 .card_name = "vc4-hdmi-1", 3469 .max_pixel_clock = 600000000, 3470 .registers = vc6_hdmi_hdmi1_fields, 3471 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi1_fields), 3472 .phy_lane_mapping = { 3473 PHY_LANE_0, 3474 PHY_LANE_1, 3475 PHY_LANE_2, 3476 PHY_LANE_CK, 3477 }, 3478 .unsupported_odd_h_timings = false, 3479 .external_irq_controller = true, 3480 3481 .init_resources = vc5_hdmi_init_resources, 3482 .csc_setup = vc5_hdmi_csc_setup, 3483 .reset = vc5_hdmi_reset, 3484 .set_timings = vc5_hdmi_set_timings, 3485 .phy_init = vc6_hdmi_phy_init, 3486 .phy_disable = vc6_hdmi_phy_disable, 3487 .channel_map = vc5_hdmi_channel_map, 3488 .supports_hdr = true, 3489 .hp_detect = vc5_hdmi_hp_detect, 3490 }; 3491 3492 static const struct of_device_id vc4_hdmi_dt_match[] = { 3493 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3494 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3495 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3496 { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant }, 3497 { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant }, 3498 {} 3499 }; 3500 3501 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3502 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3503 vc4_hdmi_runtime_resume, 3504 NULL) 3505 }; 3506 3507 struct platform_driver vc4_hdmi_driver = { 3508 .probe = vc4_hdmi_dev_probe, 3509 .remove = vc4_hdmi_dev_remove, 3510 .driver = { 3511 .name = "vc4_hdmi", 3512 .of_match_table = vc4_hdmi_dt_match, 3513 .pm = &vc4_hdmi_pm_ops, 3514 }, 3515 }; 3516