1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/display/drm_hdmi_state_helper.h> 36 #include <drm/display/drm_scdc_helper.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_drv.h> 39 #include <drm/drm_edid.h> 40 #include <drm/drm_probe_helper.h> 41 #include <drm/drm_simple_kms_helper.h> 42 #include <linux/clk.h> 43 #include <linux/component.h> 44 #include <linux/gpio/consumer.h> 45 #include <linux/i2c.h> 46 #include <linux/of.h> 47 #include <linux/of_address.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/rational.h> 50 #include <linux/reset.h> 51 #include <sound/dmaengine_pcm.h> 52 #include <sound/hdmi-codec.h> 53 #include <sound/pcm_drm_eld.h> 54 #include <sound/pcm_params.h> 55 #include <sound/soc.h> 56 #include "media/cec.h" 57 #include "vc4_drv.h" 58 #include "vc4_hdmi.h" 59 #include "vc4_hdmi_regs.h" 60 #include "vc4_regs.h" 61 62 #define VC5_HDMI_HORZA_HFP_SHIFT 16 63 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 64 #define VC5_HDMI_HORZA_VPOS BIT(15) 65 #define VC5_HDMI_HORZA_HPOS BIT(14) 66 #define VC5_HDMI_HORZA_HAP_SHIFT 0 67 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 68 69 #define VC5_HDMI_HORZB_HBP_SHIFT 16 70 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 71 #define VC5_HDMI_HORZB_HSP_SHIFT 0 72 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 73 74 #define VC5_HDMI_VERTA_VSP_SHIFT 24 75 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 76 #define VC5_HDMI_VERTA_VFP_SHIFT 16 77 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 78 #define VC5_HDMI_VERTA_VAL_SHIFT 0 79 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 80 81 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 82 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 83 84 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 85 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 86 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 87 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 88 89 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 90 91 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 93 94 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 96 97 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 98 99 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 101 102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0) 103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0) 104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4) 105 106 # define VC4_HD_M_SW_RST BIT(2) 107 # define VC4_HD_M_ENABLE BIT(0) 108 109 #define HSM_MIN_CLOCK_FREQ 120000000 110 #define CEC_CLOCK_FREQ 40000 111 112 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 113 114 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 115 { 116 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 117 118 lockdep_assert_held(&vc4_hdmi->mutex); 119 120 if (!display->is_hdmi) 121 return false; 122 123 if (!display->hdmi.scdc.supported || 124 !display->hdmi.scdc.scrambling.supported) 125 return false; 126 127 return true; 128 } 129 130 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 131 unsigned int bpc, 132 enum hdmi_colorspace fmt) 133 { 134 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt); 135 136 return clock > HDMI_14_MAX_TMDS_CLK; 137 } 138 139 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 140 { 141 struct drm_debugfs_entry *entry = m->private; 142 struct vc4_hdmi *vc4_hdmi = entry->file.data; 143 struct drm_device *drm = vc4_hdmi->connector.dev; 144 struct drm_printer p = drm_seq_file_printer(m); 145 int idx; 146 147 if (!drm_dev_enter(drm, &idx)) 148 return -ENODEV; 149 150 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 151 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 152 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 153 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 154 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 155 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 156 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 157 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 158 159 drm_dev_exit(idx); 160 161 return 0; 162 } 163 164 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 165 { 166 struct drm_device *drm = vc4_hdmi->connector.dev; 167 unsigned long flags; 168 int idx; 169 170 /* 171 * We can be called by our bind callback, when the 172 * connector->dev pointer might not be initialised yet. 173 */ 174 if (drm && !drm_dev_enter(drm, &idx)) 175 return; 176 177 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 178 179 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 180 udelay(1); 181 HDMI_WRITE(HDMI_M_CTL, 0); 182 183 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 184 185 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 186 VC4_HDMI_SW_RESET_HDMI | 187 VC4_HDMI_SW_RESET_FORMAT_DETECT); 188 189 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 190 191 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 192 193 if (drm) 194 drm_dev_exit(idx); 195 } 196 197 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 198 { 199 struct drm_device *drm = vc4_hdmi->connector.dev; 200 unsigned long flags; 201 int idx; 202 203 /* 204 * We can be called by our bind callback, when the 205 * connector->dev pointer might not be initialised yet. 206 */ 207 if (drm && !drm_dev_enter(drm, &idx)) 208 return; 209 210 reset_control_reset(vc4_hdmi->reset); 211 212 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 213 214 HDMI_WRITE(HDMI_DVP_CTL, 0); 215 216 HDMI_WRITE(HDMI_CLOCK_STOP, 217 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 218 219 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 220 221 if (drm) 222 drm_dev_exit(idx); 223 } 224 225 #ifdef CONFIG_DRM_VC4_HDMI_CEC 226 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 227 { 228 struct drm_device *drm = vc4_hdmi->connector.dev; 229 unsigned long cec_rate; 230 unsigned long flags; 231 u16 clk_cnt; 232 u32 value; 233 int idx; 234 235 /* 236 * This function is called by our runtime_resume implementation 237 * and thus at bind time, when we haven't registered our 238 * connector yet and thus don't have a pointer to the DRM 239 * device. 240 */ 241 if (drm && !drm_dev_enter(drm, &idx)) 242 return; 243 244 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 245 246 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 247 248 value = HDMI_READ(HDMI_CEC_CNTRL_1); 249 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 250 251 /* 252 * Set the clock divider: the hsm_clock rate and this divider 253 * setting will give a 40 kHz CEC clock. 254 */ 255 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 256 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 257 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 258 259 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 260 261 if (drm) 262 drm_dev_exit(idx); 263 } 264 #else 265 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 266 #endif 267 268 static int reset_pipe(struct drm_crtc *crtc, 269 struct drm_modeset_acquire_ctx *ctx) 270 { 271 struct drm_atomic_state *state; 272 struct drm_crtc_state *crtc_state; 273 int ret; 274 275 state = drm_atomic_state_alloc(crtc->dev); 276 if (!state) 277 return -ENOMEM; 278 279 state->acquire_ctx = ctx; 280 281 crtc_state = drm_atomic_get_crtc_state(state, crtc); 282 if (IS_ERR(crtc_state)) { 283 ret = PTR_ERR(crtc_state); 284 goto out; 285 } 286 287 crtc_state->connectors_changed = true; 288 289 ret = drm_atomic_commit(state); 290 out: 291 drm_atomic_state_put(state); 292 293 return ret; 294 } 295 296 static int vc4_hdmi_reset_link(struct drm_connector *connector, 297 struct drm_modeset_acquire_ctx *ctx) 298 { 299 struct drm_device *drm; 300 struct vc4_hdmi *vc4_hdmi; 301 struct drm_connector_state *conn_state; 302 struct drm_crtc_state *crtc_state; 303 struct drm_crtc *crtc; 304 bool scrambling_needed; 305 u8 config; 306 int ret; 307 308 if (!connector) 309 return 0; 310 311 drm = connector->dev; 312 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 313 if (ret) 314 return ret; 315 316 conn_state = connector->state; 317 crtc = conn_state->crtc; 318 if (!crtc) 319 return 0; 320 321 ret = drm_modeset_lock(&crtc->mutex, ctx); 322 if (ret) 323 return ret; 324 325 crtc_state = crtc->state; 326 if (!crtc_state->active) 327 return 0; 328 329 vc4_hdmi = connector_to_vc4_hdmi(connector); 330 mutex_lock(&vc4_hdmi->mutex); 331 332 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 333 mutex_unlock(&vc4_hdmi->mutex); 334 return 0; 335 } 336 337 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 338 vc4_hdmi->output_bpc, 339 vc4_hdmi->output_format); 340 if (!scrambling_needed) { 341 mutex_unlock(&vc4_hdmi->mutex); 342 return 0; 343 } 344 345 if (conn_state->commit && 346 !try_wait_for_completion(&conn_state->commit->hw_done)) { 347 mutex_unlock(&vc4_hdmi->mutex); 348 return 0; 349 } 350 351 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 352 if (ret < 0) { 353 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 354 mutex_unlock(&vc4_hdmi->mutex); 355 return 0; 356 } 357 358 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 359 mutex_unlock(&vc4_hdmi->mutex); 360 return 0; 361 } 362 363 mutex_unlock(&vc4_hdmi->mutex); 364 365 /* 366 * HDMI 2.0 says that one should not send scrambled data 367 * prior to configuring the sink scrambling, and that 368 * TMDS clock/data transmission should be suspended when 369 * changing the TMDS clock rate in the sink. So let's 370 * just do a full modeset here, even though some sinks 371 * would be perfectly happy if were to just reconfigure 372 * the SCDC settings on the fly. 373 */ 374 return reset_pipe(crtc, ctx); 375 } 376 377 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 378 struct drm_modeset_acquire_ctx *ctx, 379 enum drm_connector_status status) 380 { 381 struct drm_connector *connector = &vc4_hdmi->connector; 382 const struct drm_edid *drm_edid; 383 int ret; 384 385 /* 386 * NOTE: This function should really be called with vc4_hdmi->mutex 387 * held, but doing so results in reentrancy issues since 388 * cec_s_phys_addr() might call .adap_enable, which leads to that 389 * funtion being called with our mutex held. 390 * 391 * A similar situation occurs with vc4_hdmi_reset_link() that 392 * will call into our KMS hooks if the scrambling was enabled. 393 * 394 * Concurrency isn't an issue at the moment since we don't share 395 * any state with any of the other frameworks so we can ignore 396 * the lock for now. 397 */ 398 399 if (status == connector_status_disconnected) { 400 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 401 return; 402 } 403 404 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc); 405 406 drm_edid_connector_update(connector, drm_edid); 407 cec_s_phys_addr(vc4_hdmi->cec_adap, 408 connector->display_info.source_physical_address, false); 409 410 if (!drm_edid) 411 return; 412 413 drm_edid_free(drm_edid); 414 415 for (;;) { 416 ret = vc4_hdmi_reset_link(connector, ctx); 417 if (ret == -EDEADLK) { 418 drm_modeset_backoff(ctx); 419 continue; 420 } 421 422 break; 423 } 424 } 425 426 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 427 struct drm_modeset_acquire_ctx *ctx, 428 bool force) 429 { 430 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 431 enum drm_connector_status status = connector_status_disconnected; 432 433 /* 434 * NOTE: This function should really take vc4_hdmi->mutex, but 435 * doing so results in reentrancy issues since 436 * vc4_hdmi_handle_hotplug() can call into other functions that 437 * would take the mutex while it's held here. 438 * 439 * Concurrency isn't an issue at the moment since we don't share 440 * any state with any of the other frameworks so we can ignore 441 * the lock for now. 442 */ 443 444 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 445 446 if (vc4_hdmi->hpd_gpio) { 447 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 448 status = connector_status_connected; 449 } else { 450 if (vc4_hdmi->variant->hp_detect && 451 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 452 status = connector_status_connected; 453 } 454 455 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 456 pm_runtime_put(&vc4_hdmi->pdev->dev); 457 458 return status; 459 } 460 461 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 462 { 463 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 464 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 465 const struct drm_edid *drm_edid; 466 int ret = 0; 467 468 /* 469 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 470 * results in reentrancy issues since cec_s_phys_addr() might call 471 * .adap_enable, which leads to that funtion being called with our mutex 472 * held. 473 * 474 * Concurrency isn't an issue at the moment since we don't share 475 * any state with any of the other frameworks so we can ignore 476 * the lock for now. 477 */ 478 479 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc); 480 drm_edid_connector_update(connector, drm_edid); 481 cec_s_phys_addr(vc4_hdmi->cec_adap, 482 connector->display_info.source_physical_address, false); 483 if (!drm_edid) 484 return 0; 485 486 ret = drm_edid_connector_add_modes(connector); 487 drm_edid_free(drm_edid); 488 489 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 490 struct drm_device *drm = connector->dev; 491 const struct drm_display_mode *mode; 492 493 list_for_each_entry(mode, &connector->probed_modes, head) { 494 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) { 495 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 496 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 497 } 498 } 499 } 500 501 return ret; 502 } 503 504 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 505 struct drm_atomic_state *state) 506 { 507 struct drm_connector_state *old_state = 508 drm_atomic_get_old_connector_state(state, connector); 509 struct drm_connector_state *new_state = 510 drm_atomic_get_new_connector_state(state, connector); 511 struct drm_crtc *crtc = new_state->crtc; 512 513 if (!crtc) 514 return 0; 515 516 if (old_state->tv.margins.left != new_state->tv.margins.left || 517 old_state->tv.margins.right != new_state->tv.margins.right || 518 old_state->tv.margins.top != new_state->tv.margins.top || 519 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 520 struct drm_crtc_state *crtc_state; 521 int ret; 522 523 crtc_state = drm_atomic_get_crtc_state(state, crtc); 524 if (IS_ERR(crtc_state)) 525 return PTR_ERR(crtc_state); 526 527 /* 528 * Strictly speaking, we should be calling 529 * drm_atomic_helper_check_planes() after our call to 530 * drm_atomic_add_affected_planes(). However, the 531 * connector atomic_check is called as part of 532 * drm_atomic_helper_check_modeset() that already 533 * happens before a call to 534 * drm_atomic_helper_check_planes() in 535 * drm_atomic_helper_check(). 536 */ 537 ret = drm_atomic_add_affected_planes(state, crtc); 538 if (ret) 539 return ret; 540 } 541 542 if (old_state->colorspace != new_state->colorspace) { 543 struct drm_crtc_state *crtc_state; 544 545 crtc_state = drm_atomic_get_crtc_state(state, crtc); 546 if (IS_ERR(crtc_state)) 547 return PTR_ERR(crtc_state); 548 549 crtc_state->mode_changed = true; 550 } 551 552 return drm_atomic_helper_connector_hdmi_check(connector, state); 553 } 554 555 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 556 { 557 drm_atomic_helper_connector_reset(connector); 558 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); 559 drm_atomic_helper_connector_tv_margins_reset(connector); 560 } 561 562 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 563 .fill_modes = drm_helper_probe_single_connector_modes, 564 .reset = vc4_hdmi_connector_reset, 565 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 566 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 567 }; 568 569 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 570 .detect_ctx = vc4_hdmi_connector_detect_ctx, 571 .get_modes = vc4_hdmi_connector_get_modes, 572 .atomic_check = vc4_hdmi_connector_atomic_check, 573 }; 574 575 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs; 576 577 static int vc4_hdmi_connector_init(struct drm_device *dev, 578 struct vc4_hdmi *vc4_hdmi) 579 { 580 struct drm_connector *connector = &vc4_hdmi->connector; 581 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 582 unsigned int max_bpc = 8; 583 int ret; 584 585 if (vc4_hdmi->variant->supports_hdr) 586 max_bpc = 12; 587 588 ret = drmm_connector_hdmi_init(dev, connector, 589 "Broadcom", "Videocore", 590 &vc4_hdmi_connector_funcs, 591 &vc4_hdmi_hdmi_connector_funcs, 592 DRM_MODE_CONNECTOR_HDMIA, 593 vc4_hdmi->ddc, 594 BIT(HDMI_COLORSPACE_RGB) | 595 BIT(HDMI_COLORSPACE_YUV422) | 596 BIT(HDMI_COLORSPACE_YUV444), 597 max_bpc); 598 if (ret) 599 return ret; 600 601 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 602 603 /* 604 * Some of the properties below require access to state, like bpc. 605 * Allocate some default initial connector state with our reset helper. 606 */ 607 if (connector->funcs->reset) 608 connector->funcs->reset(connector); 609 610 /* Create and attach TV margin props to this connector. */ 611 ret = drm_mode_create_tv_margin_properties(dev); 612 if (ret) 613 return ret; 614 615 ret = drm_mode_create_hdmi_colorspace_property(connector, 0); 616 if (ret) 617 return ret; 618 619 drm_connector_attach_colorspace_property(connector); 620 drm_connector_attach_tv_margin_properties(connector); 621 622 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 623 DRM_CONNECTOR_POLL_DISCONNECT); 624 625 connector->interlace_allowed = 1; 626 connector->doublescan_allowed = 0; 627 connector->stereo_allowed = 1; 628 629 ret = drm_connector_attach_broadcast_rgb_property(connector); 630 if (ret) 631 return ret; 632 633 drm_connector_attach_encoder(connector, encoder); 634 635 return 0; 636 } 637 638 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi, 639 enum hdmi_infoframe_type type, 640 bool poll) 641 { 642 struct drm_device *drm = vc4_hdmi->connector.dev; 643 u32 packet_id = type - 0x80; 644 unsigned long flags; 645 int ret = 0; 646 int idx; 647 648 if (!drm_dev_enter(drm, &idx)) 649 return -ENODEV; 650 651 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 652 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 653 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 654 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 655 656 if (poll) { 657 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 658 BIT(packet_id)), 100); 659 } 660 661 drm_dev_exit(idx); 662 return ret; 663 } 664 665 static int vc4_hdmi_write_infoframe(struct drm_connector *connector, 666 enum hdmi_infoframe_type type, 667 const u8 *infoframe, size_t len) 668 { 669 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 670 struct drm_device *drm = connector->dev; 671 u32 packet_id = type - 0x80; 672 const struct vc4_hdmi_register *ram_packet_start = 673 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 674 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 675 u32 packet_reg_next = ram_packet_start->offset + 676 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 677 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 678 ram_packet_start->reg); 679 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 680 unsigned long flags; 681 ssize_t i; 682 int ret; 683 int idx; 684 685 if (!drm_dev_enter(drm, &idx)) 686 return 0; 687 688 if (len > sizeof(buffer)) { 689 ret = -ENOMEM; 690 goto out; 691 } 692 693 memcpy(buffer, infoframe, len); 694 695 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 696 VC4_HDMI_RAM_PACKET_ENABLE), 697 "Packet RAM has to be on to store the packet."); 698 699 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true); 700 if (ret) { 701 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 702 goto out; 703 } 704 705 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 706 707 for (i = 0; i < len; i += 7) { 708 writel(buffer[i + 0] << 0 | 709 buffer[i + 1] << 8 | 710 buffer[i + 2] << 16, 711 base + packet_reg); 712 packet_reg += 4; 713 714 writel(buffer[i + 3] << 0 | 715 buffer[i + 4] << 8 | 716 buffer[i + 5] << 16 | 717 buffer[i + 6] << 24, 718 base + packet_reg); 719 packet_reg += 4; 720 } 721 722 /* 723 * clear remainder of packet ram as it's included in the 724 * infoframe and triggers a checksum error on hdmi analyser 725 */ 726 for (; packet_reg < packet_reg_next; packet_reg += 4) 727 writel(0, base + packet_reg); 728 729 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 730 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 731 732 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 733 734 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 735 BIT(packet_id)), 100); 736 if (ret) 737 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 738 739 out: 740 drm_dev_exit(idx); 741 return ret; 742 } 743 744 #define SCRAMBLING_POLLING_DELAY_MS 1000 745 746 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 747 { 748 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 749 struct drm_connector *connector = &vc4_hdmi->connector; 750 struct drm_device *drm = connector->dev; 751 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 752 unsigned long flags; 753 int idx; 754 755 lockdep_assert_held(&vc4_hdmi->mutex); 756 757 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 758 return; 759 760 if (!vc4_hdmi_mode_needs_scrambling(mode, 761 vc4_hdmi->output_bpc, 762 vc4_hdmi->output_format)) 763 return; 764 765 if (!drm_dev_enter(drm, &idx)) 766 return; 767 768 drm_scdc_set_high_tmds_clock_ratio(connector, true); 769 drm_scdc_set_scrambling(connector, true); 770 771 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 772 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 773 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 774 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 775 776 drm_dev_exit(idx); 777 778 vc4_hdmi->scdc_enabled = true; 779 780 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 781 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 782 } 783 784 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 785 { 786 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 787 struct drm_connector *connector = &vc4_hdmi->connector; 788 struct drm_device *drm = connector->dev; 789 unsigned long flags; 790 int idx; 791 792 lockdep_assert_held(&vc4_hdmi->mutex); 793 794 if (!vc4_hdmi->scdc_enabled) 795 return; 796 797 vc4_hdmi->scdc_enabled = false; 798 799 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 800 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 801 802 if (!drm_dev_enter(drm, &idx)) 803 return; 804 805 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 806 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 807 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 808 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 809 810 drm_scdc_set_scrambling(connector, false); 811 drm_scdc_set_high_tmds_clock_ratio(connector, false); 812 813 drm_dev_exit(idx); 814 } 815 816 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 817 { 818 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 819 struct vc4_hdmi, 820 scrambling_work); 821 struct drm_connector *connector = &vc4_hdmi->connector; 822 823 if (drm_scdc_get_scrambling_status(connector)) 824 return; 825 826 drm_scdc_set_high_tmds_clock_ratio(connector, true); 827 drm_scdc_set_scrambling(connector, true); 828 829 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 830 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 831 } 832 833 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 834 struct drm_atomic_state *state) 835 { 836 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 837 struct drm_device *drm = vc4_hdmi->connector.dev; 838 unsigned long flags; 839 int idx; 840 841 mutex_lock(&vc4_hdmi->mutex); 842 843 vc4_hdmi->packet_ram_enabled = false; 844 845 if (!drm_dev_enter(drm, &idx)) 846 goto out; 847 848 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 849 850 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 851 852 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 853 854 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 855 856 mdelay(1); 857 858 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 859 HDMI_WRITE(HDMI_VID_CTL, 860 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 861 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 862 863 vc4_hdmi_disable_scrambling(encoder); 864 865 drm_dev_exit(idx); 866 867 out: 868 mutex_unlock(&vc4_hdmi->mutex); 869 } 870 871 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 872 struct drm_atomic_state *state) 873 { 874 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 875 struct drm_device *drm = vc4_hdmi->connector.dev; 876 unsigned long flags; 877 int ret; 878 int idx; 879 880 mutex_lock(&vc4_hdmi->mutex); 881 882 if (!drm_dev_enter(drm, &idx)) 883 goto out; 884 885 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 886 HDMI_WRITE(HDMI_VID_CTL, 887 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 888 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 889 890 if (vc4_hdmi->variant->phy_disable) 891 vc4_hdmi->variant->phy_disable(vc4_hdmi); 892 893 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 894 clk_disable_unprepare(vc4_hdmi->pixel_clock); 895 896 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 897 if (ret < 0) 898 DRM_ERROR("Failed to release power domain: %d\n", ret); 899 900 drm_dev_exit(idx); 901 902 out: 903 mutex_unlock(&vc4_hdmi->mutex); 904 } 905 906 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 907 struct drm_connector_state *state, 908 const struct drm_display_mode *mode) 909 { 910 struct drm_device *drm = vc4_hdmi->connector.dev; 911 unsigned long flags; 912 u32 csc_ctl; 913 int idx; 914 915 if (!drm_dev_enter(drm, &idx)) 916 return; 917 918 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 919 920 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 921 VC4_HD_CSC_CTL_ORDER); 922 923 if (state->hdmi.is_limited_range) { 924 /* CEA VICs other than #1 requre limited range RGB 925 * output unless overridden by an AVI infoframe. 926 * Apply a colorspace conversion to squash 0-255 down 927 * to 16-235. The matrix here is: 928 * 929 * [ 0 0 0.8594 16] 930 * [ 0 0.8594 0 16] 931 * [ 0.8594 0 0 16] 932 * [ 0 0 0 1] 933 */ 934 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 935 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 936 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 937 VC4_HD_CSC_CTL_MODE); 938 939 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 940 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 941 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 942 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 943 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 944 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 945 } 946 947 /* The RGB order applies even when CSC is disabled. */ 948 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 949 950 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 951 952 drm_dev_exit(idx); 953 } 954 955 /* 956 * Matrices for (internal) RGB to RGB output. 957 * 958 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 959 */ 960 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = { 961 { 962 /* 963 * Full range - unity 964 * 965 * [ 1 0 0 0] 966 * [ 0 1 0 0] 967 * [ 0 0 1 0] 968 */ 969 { 0x2000, 0x0000, 0x0000, 0x0000 }, 970 { 0x0000, 0x2000, 0x0000, 0x0000 }, 971 { 0x0000, 0x0000, 0x2000, 0x0000 }, 972 }, 973 { 974 /* 975 * Limited range 976 * 977 * CEA VICs other than #1 require limited range RGB 978 * output unless overridden by an AVI infoframe. Apply a 979 * colorspace conversion to squash 0-255 down to 16-235. 980 * The matrix here is: 981 * 982 * [ 0.8594 0 0 16] 983 * [ 0 0.8594 0 16] 984 * [ 0 0 0.8594 16] 985 */ 986 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 987 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 988 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 989 }, 990 }; 991 992 /* 993 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace 994 * 995 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 996 */ 997 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = { 998 { 999 /* 1000 * Full Range 1001 * 1002 * [ 0.299000 0.587000 0.114000 0 ] 1003 * [ -0.168736 -0.331264 0.500000 128 ] 1004 * [ 0.500000 -0.418688 -0.081312 128 ] 1005 */ 1006 { 0x0991, 0x12c9, 0x03a6, 0x0000 }, 1007 { 0xfa9b, 0xf567, 0x1000, 0x2000 }, 1008 { 0x1000, 0xf29b, 0xfd67, 0x2000 }, 1009 }, 1010 { 1011 /* Limited Range 1012 * 1013 * [ 0.255785 0.502160 0.097523 16 ] 1014 * [ -0.147644 -0.289856 0.437500 128 ] 1015 * [ 0.437500 -0.366352 -0.071148 128 ] 1016 */ 1017 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1018 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1019 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1020 }, 1021 }; 1022 1023 /* 1024 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace 1025 * 1026 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1027 */ 1028 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = { 1029 { 1030 /* 1031 * Full Range 1032 * 1033 * [ 0.212600 0.715200 0.072200 0 ] 1034 * [ -0.114572 -0.385428 0.500000 128 ] 1035 * [ 0.500000 -0.454153 -0.045847 128 ] 1036 */ 1037 { 0x06ce, 0x16e3, 0x024f, 0x0000 }, 1038 { 0xfc56, 0xf3ac, 0x1000, 0x2000 }, 1039 { 0x1000, 0xf179, 0xfe89, 0x2000 }, 1040 }, 1041 { 1042 /* 1043 * Limited Range 1044 * 1045 * [ 0.181906 0.611804 0.061758 16 ] 1046 * [ -0.100268 -0.337232 0.437500 128 ] 1047 * [ 0.437500 -0.397386 -0.040114 128 ] 1048 */ 1049 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1050 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1051 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1052 }, 1053 }; 1054 1055 /* 1056 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace 1057 * 1058 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1059 */ 1060 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = { 1061 { 1062 /* 1063 * Full Range 1064 * 1065 * [ 0.262700 0.678000 0.059300 0 ] 1066 * [ -0.139630 -0.360370 0.500000 128 ] 1067 * [ 0.500000 -0.459786 -0.040214 128 ] 1068 */ 1069 { 0x0868, 0x15b2, 0x01e6, 0x0000 }, 1070 { 0xfb89, 0xf479, 0x1000, 0x2000 }, 1071 { 0x1000, 0xf14a, 0xfeb8, 0x2000 }, 1072 }, 1073 { 1074 /* Limited Range 1075 * 1076 * [ 0.224732 0.580008 0.050729 16 ] 1077 * [ -0.122176 -0.315324 0.437500 128 ] 1078 * [ 0.437500 -0.402312 -0.035188 128 ] 1079 */ 1080 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1081 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1082 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1083 }, 1084 }; 1085 1086 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1087 const u16 coeffs[3][4]) 1088 { 1089 lockdep_assert_held(&vc4_hdmi->hw_lock); 1090 1091 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1092 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1093 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1094 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1095 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1096 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1097 } 1098 1099 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi, 1100 const u16 coeffs[3][4]) 1101 { 1102 lockdep_assert_held(&vc4_hdmi->hw_lock); 1103 1104 /* YUV444 needs the CSC matrices using the channels in a different order */ 1105 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]); 1106 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]); 1107 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]); 1108 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]); 1109 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]); 1110 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]); 1111 } 1112 1113 static const u16 1114 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4] 1115 { 1116 switch (colorspace) { 1117 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC: 1118 case DRM_MODE_COLORIMETRY_XVYCC_601: 1119 case DRM_MODE_COLORIMETRY_SYCC_601: 1120 case DRM_MODE_COLORIMETRY_OPYCC_601: 1121 case DRM_MODE_COLORIMETRY_BT601_YCC: 1122 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited]; 1123 1124 default: 1125 case DRM_MODE_COLORIMETRY_NO_DATA: 1126 case DRM_MODE_COLORIMETRY_BT709_YCC: 1127 case DRM_MODE_COLORIMETRY_XVYCC_709: 1128 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED: 1129 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT: 1130 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited]; 1131 1132 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 1133 case DRM_MODE_COLORIMETRY_BT2020_YCC: 1134 case DRM_MODE_COLORIMETRY_BT2020_RGB: 1135 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 1136 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 1137 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited]; 1138 } 1139 } 1140 1141 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1142 struct drm_connector_state *state, 1143 const struct drm_display_mode *mode) 1144 { 1145 struct drm_device *drm = vc4_hdmi->connector.dev; 1146 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0; 1147 unsigned long flags; 1148 const u16 (*csc)[4]; 1149 u32 if_cfg = 0; 1150 u32 if_xbar = 0x543210; 1151 u32 csc_chan_ctl = 0; 1152 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1153 VC5_MT_CP_CSC_CTL_MODE); 1154 int idx; 1155 1156 if (!drm_dev_enter(drm, &idx)) 1157 return; 1158 1159 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1160 1161 switch (state->hdmi.output_format) { 1162 case HDMI_COLORSPACE_YUV444: 1163 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1164 1165 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc); 1166 break; 1167 1168 case HDMI_COLORSPACE_YUV422: 1169 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1170 1171 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1172 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1173 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1174 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1175 1176 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1177 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1178 1179 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1180 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1181 1182 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc); 1183 break; 1184 1185 case HDMI_COLORSPACE_RGB: 1186 if_xbar = 0x354021; 1187 1188 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]); 1189 break; 1190 1191 default: 1192 break; 1193 } 1194 1195 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1196 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1197 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1198 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1199 1200 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1201 1202 drm_dev_exit(idx); 1203 } 1204 1205 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1206 struct drm_connector_state *state, 1207 const struct drm_display_mode *mode) 1208 { 1209 struct drm_device *drm = vc4_hdmi->connector.dev; 1210 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1211 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1212 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1213 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1214 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1215 VC4_HDMI_VERTA_VSP) | 1216 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1217 VC4_HDMI_VERTA_VFP) | 1218 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1219 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1220 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1221 interlaced, 1222 VC4_HDMI_VERTB_VBP)); 1223 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1224 VC4_SET_FIELD(mode->crtc_vtotal - 1225 mode->crtc_vsync_end, 1226 VC4_HDMI_VERTB_VBP)); 1227 unsigned long flags; 1228 u32 reg; 1229 int idx; 1230 1231 if (!drm_dev_enter(drm, &idx)) 1232 return; 1233 1234 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1235 1236 HDMI_WRITE(HDMI_HORZA, 1237 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1238 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1239 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1240 VC4_HDMI_HORZA_HAP)); 1241 1242 HDMI_WRITE(HDMI_HORZB, 1243 VC4_SET_FIELD((mode->htotal - 1244 mode->hsync_end) * pixel_rep, 1245 VC4_HDMI_HORZB_HBP) | 1246 VC4_SET_FIELD((mode->hsync_end - 1247 mode->hsync_start) * pixel_rep, 1248 VC4_HDMI_HORZB_HSP) | 1249 VC4_SET_FIELD((mode->hsync_start - 1250 mode->hdisplay) * pixel_rep, 1251 VC4_HDMI_HORZB_HFP)); 1252 1253 HDMI_WRITE(HDMI_VERTA0, verta); 1254 HDMI_WRITE(HDMI_VERTA1, verta); 1255 1256 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1257 HDMI_WRITE(HDMI_VERTB1, vertb); 1258 1259 reg = HDMI_READ(HDMI_MISC_CONTROL); 1260 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1261 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1262 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1263 1264 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1265 1266 drm_dev_exit(idx); 1267 } 1268 1269 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1270 struct drm_connector_state *state, 1271 const struct drm_display_mode *mode) 1272 { 1273 struct drm_device *drm = vc4_hdmi->connector.dev; 1274 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1275 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1276 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1277 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1278 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1279 VC5_HDMI_VERTA_VSP) | 1280 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1281 VC5_HDMI_VERTA_VFP) | 1282 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1283 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1284 VC5_HDMI_VERTB_VSPO) | 1285 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1286 interlaced, 1287 VC4_HDMI_VERTB_VBP)); 1288 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1289 VC4_SET_FIELD(mode->crtc_vtotal - 1290 mode->crtc_vsync_end, 1291 VC4_HDMI_VERTB_VBP)); 1292 unsigned long flags; 1293 unsigned char gcp; 1294 u32 reg; 1295 int idx; 1296 1297 if (!drm_dev_enter(drm, &idx)) 1298 return; 1299 1300 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1301 1302 HDMI_WRITE(HDMI_HORZA, 1303 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1304 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1305 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1306 VC5_HDMI_HORZA_HAP) | 1307 VC4_SET_FIELD((mode->hsync_start - 1308 mode->hdisplay) * pixel_rep, 1309 VC5_HDMI_HORZA_HFP)); 1310 1311 HDMI_WRITE(HDMI_HORZB, 1312 VC4_SET_FIELD((mode->htotal - 1313 mode->hsync_end) * pixel_rep, 1314 VC5_HDMI_HORZB_HBP) | 1315 VC4_SET_FIELD((mode->hsync_end - 1316 mode->hsync_start) * pixel_rep, 1317 VC5_HDMI_HORZB_HSP)); 1318 1319 HDMI_WRITE(HDMI_VERTA0, verta); 1320 HDMI_WRITE(HDMI_VERTA1, verta); 1321 1322 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1323 HDMI_WRITE(HDMI_VERTB1, vertb); 1324 1325 switch (state->hdmi.output_bpc) { 1326 case 12: 1327 gcp = 6; 1328 break; 1329 case 10: 1330 gcp = 5; 1331 break; 1332 case 8: 1333 default: 1334 gcp = 0; 1335 break; 1336 } 1337 1338 /* 1339 * YCC422 is always 36-bit and not considered deep colour so 1340 * doesn't signal in GCP. 1341 */ 1342 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) { 1343 gcp = 0; 1344 } 1345 1346 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1347 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1348 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1349 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1350 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1351 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1352 1353 reg = HDMI_READ(HDMI_GCP_WORD_1); 1354 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1355 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1356 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK; 1357 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE; 1358 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1359 1360 reg = HDMI_READ(HDMI_GCP_CONFIG); 1361 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1362 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1363 1364 reg = HDMI_READ(HDMI_MISC_CONTROL); 1365 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1366 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1367 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1368 1369 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1370 1371 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1372 1373 drm_dev_exit(idx); 1374 } 1375 1376 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1377 { 1378 struct drm_device *drm = vc4_hdmi->connector.dev; 1379 unsigned long flags; 1380 u32 drift; 1381 int ret; 1382 int idx; 1383 1384 if (!drm_dev_enter(drm, &idx)) 1385 return; 1386 1387 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1388 1389 drift = HDMI_READ(HDMI_FIFO_CTL); 1390 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1391 1392 HDMI_WRITE(HDMI_FIFO_CTL, 1393 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1394 HDMI_WRITE(HDMI_FIFO_CTL, 1395 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1396 1397 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1398 1399 usleep_range(1000, 1100); 1400 1401 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1402 1403 HDMI_WRITE(HDMI_FIFO_CTL, 1404 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1405 HDMI_WRITE(HDMI_FIFO_CTL, 1406 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1407 1408 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1409 1410 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1411 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1412 WARN_ONCE(ret, "Timeout waiting for " 1413 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1414 1415 drm_dev_exit(idx); 1416 } 1417 1418 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1419 struct drm_atomic_state *state) 1420 { 1421 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1422 struct drm_device *drm = vc4_hdmi->connector.dev; 1423 struct drm_connector *connector = &vc4_hdmi->connector; 1424 struct drm_connector_state *conn_state = 1425 drm_atomic_get_new_connector_state(state, connector); 1426 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1427 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate; 1428 unsigned long bvb_rate, hsm_rate; 1429 unsigned long flags; 1430 int ret; 1431 int idx; 1432 1433 mutex_lock(&vc4_hdmi->mutex); 1434 1435 if (!drm_dev_enter(drm, &idx)) 1436 goto out; 1437 1438 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1439 if (ret < 0) { 1440 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1441 goto err_dev_exit; 1442 } 1443 1444 /* 1445 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1446 * be faster than pixel clock, infinitesimally faster, tested in 1447 * simulation. Otherwise, exact value is unimportant for HDMI 1448 * operation." This conflicts with bcm2835's vc4 documentation, which 1449 * states HSM's clock has to be at least 108% of the pixel clock. 1450 * 1451 * Real life tests reveal that vc4's firmware statement holds up, and 1452 * users are able to use pixel clocks closer to HSM's, namely for 1453 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1454 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1455 * 162MHz. 1456 * 1457 * Additionally, the AXI clock needs to be at least 25% of 1458 * pixel clock, but HSM ends up being the limiting factor. 1459 */ 1460 hsm_rate = max_t(unsigned long, 1461 HSM_MIN_CLOCK_FREQ, 1462 div_u64(tmds_char_rate, 100) * 101); 1463 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1464 if (ret) { 1465 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1466 goto err_put_runtime_pm; 1467 } 1468 1469 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1470 if (ret) { 1471 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1472 goto err_put_runtime_pm; 1473 } 1474 1475 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1476 if (ret) { 1477 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1478 goto err_put_runtime_pm; 1479 } 1480 1481 1482 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1483 1484 if (tmds_char_rate > 297000000) 1485 bvb_rate = 300000000; 1486 else if (tmds_char_rate > 148500000) 1487 bvb_rate = 150000000; 1488 else 1489 bvb_rate = 75000000; 1490 1491 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1492 if (ret) { 1493 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1494 goto err_disable_pixel_clock; 1495 } 1496 1497 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1498 if (ret) { 1499 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1500 goto err_disable_pixel_clock; 1501 } 1502 1503 if (vc4_hdmi->variant->phy_init) 1504 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state); 1505 1506 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1507 1508 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1509 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1510 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1511 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1512 1513 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1514 1515 if (vc4_hdmi->variant->set_timings) 1516 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1517 1518 drm_dev_exit(idx); 1519 1520 mutex_unlock(&vc4_hdmi->mutex); 1521 1522 return; 1523 1524 err_disable_pixel_clock: 1525 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1526 err_put_runtime_pm: 1527 pm_runtime_put(&vc4_hdmi->pdev->dev); 1528 err_dev_exit: 1529 drm_dev_exit(idx); 1530 out: 1531 mutex_unlock(&vc4_hdmi->mutex); 1532 return; 1533 } 1534 1535 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1536 struct drm_atomic_state *state) 1537 { 1538 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1539 struct drm_device *drm = vc4_hdmi->connector.dev; 1540 struct drm_connector *connector = &vc4_hdmi->connector; 1541 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1542 struct drm_connector_state *conn_state = 1543 drm_atomic_get_new_connector_state(state, connector); 1544 unsigned long flags; 1545 int idx; 1546 1547 mutex_lock(&vc4_hdmi->mutex); 1548 1549 if (!drm_dev_enter(drm, &idx)) 1550 goto out; 1551 1552 if (vc4_hdmi->variant->csc_setup) 1553 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1554 1555 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1556 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1557 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1558 1559 drm_dev_exit(idx); 1560 1561 out: 1562 mutex_unlock(&vc4_hdmi->mutex); 1563 } 1564 1565 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1566 struct drm_atomic_state *state) 1567 { 1568 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1569 struct drm_connector *connector = &vc4_hdmi->connector; 1570 struct drm_device *drm = connector->dev; 1571 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1572 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1573 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1574 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1575 unsigned long flags; 1576 int ret; 1577 int idx; 1578 1579 mutex_lock(&vc4_hdmi->mutex); 1580 1581 if (!drm_dev_enter(drm, &idx)) 1582 goto out; 1583 1584 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1585 1586 HDMI_WRITE(HDMI_VID_CTL, 1587 VC4_HD_VID_CTL_ENABLE | 1588 VC4_HD_VID_CTL_CLRRGB | 1589 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1590 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1591 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1592 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1593 1594 HDMI_WRITE(HDMI_VID_CTL, 1595 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1596 1597 if (display->is_hdmi) { 1598 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1599 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1600 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1601 1602 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1603 1604 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1605 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1606 WARN_ONCE(ret, "Timeout waiting for " 1607 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1608 } else { 1609 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1610 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1611 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1612 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1613 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1614 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1615 1616 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1617 1618 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1619 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1620 WARN_ONCE(ret, "Timeout waiting for " 1621 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1622 } 1623 1624 if (display->is_hdmi) { 1625 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1626 1627 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1628 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1629 1630 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1631 VC4_HDMI_RAM_PACKET_ENABLE); 1632 1633 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1634 vc4_hdmi->packet_ram_enabled = true; 1635 1636 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 1637 } 1638 1639 vc4_hdmi_recenter_fifo(vc4_hdmi); 1640 vc4_hdmi_enable_scrambling(encoder); 1641 1642 drm_dev_exit(idx); 1643 1644 out: 1645 mutex_unlock(&vc4_hdmi->mutex); 1646 } 1647 1648 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1649 struct drm_crtc_state *crtc_state, 1650 struct drm_connector_state *conn_state) 1651 { 1652 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1653 1654 mutex_lock(&vc4_hdmi->mutex); 1655 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1656 &crtc_state->adjusted_mode); 1657 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc; 1658 vc4_hdmi->output_format = conn_state->hdmi.output_format; 1659 mutex_unlock(&vc4_hdmi->mutex); 1660 } 1661 1662 static enum drm_mode_status 1663 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector, 1664 const struct drm_display_mode *mode, 1665 unsigned long long clock) 1666 { 1667 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1668 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 1669 1670 if (clock > vc4_hdmi->variant->max_pixel_clock) 1671 return MODE_CLOCK_HIGH; 1672 1673 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 1674 return MODE_CLOCK_HIGH; 1675 1676 /* 4096x2160@60 is not reliable without overclocking core */ 1677 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 1678 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 1679 drm_mode_vrefresh(mode) >= 50) 1680 return MODE_CLOCK_HIGH; 1681 1682 return MODE_OK; 1683 } 1684 1685 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = { 1686 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid, 1687 .write_infoframe = vc4_hdmi_write_infoframe, 1688 }; 1689 1690 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1691 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1692 1693 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1694 struct drm_crtc_state *crtc_state, 1695 struct drm_connector_state *conn_state) 1696 { 1697 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1698 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1699 unsigned long long tmds_char_rate = mode->clock * 1000; 1700 unsigned long long tmds_bit_rate; 1701 1702 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1703 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1704 /* Only try to fixup DBLCLK modes to get 480i and 576i 1705 * working. 1706 * A generic solution for all modes with odd horizontal 1707 * timing values seems impossible based on trying to 1708 * solve it for 1366x768 monitors. 1709 */ 1710 if ((mode->hsync_start - mode->hdisplay) & 1) 1711 mode->hsync_start--; 1712 if ((mode->hsync_end - mode->hsync_start) & 1) 1713 mode->hsync_end--; 1714 } 1715 1716 /* Now check whether we still have odd values remaining */ 1717 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1718 (mode->hsync_end % 2) || (mode->htotal % 2)) 1719 return -EINVAL; 1720 } 1721 1722 /* 1723 * The 1440p@60 pixel rate is in the same range than the first 1724 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1725 * bandwidth). Slightly lower the frequency to bring it out of 1726 * the WiFi range. 1727 */ 1728 tmds_bit_rate = tmds_char_rate * 10; 1729 if (vc4_hdmi->disable_wifi_frequencies && 1730 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1731 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1732 mode->clock = 238560; 1733 tmds_char_rate = mode->clock * 1000; 1734 } 1735 1736 return 0; 1737 } 1738 1739 static enum drm_mode_status 1740 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1741 const struct drm_display_mode *mode) 1742 { 1743 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1744 unsigned long long rate; 1745 1746 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1747 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1748 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1749 (mode->hsync_end % 2) || (mode->htotal % 2))) 1750 return MODE_H_ILLEGAL; 1751 1752 rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB); 1753 return vc4_hdmi_connector_clock_valid(&vc4_hdmi->connector, mode, rate); 1754 } 1755 1756 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1757 .atomic_check = vc4_hdmi_encoder_atomic_check, 1758 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1759 .mode_valid = vc4_hdmi_encoder_mode_valid, 1760 }; 1761 1762 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 1763 { 1764 struct drm_device *drm = encoder->dev; 1765 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1766 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1767 1768 drm_debugfs_add_file(drm, variant->debugfs_name, 1769 vc4_hdmi_debugfs_regs, vc4_hdmi); 1770 1771 return 0; 1772 } 1773 1774 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 1775 .late_register = vc4_hdmi_late_register, 1776 }; 1777 1778 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1779 { 1780 int i; 1781 u32 channel_map = 0; 1782 1783 for (i = 0; i < 8; i++) { 1784 if (channel_mask & BIT(i)) 1785 channel_map |= i << (3 * i); 1786 } 1787 return channel_map; 1788 } 1789 1790 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1791 { 1792 int i; 1793 u32 channel_map = 0; 1794 1795 for (i = 0; i < 8; i++) { 1796 if (channel_mask & BIT(i)) 1797 channel_map |= i << (4 * i); 1798 } 1799 return channel_map; 1800 } 1801 1802 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1803 { 1804 struct drm_device *drm = vc4_hdmi->connector.dev; 1805 unsigned long flags; 1806 u32 hotplug; 1807 int idx; 1808 1809 if (!drm_dev_enter(drm, &idx)) 1810 return false; 1811 1812 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1813 hotplug = HDMI_READ(HDMI_HOTPLUG); 1814 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1815 1816 drm_dev_exit(idx); 1817 1818 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1819 } 1820 1821 /* HDMI audio codec callbacks */ 1822 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1823 unsigned int samplerate) 1824 { 1825 struct drm_device *drm = vc4_hdmi->connector.dev; 1826 u32 hsm_clock; 1827 unsigned long flags; 1828 unsigned long n, m; 1829 int idx; 1830 1831 if (!drm_dev_enter(drm, &idx)) 1832 return; 1833 1834 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1835 rational_best_approximation(hsm_clock, samplerate, 1836 VC4_HD_MAI_SMP_N_MASK >> 1837 VC4_HD_MAI_SMP_N_SHIFT, 1838 (VC4_HD_MAI_SMP_M_MASK >> 1839 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1840 &n, &m); 1841 1842 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1843 HDMI_WRITE(HDMI_MAI_SMP, 1844 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1845 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1846 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1847 1848 drm_dev_exit(idx); 1849 } 1850 1851 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1852 { 1853 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1854 u32 n, cts; 1855 u64 tmp; 1856 1857 lockdep_assert_held(&vc4_hdmi->mutex); 1858 lockdep_assert_held(&vc4_hdmi->hw_lock); 1859 1860 n = 128 * samplerate / 1000; 1861 tmp = (u64)(mode->clock * 1000) * n; 1862 do_div(tmp, 128 * samplerate); 1863 cts = tmp; 1864 1865 HDMI_WRITE(HDMI_CRP_CFG, 1866 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1867 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1868 1869 /* 1870 * We could get slightly more accurate clocks in some cases by 1871 * providing a CTS_1 value. The two CTS values are alternated 1872 * between based on the period fields 1873 */ 1874 HDMI_WRITE(HDMI_CTS_0, cts); 1875 HDMI_WRITE(HDMI_CTS_1, cts); 1876 } 1877 1878 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1879 { 1880 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1881 1882 return snd_soc_card_get_drvdata(card); 1883 } 1884 1885 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1886 { 1887 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1888 1889 lockdep_assert_held(&vc4_hdmi->mutex); 1890 1891 /* 1892 * If the encoder is currently in DVI mode, treat the codec DAI 1893 * as missing. 1894 */ 1895 if (!display->is_hdmi) 1896 return false; 1897 1898 return true; 1899 } 1900 1901 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1902 { 1903 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1904 struct drm_device *drm = vc4_hdmi->connector.dev; 1905 unsigned long flags; 1906 int ret = 0; 1907 int idx; 1908 1909 mutex_lock(&vc4_hdmi->mutex); 1910 1911 if (!drm_dev_enter(drm, &idx)) { 1912 ret = -ENODEV; 1913 goto out; 1914 } 1915 1916 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1917 ret = -ENODEV; 1918 goto out_dev_exit; 1919 } 1920 1921 vc4_hdmi->audio.streaming = true; 1922 1923 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1924 HDMI_WRITE(HDMI_MAI_CTL, 1925 VC4_HD_MAI_CTL_RESET | 1926 VC4_HD_MAI_CTL_FLUSH | 1927 VC4_HD_MAI_CTL_DLATE | 1928 VC4_HD_MAI_CTL_ERRORE | 1929 VC4_HD_MAI_CTL_ERRORF); 1930 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1931 1932 if (vc4_hdmi->variant->phy_rng_enable) 1933 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1934 1935 out_dev_exit: 1936 drm_dev_exit(idx); 1937 out: 1938 mutex_unlock(&vc4_hdmi->mutex); 1939 1940 return ret; 1941 } 1942 1943 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1944 { 1945 struct device *dev = &vc4_hdmi->pdev->dev; 1946 unsigned long flags; 1947 int ret; 1948 1949 lockdep_assert_held(&vc4_hdmi->mutex); 1950 1951 vc4_hdmi->audio.streaming = false; 1952 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false); 1953 if (ret) 1954 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1955 1956 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1957 1958 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1959 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1960 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1961 1962 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1963 } 1964 1965 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1966 { 1967 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1968 struct drm_device *drm = vc4_hdmi->connector.dev; 1969 unsigned long flags; 1970 int idx; 1971 1972 mutex_lock(&vc4_hdmi->mutex); 1973 1974 if (!drm_dev_enter(drm, &idx)) 1975 goto out; 1976 1977 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1978 1979 HDMI_WRITE(HDMI_MAI_CTL, 1980 VC4_HD_MAI_CTL_DLATE | 1981 VC4_HD_MAI_CTL_ERRORE | 1982 VC4_HD_MAI_CTL_ERRORF); 1983 1984 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1985 1986 if (vc4_hdmi->variant->phy_rng_disable) 1987 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1988 1989 vc4_hdmi->audio.streaming = false; 1990 vc4_hdmi_audio_reset(vc4_hdmi); 1991 1992 drm_dev_exit(idx); 1993 1994 out: 1995 mutex_unlock(&vc4_hdmi->mutex); 1996 } 1997 1998 static int sample_rate_to_mai_fmt(int samplerate) 1999 { 2000 switch (samplerate) { 2001 case 8000: 2002 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2003 case 11025: 2004 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2005 case 12000: 2006 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2007 case 16000: 2008 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2009 case 22050: 2010 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2011 case 24000: 2012 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2013 case 32000: 2014 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2015 case 44100: 2016 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2017 case 48000: 2018 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2019 case 64000: 2020 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2021 case 88200: 2022 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2023 case 96000: 2024 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2025 case 128000: 2026 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2027 case 176400: 2028 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2029 case 192000: 2030 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2031 default: 2032 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2033 } 2034 } 2035 2036 /* HDMI audio codec callbacks */ 2037 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 2038 struct hdmi_codec_daifmt *daifmt, 2039 struct hdmi_codec_params *params) 2040 { 2041 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2042 struct drm_device *drm = vc4_hdmi->connector.dev; 2043 struct drm_connector *connector = &vc4_hdmi->connector; 2044 unsigned int sample_rate = params->sample_rate; 2045 unsigned int channels = params->channels; 2046 unsigned long flags; 2047 u32 audio_packet_config, channel_mask; 2048 u32 channel_map; 2049 u32 mai_audio_format; 2050 u32 mai_sample_rate; 2051 int ret = 0; 2052 int idx; 2053 2054 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2055 sample_rate, params->sample_width, channels); 2056 2057 mutex_lock(&vc4_hdmi->mutex); 2058 2059 if (!drm_dev_enter(drm, &idx)) { 2060 ret = -ENODEV; 2061 goto out; 2062 } 2063 2064 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2065 ret = -EINVAL; 2066 goto out_dev_exit; 2067 } 2068 2069 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2070 2071 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2072 HDMI_WRITE(HDMI_MAI_CTL, 2073 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2074 VC4_HD_MAI_CTL_WHOLSMP | 2075 VC4_HD_MAI_CTL_CHALIGN | 2076 VC4_HD_MAI_CTL_ENABLE); 2077 2078 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2079 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2080 params->channels == 8) 2081 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2082 else 2083 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2084 HDMI_WRITE(HDMI_MAI_FMT, 2085 VC4_SET_FIELD(mai_sample_rate, 2086 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2087 VC4_SET_FIELD(mai_audio_format, 2088 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2089 2090 /* The B frame identifier should match the value used by alsa-lib (8) */ 2091 audio_packet_config = 2092 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2093 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2094 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2095 2096 channel_mask = GENMASK(channels - 1, 0); 2097 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2098 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2099 2100 /* Set the MAI threshold */ 2101 HDMI_WRITE(HDMI_MAI_THR, 2102 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) | 2103 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) | 2104 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) | 2105 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW)); 2106 2107 HDMI_WRITE(HDMI_MAI_CONFIG, 2108 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2109 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2110 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2111 2112 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2113 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2114 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2115 2116 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2117 2118 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2119 2120 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, 2121 ¶ms->cea); 2122 if (ret) 2123 goto out_dev_exit; 2124 2125 out_dev_exit: 2126 drm_dev_exit(idx); 2127 out: 2128 mutex_unlock(&vc4_hdmi->mutex); 2129 2130 return ret; 2131 } 2132 2133 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2134 .name = "vc4-hdmi-cpu-dai-component", 2135 .legacy_dai_naming = 1, 2136 }; 2137 2138 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2139 { 2140 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2141 2142 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2143 2144 return 0; 2145 } 2146 2147 static const struct snd_soc_dai_ops vc4_snd_dai_ops = { 2148 .probe = vc4_hdmi_audio_cpu_dai_probe, 2149 }; 2150 2151 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2152 .name = "vc4-hdmi-cpu-dai", 2153 .ops = &vc4_snd_dai_ops, 2154 .playback = { 2155 .stream_name = "Playback", 2156 .channels_min = 1, 2157 .channels_max = 8, 2158 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2159 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2160 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2161 SNDRV_PCM_RATE_192000, 2162 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2163 }, 2164 }; 2165 2166 static const struct snd_dmaengine_pcm_config pcm_conf = { 2167 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2168 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2169 }; 2170 2171 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2172 uint8_t *buf, size_t len) 2173 { 2174 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2175 struct drm_connector *connector = &vc4_hdmi->connector; 2176 2177 mutex_lock(&vc4_hdmi->mutex); 2178 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2179 mutex_unlock(&vc4_hdmi->mutex); 2180 2181 return 0; 2182 } 2183 2184 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2185 .get_eld = vc4_hdmi_audio_get_eld, 2186 .prepare = vc4_hdmi_audio_prepare, 2187 .audio_shutdown = vc4_hdmi_audio_shutdown, 2188 .audio_startup = vc4_hdmi_audio_startup, 2189 }; 2190 2191 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2192 .ops = &vc4_hdmi_codec_ops, 2193 .max_i2s_channels = 8, 2194 .i2s = 1, 2195 }; 2196 2197 static void vc4_hdmi_audio_codec_release(void *ptr) 2198 { 2199 struct vc4_hdmi *vc4_hdmi = ptr; 2200 2201 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 2202 vc4_hdmi->audio.codec_pdev = NULL; 2203 } 2204 2205 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2206 { 2207 const struct vc4_hdmi_register *mai_data = 2208 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2209 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2210 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2211 struct device *dev = &vc4_hdmi->pdev->dev; 2212 struct platform_device *codec_pdev; 2213 const __be32 *addr; 2214 int index, len; 2215 int ret; 2216 2217 /* 2218 * ASoC makes it a bit hard to retrieve a pointer to the 2219 * vc4_hdmi structure. Registering the card will overwrite our 2220 * device drvdata with a pointer to the snd_soc_card structure, 2221 * which can then be used to retrieve whatever drvdata we want 2222 * to associate. 2223 * 2224 * However, that doesn't fly in the case where we wouldn't 2225 * register an ASoC card (because of an old DT that is missing 2226 * the dmas properties for example), then the card isn't 2227 * registered and the device drvdata wouldn't be set. 2228 * 2229 * We can deal with both cases by making sure a snd_soc_card 2230 * pointer and a vc4_hdmi structure are pointing to the same 2231 * memory address, so we can treat them indistinctly without any 2232 * issue. 2233 */ 2234 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2235 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2236 2237 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2238 dev_warn(dev, 2239 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2240 return 0; 2241 } 2242 2243 if (mai_data->reg != VC4_HD) { 2244 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2245 return -EINVAL; 2246 } 2247 2248 /* 2249 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2250 * the bus address specified in the DT, because the physical address 2251 * (the one returned by platform_get_resource()) is not appropriate 2252 * for DMA transfers. 2253 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2254 */ 2255 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2256 /* Before BCM2711, we don't have a named register range */ 2257 if (index < 0) 2258 index = 1; 2259 2260 addr = of_get_address(dev->of_node, index, NULL, NULL); 2261 if (!addr) 2262 return -EINVAL; 2263 2264 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2265 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2266 vc4_hdmi->audio.dma_data.maxburst = 2; 2267 2268 /* 2269 * NOTE: Strictly speaking, we should probably use a DRM-managed 2270 * registration there to avoid removing all the audio components 2271 * by the time the driver doesn't have any user anymore. 2272 * 2273 * However, the ASoC core uses a number of devm_kzalloc calls 2274 * when registering, even when using non-device-managed 2275 * functions (such as in snd_soc_register_component()). 2276 * 2277 * If we call snd_soc_unregister_component() in a DRM-managed 2278 * action, the device-managed actions have already been executed 2279 * and thus we would access memory that has been freed. 2280 * 2281 * Using device-managed hooks here probably leaves us open to a 2282 * bunch of issues if userspace still has a handle on the ALSA 2283 * device when the device is removed. However, this is mitigated 2284 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2285 * path to prevent the access to the device resources if it 2286 * isn't there anymore. 2287 * 2288 * Then, the vc4_hdmi structure is DRM-managed and thus only 2289 * freed whenever the last user has closed the DRM device file. 2290 * It should thus outlive ALSA in most situations. 2291 */ 2292 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2293 if (ret) { 2294 dev_err(dev, "Could not register PCM component: %d\n", ret); 2295 return ret; 2296 } 2297 2298 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2299 &vc4_hdmi_audio_cpu_dai_drv, 1); 2300 if (ret) { 2301 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2302 return ret; 2303 } 2304 2305 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2306 PLATFORM_DEVID_AUTO, 2307 &vc4_hdmi_codec_pdata, 2308 sizeof(vc4_hdmi_codec_pdata)); 2309 if (IS_ERR(codec_pdev)) { 2310 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2311 return PTR_ERR(codec_pdev); 2312 } 2313 vc4_hdmi->audio.codec_pdev = codec_pdev; 2314 2315 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi); 2316 if (ret) 2317 return ret; 2318 2319 dai_link->cpus = &vc4_hdmi->audio.cpu; 2320 dai_link->codecs = &vc4_hdmi->audio.codec; 2321 dai_link->platforms = &vc4_hdmi->audio.platform; 2322 2323 dai_link->num_cpus = 1; 2324 dai_link->num_codecs = 1; 2325 dai_link->num_platforms = 1; 2326 2327 dai_link->name = "MAI"; 2328 dai_link->stream_name = "MAI PCM"; 2329 dai_link->codecs->dai_name = "i2s-hifi"; 2330 dai_link->cpus->dai_name = dev_name(dev); 2331 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2332 dai_link->platforms->name = dev_name(dev); 2333 2334 card->dai_link = dai_link; 2335 card->num_links = 1; 2336 card->name = vc4_hdmi->variant->card_name; 2337 card->driver_name = "vc4-hdmi"; 2338 card->dev = dev; 2339 card->owner = THIS_MODULE; 2340 2341 /* 2342 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2343 * stores a pointer to the snd card object in dev->driver_data. This 2344 * means we cannot use it for something else. The hdmi back-pointer is 2345 * now stored in card->drvdata and should be retrieved with 2346 * snd_soc_card_get_drvdata() if needed. 2347 */ 2348 snd_soc_card_set_drvdata(card, vc4_hdmi); 2349 ret = devm_snd_soc_register_card(dev, card); 2350 if (ret) 2351 dev_err_probe(dev, ret, "Could not register sound card\n"); 2352 2353 return ret; 2354 2355 } 2356 2357 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2358 { 2359 struct vc4_hdmi *vc4_hdmi = priv; 2360 struct drm_connector *connector = &vc4_hdmi->connector; 2361 struct drm_device *dev = connector->dev; 2362 2363 if (dev && dev->registered) 2364 drm_connector_helper_hpd_irq_event(connector); 2365 2366 return IRQ_HANDLED; 2367 } 2368 2369 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2370 { 2371 struct drm_connector *connector = &vc4_hdmi->connector; 2372 struct platform_device *pdev = vc4_hdmi->pdev; 2373 int ret; 2374 2375 if (vc4_hdmi->variant->external_irq_controller) { 2376 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2377 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2378 2379 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2380 NULL, 2381 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2382 "vc4 hdmi hpd connected", vc4_hdmi); 2383 if (ret) 2384 return ret; 2385 2386 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2387 NULL, 2388 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2389 "vc4 hdmi hpd disconnected", vc4_hdmi); 2390 if (ret) 2391 return ret; 2392 2393 connector->polled = DRM_CONNECTOR_POLL_HPD; 2394 } 2395 2396 return 0; 2397 } 2398 2399 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2400 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2401 { 2402 struct vc4_hdmi *vc4_hdmi = priv; 2403 2404 if (vc4_hdmi->cec_rx_msg.len) 2405 cec_received_msg(vc4_hdmi->cec_adap, 2406 &vc4_hdmi->cec_rx_msg); 2407 2408 return IRQ_HANDLED; 2409 } 2410 2411 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2412 { 2413 struct vc4_hdmi *vc4_hdmi = priv; 2414 2415 if (vc4_hdmi->cec_tx_ok) { 2416 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2417 0, 0, 0, 0); 2418 } else { 2419 /* 2420 * This CEC implementation makes 1 retry, so if we 2421 * get a NACK, then that means it made 2 attempts. 2422 */ 2423 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2424 0, 2, 0, 0); 2425 } 2426 return IRQ_HANDLED; 2427 } 2428 2429 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2430 { 2431 struct vc4_hdmi *vc4_hdmi = priv; 2432 irqreturn_t ret; 2433 2434 if (vc4_hdmi->cec_irq_was_rx) 2435 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2436 else 2437 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2438 2439 return ret; 2440 } 2441 2442 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2443 { 2444 struct drm_device *dev = vc4_hdmi->connector.dev; 2445 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2446 unsigned int i; 2447 2448 lockdep_assert_held(&vc4_hdmi->hw_lock); 2449 2450 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2451 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2452 2453 if (msg->len > 16) { 2454 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2455 return; 2456 } 2457 2458 for (i = 0; i < msg->len; i += 4) { 2459 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2460 2461 msg->msg[i] = val & 0xff; 2462 msg->msg[i + 1] = (val >> 8) & 0xff; 2463 msg->msg[i + 2] = (val >> 16) & 0xff; 2464 msg->msg[i + 3] = (val >> 24) & 0xff; 2465 } 2466 } 2467 2468 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2469 { 2470 u32 cntrl1; 2471 2472 /* 2473 * We don't need to protect the register access using 2474 * drm_dev_enter() there because the interrupt handler lifetime 2475 * is tied to the device itself, and not to the DRM device. 2476 * 2477 * So when the device will be gone, one of the first thing we 2478 * will be doing will be to unregister the interrupt handler, 2479 * and then unregister the DRM device. drm_dev_enter() would 2480 * thus always succeed if we are here. 2481 */ 2482 2483 lockdep_assert_held(&vc4_hdmi->hw_lock); 2484 2485 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2486 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2487 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2488 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2489 2490 return IRQ_WAKE_THREAD; 2491 } 2492 2493 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2494 { 2495 struct vc4_hdmi *vc4_hdmi = priv; 2496 irqreturn_t ret; 2497 2498 spin_lock(&vc4_hdmi->hw_lock); 2499 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2500 spin_unlock(&vc4_hdmi->hw_lock); 2501 2502 return ret; 2503 } 2504 2505 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2506 { 2507 u32 cntrl1; 2508 2509 lockdep_assert_held(&vc4_hdmi->hw_lock); 2510 2511 /* 2512 * We don't need to protect the register access using 2513 * drm_dev_enter() there because the interrupt handler lifetime 2514 * is tied to the device itself, and not to the DRM device. 2515 * 2516 * So when the device will be gone, one of the first thing we 2517 * will be doing will be to unregister the interrupt handler, 2518 * and then unregister the DRM device. drm_dev_enter() would 2519 * thus always succeed if we are here. 2520 */ 2521 2522 vc4_hdmi->cec_rx_msg.len = 0; 2523 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2524 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2525 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2526 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2527 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2528 2529 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2530 2531 return IRQ_WAKE_THREAD; 2532 } 2533 2534 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2535 { 2536 struct vc4_hdmi *vc4_hdmi = priv; 2537 irqreturn_t ret; 2538 2539 spin_lock(&vc4_hdmi->hw_lock); 2540 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2541 spin_unlock(&vc4_hdmi->hw_lock); 2542 2543 return ret; 2544 } 2545 2546 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2547 { 2548 struct vc4_hdmi *vc4_hdmi = priv; 2549 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2550 irqreturn_t ret; 2551 u32 cntrl5; 2552 2553 /* 2554 * We don't need to protect the register access using 2555 * drm_dev_enter() there because the interrupt handler lifetime 2556 * is tied to the device itself, and not to the DRM device. 2557 * 2558 * So when the device will be gone, one of the first thing we 2559 * will be doing will be to unregister the interrupt handler, 2560 * and then unregister the DRM device. drm_dev_enter() would 2561 * thus always succeed if we are here. 2562 */ 2563 2564 if (!(stat & VC4_HDMI_CPU_CEC)) 2565 return IRQ_NONE; 2566 2567 spin_lock(&vc4_hdmi->hw_lock); 2568 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2569 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2570 if (vc4_hdmi->cec_irq_was_rx) 2571 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2572 else 2573 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2574 2575 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2576 spin_unlock(&vc4_hdmi->hw_lock); 2577 2578 return ret; 2579 } 2580 2581 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2582 { 2583 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2584 struct drm_device *drm = vc4_hdmi->connector.dev; 2585 /* clock period in microseconds */ 2586 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2587 unsigned long flags; 2588 u32 val; 2589 int ret; 2590 int idx; 2591 2592 if (!drm_dev_enter(drm, &idx)) 2593 /* 2594 * We can't return an error code, because the CEC 2595 * framework will emit WARN_ON messages at unbind 2596 * otherwise. 2597 */ 2598 return 0; 2599 2600 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2601 if (ret) { 2602 drm_dev_exit(idx); 2603 return ret; 2604 } 2605 2606 mutex_lock(&vc4_hdmi->mutex); 2607 2608 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2609 2610 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2611 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2612 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2613 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2614 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2615 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2616 2617 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2618 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2619 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2620 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2621 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2622 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2623 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2624 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2625 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2626 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2627 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2628 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2629 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2630 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2631 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2632 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2633 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2634 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2635 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2636 2637 if (!vc4_hdmi->variant->external_irq_controller) 2638 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2639 2640 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2641 2642 mutex_unlock(&vc4_hdmi->mutex); 2643 drm_dev_exit(idx); 2644 2645 return 0; 2646 } 2647 2648 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2649 { 2650 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2651 struct drm_device *drm = vc4_hdmi->connector.dev; 2652 unsigned long flags; 2653 int idx; 2654 2655 if (!drm_dev_enter(drm, &idx)) 2656 /* 2657 * We can't return an error code, because the CEC 2658 * framework will emit WARN_ON messages at unbind 2659 * otherwise. 2660 */ 2661 return 0; 2662 2663 mutex_lock(&vc4_hdmi->mutex); 2664 2665 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2666 2667 if (!vc4_hdmi->variant->external_irq_controller) 2668 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2669 2670 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2671 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2672 2673 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2674 2675 mutex_unlock(&vc4_hdmi->mutex); 2676 2677 pm_runtime_put(&vc4_hdmi->pdev->dev); 2678 2679 drm_dev_exit(idx); 2680 2681 return 0; 2682 } 2683 2684 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2685 { 2686 if (enable) 2687 return vc4_hdmi_cec_enable(adap); 2688 else 2689 return vc4_hdmi_cec_disable(adap); 2690 } 2691 2692 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2693 { 2694 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2695 struct drm_device *drm = vc4_hdmi->connector.dev; 2696 unsigned long flags; 2697 int idx; 2698 2699 if (!drm_dev_enter(drm, &idx)) 2700 /* 2701 * We can't return an error code, because the CEC 2702 * framework will emit WARN_ON messages at unbind 2703 * otherwise. 2704 */ 2705 return 0; 2706 2707 mutex_lock(&vc4_hdmi->mutex); 2708 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2709 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2710 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2711 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2712 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2713 mutex_unlock(&vc4_hdmi->mutex); 2714 2715 drm_dev_exit(idx); 2716 2717 return 0; 2718 } 2719 2720 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2721 u32 signal_free_time, struct cec_msg *msg) 2722 { 2723 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2724 struct drm_device *dev = vc4_hdmi->connector.dev; 2725 unsigned long flags; 2726 u32 val; 2727 unsigned int i; 2728 int idx; 2729 2730 if (!drm_dev_enter(dev, &idx)) 2731 return -ENODEV; 2732 2733 if (msg->len > 16) { 2734 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2735 drm_dev_exit(idx); 2736 return -ENOMEM; 2737 } 2738 2739 mutex_lock(&vc4_hdmi->mutex); 2740 2741 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2742 2743 for (i = 0; i < msg->len; i += 4) 2744 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2745 (msg->msg[i]) | 2746 (msg->msg[i + 1] << 8) | 2747 (msg->msg[i + 2] << 16) | 2748 (msg->msg[i + 3] << 24)); 2749 2750 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2751 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2752 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2753 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2754 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2755 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2756 2757 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2758 2759 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2760 mutex_unlock(&vc4_hdmi->mutex); 2761 drm_dev_exit(idx); 2762 2763 return 0; 2764 } 2765 2766 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2767 .adap_enable = vc4_hdmi_cec_adap_enable, 2768 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2769 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2770 }; 2771 2772 static void vc4_hdmi_cec_release(void *ptr) 2773 { 2774 struct vc4_hdmi *vc4_hdmi = ptr; 2775 2776 cec_unregister_adapter(vc4_hdmi->cec_adap); 2777 vc4_hdmi->cec_adap = NULL; 2778 } 2779 2780 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2781 { 2782 struct cec_connector_info conn_info; 2783 struct platform_device *pdev = vc4_hdmi->pdev; 2784 struct device *dev = &pdev->dev; 2785 int ret; 2786 2787 if (!of_property_present(dev->of_node, "interrupts")) { 2788 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2789 return 0; 2790 } 2791 2792 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2793 vc4_hdmi, 2794 vc4_hdmi->variant->card_name, 2795 CEC_CAP_DEFAULTS | 2796 CEC_CAP_CONNECTOR_INFO, 1); 2797 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2798 if (ret < 0) 2799 return ret; 2800 2801 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2802 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2803 2804 if (vc4_hdmi->variant->external_irq_controller) { 2805 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 2806 vc4_cec_irq_handler_rx_bare, 2807 vc4_cec_irq_handler_rx_thread, 0, 2808 "vc4 hdmi cec rx", vc4_hdmi); 2809 if (ret) 2810 goto err_delete_cec_adap; 2811 2812 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 2813 vc4_cec_irq_handler_tx_bare, 2814 vc4_cec_irq_handler_tx_thread, 0, 2815 "vc4 hdmi cec tx", vc4_hdmi); 2816 if (ret) 2817 goto err_delete_cec_adap; 2818 } else { 2819 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 2820 vc4_cec_irq_handler, 2821 vc4_cec_irq_handler_thread, 0, 2822 "vc4 hdmi cec", vc4_hdmi); 2823 if (ret) 2824 goto err_delete_cec_adap; 2825 } 2826 2827 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2828 if (ret < 0) 2829 goto err_delete_cec_adap; 2830 2831 /* 2832 * NOTE: Strictly speaking, we should probably use a DRM-managed 2833 * registration there to avoid removing the CEC adapter by the 2834 * time the DRM driver doesn't have any user anymore. 2835 * 2836 * However, the CEC framework already cleans up the CEC adapter 2837 * only when the last user has closed its file descriptor, so we 2838 * don't need to handle it in DRM. 2839 * 2840 * By the time the device-managed hook is executed, we will give 2841 * up our reference to the CEC adapter and therefore don't 2842 * really care when it's actually freed. 2843 * 2844 * There's still a problematic sequence: if we unregister our 2845 * CEC adapter, but the userspace keeps a handle on the CEC 2846 * adapter but not the DRM device for some reason. In such a 2847 * case, our vc4_hdmi structure will be freed, but the 2848 * cec_adapter structure will have a dangling pointer to what 2849 * used to be our HDMI controller. If we get a CEC call at that 2850 * moment, we could end up with a use-after-free. Fortunately, 2851 * the CEC framework already handles this too, by calling 2852 * cec_is_registered() in cec_ioctl() and cec_poll(). 2853 */ 2854 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi); 2855 if (ret) 2856 return ret; 2857 2858 return 0; 2859 2860 err_delete_cec_adap: 2861 cec_delete_adapter(vc4_hdmi->cec_adap); 2862 2863 return ret; 2864 } 2865 #else 2866 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2867 { 2868 return 0; 2869 } 2870 #endif 2871 2872 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 2873 { 2874 struct debugfs_reg32 *regs = ptr; 2875 2876 kfree(regs); 2877 } 2878 2879 static int vc4_hdmi_build_regset(struct drm_device *drm, 2880 struct vc4_hdmi *vc4_hdmi, 2881 struct debugfs_regset32 *regset, 2882 enum vc4_hdmi_regs reg) 2883 { 2884 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2885 struct debugfs_reg32 *regs, *new_regs; 2886 unsigned int count = 0; 2887 unsigned int i; 2888 int ret; 2889 2890 regs = kcalloc(variant->num_registers, sizeof(*regs), 2891 GFP_KERNEL); 2892 if (!regs) 2893 return -ENOMEM; 2894 2895 for (i = 0; i < variant->num_registers; i++) { 2896 const struct vc4_hdmi_register *field = &variant->registers[i]; 2897 2898 if (field->reg != reg) 2899 continue; 2900 2901 regs[count].name = field->name; 2902 regs[count].offset = field->offset; 2903 count++; 2904 } 2905 2906 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2907 if (!new_regs) 2908 return -ENOMEM; 2909 2910 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2911 regset->regs = new_regs; 2912 regset->nregs = count; 2913 2914 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 2915 if (ret) 2916 return ret; 2917 2918 return 0; 2919 } 2920 2921 static int vc4_hdmi_init_resources(struct drm_device *drm, 2922 struct vc4_hdmi *vc4_hdmi) 2923 { 2924 struct platform_device *pdev = vc4_hdmi->pdev; 2925 struct device *dev = &pdev->dev; 2926 int ret; 2927 2928 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2929 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2930 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2931 2932 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2933 if (IS_ERR(vc4_hdmi->hd_regs)) 2934 return PTR_ERR(vc4_hdmi->hd_regs); 2935 2936 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2937 if (ret) 2938 return ret; 2939 2940 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2941 if (ret) 2942 return ret; 2943 2944 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2945 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2946 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2947 if (ret != -EPROBE_DEFER) 2948 DRM_ERROR("Failed to get pixel clock\n"); 2949 return ret; 2950 } 2951 2952 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2953 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2954 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2955 return PTR_ERR(vc4_hdmi->hsm_clock); 2956 } 2957 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2958 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2959 2960 return 0; 2961 } 2962 2963 static int vc5_hdmi_init_resources(struct drm_device *drm, 2964 struct vc4_hdmi *vc4_hdmi) 2965 { 2966 struct platform_device *pdev = vc4_hdmi->pdev; 2967 struct device *dev = &pdev->dev; 2968 struct resource *res; 2969 int ret; 2970 2971 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2972 if (!res) 2973 return -ENODEV; 2974 2975 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2976 resource_size(res)); 2977 if (!vc4_hdmi->hdmicore_regs) 2978 return -ENOMEM; 2979 2980 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2981 if (!res) 2982 return -ENODEV; 2983 2984 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2985 if (!vc4_hdmi->hd_regs) 2986 return -ENOMEM; 2987 2988 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2989 if (!res) 2990 return -ENODEV; 2991 2992 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2993 if (!vc4_hdmi->cec_regs) 2994 return -ENOMEM; 2995 2996 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2997 if (!res) 2998 return -ENODEV; 2999 3000 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 3001 if (!vc4_hdmi->csc_regs) 3002 return -ENOMEM; 3003 3004 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 3005 if (!res) 3006 return -ENODEV; 3007 3008 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 3009 if (!vc4_hdmi->dvp_regs) 3010 return -ENOMEM; 3011 3012 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 3013 if (!res) 3014 return -ENODEV; 3015 3016 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 3017 if (!vc4_hdmi->phy_regs) 3018 return -ENOMEM; 3019 3020 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 3021 if (!res) 3022 return -ENODEV; 3023 3024 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 3025 if (!vc4_hdmi->ram_regs) 3026 return -ENOMEM; 3027 3028 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 3029 if (!res) 3030 return -ENODEV; 3031 3032 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 3033 if (!vc4_hdmi->rm_regs) 3034 return -ENOMEM; 3035 3036 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3037 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3038 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3039 return PTR_ERR(vc4_hdmi->hsm_clock); 3040 } 3041 3042 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3043 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3044 DRM_ERROR("Failed to get pixel bvb clock\n"); 3045 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3046 } 3047 3048 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3049 if (IS_ERR(vc4_hdmi->audio_clock)) { 3050 DRM_ERROR("Failed to get audio clock\n"); 3051 return PTR_ERR(vc4_hdmi->audio_clock); 3052 } 3053 3054 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3055 if (IS_ERR(vc4_hdmi->cec_clock)) { 3056 DRM_ERROR("Failed to get CEC clock\n"); 3057 return PTR_ERR(vc4_hdmi->cec_clock); 3058 } 3059 3060 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3061 if (IS_ERR(vc4_hdmi->reset)) { 3062 DRM_ERROR("Failed to get HDMI reset line\n"); 3063 return PTR_ERR(vc4_hdmi->reset); 3064 } 3065 3066 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3067 if (ret) 3068 return ret; 3069 3070 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3071 if (ret) 3072 return ret; 3073 3074 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3075 if (ret) 3076 return ret; 3077 3078 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3079 if (ret) 3080 return ret; 3081 3082 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3083 if (ret) 3084 return ret; 3085 3086 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3087 if (ret) 3088 return ret; 3089 3090 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3091 if (ret) 3092 return ret; 3093 3094 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3095 if (ret) 3096 return ret; 3097 3098 return 0; 3099 } 3100 3101 static int vc4_hdmi_runtime_suspend(struct device *dev) 3102 { 3103 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3104 3105 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3106 3107 return 0; 3108 } 3109 3110 static int vc4_hdmi_runtime_resume(struct device *dev) 3111 { 3112 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3113 unsigned long __maybe_unused flags; 3114 u32 __maybe_unused value; 3115 unsigned long rate; 3116 int ret; 3117 3118 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3119 if (ret) 3120 return ret; 3121 3122 /* 3123 * Whenever the RaspberryPi boots without an HDMI monitor 3124 * plugged in, the firmware won't have initialized the HSM clock 3125 * rate and it will be reported as 0. 3126 * 3127 * If we try to access a register of the controller in such a 3128 * case, it will lead to a silent CPU stall. Let's make sure we 3129 * prevent such a case. 3130 */ 3131 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3132 if (!rate) { 3133 ret = -EINVAL; 3134 goto err_disable_clk; 3135 } 3136 3137 if (vc4_hdmi->variant->reset) 3138 vc4_hdmi->variant->reset(vc4_hdmi); 3139 3140 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3141 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3142 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3143 /* Set the logical address to Unregistered */ 3144 value |= VC4_HDMI_CEC_ADDR_MASK; 3145 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3146 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3147 3148 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3149 3150 if (!vc4_hdmi->variant->external_irq_controller) { 3151 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3152 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3153 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3154 } 3155 #endif 3156 3157 return 0; 3158 3159 err_disable_clk: 3160 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3161 return ret; 3162 } 3163 3164 static void vc4_hdmi_put_ddc_device(void *ptr) 3165 { 3166 struct vc4_hdmi *vc4_hdmi = ptr; 3167 3168 put_device(&vc4_hdmi->ddc->dev); 3169 } 3170 3171 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3172 { 3173 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3174 struct platform_device *pdev = to_platform_device(dev); 3175 struct drm_device *drm = dev_get_drvdata(master); 3176 struct vc4_hdmi *vc4_hdmi; 3177 struct drm_encoder *encoder; 3178 struct device_node *ddc_node; 3179 int ret; 3180 3181 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3182 if (!vc4_hdmi) 3183 return -ENOMEM; 3184 3185 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3186 if (ret) 3187 return ret; 3188 3189 spin_lock_init(&vc4_hdmi->hw_lock); 3190 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3191 3192 dev_set_drvdata(dev, vc4_hdmi); 3193 encoder = &vc4_hdmi->encoder.base; 3194 vc4_hdmi->encoder.type = variant->encoder_type; 3195 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3196 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3197 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3198 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3199 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3200 vc4_hdmi->pdev = pdev; 3201 vc4_hdmi->variant = variant; 3202 3203 /* 3204 * Since we don't know the state of the controller and its 3205 * display (if any), let's assume it's always enabled. 3206 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3207 * sure it's disabled, and avoid any inconsistency. 3208 */ 3209 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3210 vc4_hdmi->scdc_enabled = true; 3211 3212 ret = variant->init_resources(drm, vc4_hdmi); 3213 if (ret) 3214 return ret; 3215 3216 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3217 if (!ddc_node) { 3218 DRM_ERROR("Failed to find ddc node in device tree\n"); 3219 return -ENODEV; 3220 } 3221 3222 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3223 of_node_put(ddc_node); 3224 if (!vc4_hdmi->ddc) { 3225 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 3226 return -EPROBE_DEFER; 3227 } 3228 3229 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3230 if (ret) 3231 return ret; 3232 3233 /* Only use the GPIO HPD pin if present in the DT, otherwise 3234 * we'll use the HDMI core's register. 3235 */ 3236 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3237 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3238 return PTR_ERR(vc4_hdmi->hpd_gpio); 3239 } 3240 3241 vc4_hdmi->disable_wifi_frequencies = 3242 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3243 3244 ret = devm_pm_runtime_enable(dev); 3245 if (ret) 3246 return ret; 3247 3248 /* 3249 * We need to have the device powered up at this point to call 3250 * our reset hook and for the CEC init. 3251 */ 3252 ret = pm_runtime_resume_and_get(dev); 3253 if (ret) 3254 return ret; 3255 3256 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3257 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 3258 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3259 clk_prepare_enable(vc4_hdmi->pixel_clock); 3260 clk_prepare_enable(vc4_hdmi->hsm_clock); 3261 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3262 } 3263 3264 ret = drmm_encoder_init(drm, encoder, 3265 &vc4_hdmi_encoder_funcs, 3266 DRM_MODE_ENCODER_TMDS, 3267 NULL); 3268 if (ret) 3269 goto err_put_runtime_pm; 3270 3271 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3272 3273 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3274 if (ret) 3275 goto err_put_runtime_pm; 3276 3277 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3278 if (ret) 3279 goto err_put_runtime_pm; 3280 3281 ret = vc4_hdmi_cec_init(vc4_hdmi); 3282 if (ret) 3283 goto err_put_runtime_pm; 3284 3285 ret = vc4_hdmi_audio_init(vc4_hdmi); 3286 if (ret) 3287 goto err_put_runtime_pm; 3288 3289 pm_runtime_put_sync(dev); 3290 3291 return 0; 3292 3293 err_put_runtime_pm: 3294 pm_runtime_put_sync(dev); 3295 3296 return ret; 3297 } 3298 3299 static const struct component_ops vc4_hdmi_ops = { 3300 .bind = vc4_hdmi_bind, 3301 }; 3302 3303 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3304 { 3305 return component_add(&pdev->dev, &vc4_hdmi_ops); 3306 } 3307 3308 static void vc4_hdmi_dev_remove(struct platform_device *pdev) 3309 { 3310 component_del(&pdev->dev, &vc4_hdmi_ops); 3311 } 3312 3313 static const struct vc4_hdmi_variant bcm2835_variant = { 3314 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3315 .debugfs_name = "hdmi_regs", 3316 .card_name = "vc4-hdmi", 3317 .max_pixel_clock = 162000000, 3318 .registers = vc4_hdmi_fields, 3319 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3320 3321 .init_resources = vc4_hdmi_init_resources, 3322 .csc_setup = vc4_hdmi_csc_setup, 3323 .reset = vc4_hdmi_reset, 3324 .set_timings = vc4_hdmi_set_timings, 3325 .phy_init = vc4_hdmi_phy_init, 3326 .phy_disable = vc4_hdmi_phy_disable, 3327 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3328 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3329 .channel_map = vc4_hdmi_channel_map, 3330 .supports_hdr = false, 3331 }; 3332 3333 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3334 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3335 .debugfs_name = "hdmi0_regs", 3336 .card_name = "vc4-hdmi-0", 3337 .max_pixel_clock = 600000000, 3338 .registers = vc5_hdmi_hdmi0_fields, 3339 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3340 .phy_lane_mapping = { 3341 PHY_LANE_0, 3342 PHY_LANE_1, 3343 PHY_LANE_2, 3344 PHY_LANE_CK, 3345 }, 3346 .unsupported_odd_h_timings = true, 3347 .external_irq_controller = true, 3348 3349 .init_resources = vc5_hdmi_init_resources, 3350 .csc_setup = vc5_hdmi_csc_setup, 3351 .reset = vc5_hdmi_reset, 3352 .set_timings = vc5_hdmi_set_timings, 3353 .phy_init = vc5_hdmi_phy_init, 3354 .phy_disable = vc5_hdmi_phy_disable, 3355 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3356 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3357 .channel_map = vc5_hdmi_channel_map, 3358 .supports_hdr = true, 3359 .hp_detect = vc5_hdmi_hp_detect, 3360 }; 3361 3362 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3363 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3364 .debugfs_name = "hdmi1_regs", 3365 .card_name = "vc4-hdmi-1", 3366 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3367 .registers = vc5_hdmi_hdmi1_fields, 3368 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3369 .phy_lane_mapping = { 3370 PHY_LANE_1, 3371 PHY_LANE_0, 3372 PHY_LANE_CK, 3373 PHY_LANE_2, 3374 }, 3375 .unsupported_odd_h_timings = true, 3376 .external_irq_controller = true, 3377 3378 .init_resources = vc5_hdmi_init_resources, 3379 .csc_setup = vc5_hdmi_csc_setup, 3380 .reset = vc5_hdmi_reset, 3381 .set_timings = vc5_hdmi_set_timings, 3382 .phy_init = vc5_hdmi_phy_init, 3383 .phy_disable = vc5_hdmi_phy_disable, 3384 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3385 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3386 .channel_map = vc5_hdmi_channel_map, 3387 .supports_hdr = true, 3388 .hp_detect = vc5_hdmi_hp_detect, 3389 }; 3390 3391 static const struct of_device_id vc4_hdmi_dt_match[] = { 3392 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3393 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3394 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3395 {} 3396 }; 3397 3398 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3399 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3400 vc4_hdmi_runtime_resume, 3401 NULL) 3402 }; 3403 3404 struct platform_driver vc4_hdmi_driver = { 3405 .probe = vc4_hdmi_dev_probe, 3406 .remove_new = vc4_hdmi_dev_remove, 3407 .driver = { 3408 .name = "vc4_hdmi", 3409 .of_match_table = vc4_hdmi_dt_match, 3410 .pm = &vc4_hdmi_pm_ops, 3411 }, 3412 }; 3413