1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/hdmi-codec.h> 50 #include <sound/pcm_drm_eld.h> 51 #include <sound/pcm_params.h> 52 #include <sound/soc.h> 53 #include "media/cec.h" 54 #include "vc4_drv.h" 55 #include "vc4_hdmi.h" 56 #include "vc4_hdmi_regs.h" 57 #include "vc4_regs.h" 58 59 #define VC5_HDMI_HORZA_HFP_SHIFT 16 60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 61 #define VC5_HDMI_HORZA_VPOS BIT(15) 62 #define VC5_HDMI_HORZA_HPOS BIT(14) 63 #define VC5_HDMI_HORZA_HAP_SHIFT 0 64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 65 66 #define VC5_HDMI_HORZB_HBP_SHIFT 16 67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 68 #define VC5_HDMI_HORZB_HSP_SHIFT 0 69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 70 71 #define VC5_HDMI_VERTA_VSP_SHIFT 24 72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 73 #define VC5_HDMI_VERTA_VFP_SHIFT 16 74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 75 #define VC5_HDMI_VERTA_VAL_SHIFT 0 76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 77 78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 80 81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 82 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 85 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 88 89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 90 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 93 94 # define VC4_HD_M_SW_RST BIT(2) 95 # define VC4_HD_M_ENABLE BIT(0) 96 97 #define HSM_MIN_CLOCK_FREQ 120000000 98 #define CEC_CLOCK_FREQ 40000 99 100 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 101 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode) 103 { 104 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK; 105 } 106 107 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 108 const struct drm_display_mode *mode) 109 { 110 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 111 112 return !vc4_encoder->hdmi_monitor || 113 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 114 } 115 116 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 117 { 118 struct drm_info_node *node = (struct drm_info_node *)m->private; 119 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 120 struct drm_printer p = drm_seq_file_printer(m); 121 122 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 123 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 124 125 return 0; 126 } 127 128 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 129 { 130 unsigned long flags; 131 132 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 133 134 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 135 udelay(1); 136 HDMI_WRITE(HDMI_M_CTL, 0); 137 138 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 139 140 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 141 VC4_HDMI_SW_RESET_HDMI | 142 VC4_HDMI_SW_RESET_FORMAT_DETECT); 143 144 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 145 146 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 147 } 148 149 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 150 { 151 unsigned long flags; 152 153 reset_control_reset(vc4_hdmi->reset); 154 155 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 156 157 HDMI_WRITE(HDMI_DVP_CTL, 0); 158 159 HDMI_WRITE(HDMI_CLOCK_STOP, 160 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 161 162 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 163 } 164 165 #ifdef CONFIG_DRM_VC4_HDMI_CEC 166 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 167 { 168 unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 169 unsigned long flags; 170 u16 clk_cnt; 171 u32 value; 172 173 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 174 175 value = HDMI_READ(HDMI_CEC_CNTRL_1); 176 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 177 178 /* 179 * Set the clock divider: the hsm_clock rate and this divider 180 * setting will give a 40 kHz CEC clock. 181 */ 182 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 183 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 184 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 185 186 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 187 } 188 #else 189 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 190 #endif 191 192 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder); 193 194 static enum drm_connector_status 195 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 196 { 197 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 198 bool connected = false; 199 200 mutex_lock(&vc4_hdmi->mutex); 201 202 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 203 204 if (vc4_hdmi->hpd_gpio) { 205 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 206 connected = true; 207 } else { 208 if (vc4_hdmi->variant->hp_detect && 209 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 210 connected = true; 211 } 212 213 if (connected) { 214 if (connector->status != connector_status_connected) { 215 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 216 217 if (edid) { 218 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 219 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 220 kfree(edid); 221 } 222 } 223 224 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base); 225 pm_runtime_put(&vc4_hdmi->pdev->dev); 226 mutex_unlock(&vc4_hdmi->mutex); 227 return connector_status_connected; 228 } 229 230 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 231 pm_runtime_put(&vc4_hdmi->pdev->dev); 232 mutex_unlock(&vc4_hdmi->mutex); 233 return connector_status_disconnected; 234 } 235 236 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 237 { 238 drm_connector_unregister(connector); 239 drm_connector_cleanup(connector); 240 } 241 242 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 243 { 244 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 245 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 246 int ret = 0; 247 struct edid *edid; 248 249 mutex_lock(&vc4_hdmi->mutex); 250 251 edid = drm_get_edid(connector, vc4_hdmi->ddc); 252 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 253 if (!edid) { 254 ret = -ENODEV; 255 goto out; 256 } 257 258 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 259 260 drm_connector_update_edid_property(connector, edid); 261 ret = drm_add_edid_modes(connector, edid); 262 kfree(edid); 263 264 if (vc4_hdmi->disable_4kp60) { 265 struct drm_device *drm = connector->dev; 266 struct drm_display_mode *mode; 267 268 list_for_each_entry(mode, &connector->probed_modes, head) { 269 if (vc4_hdmi_mode_needs_scrambling(mode)) { 270 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 271 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 272 } 273 } 274 } 275 276 out: 277 mutex_unlock(&vc4_hdmi->mutex); 278 279 return ret; 280 } 281 282 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 283 struct drm_atomic_state *state) 284 { 285 struct drm_connector_state *old_state = 286 drm_atomic_get_old_connector_state(state, connector); 287 struct drm_connector_state *new_state = 288 drm_atomic_get_new_connector_state(state, connector); 289 struct drm_crtc *crtc = new_state->crtc; 290 291 if (!crtc) 292 return 0; 293 294 if (old_state->colorspace != new_state->colorspace || 295 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 296 struct drm_crtc_state *crtc_state; 297 298 crtc_state = drm_atomic_get_crtc_state(state, crtc); 299 if (IS_ERR(crtc_state)) 300 return PTR_ERR(crtc_state); 301 302 crtc_state->mode_changed = true; 303 } 304 305 return 0; 306 } 307 308 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 309 { 310 struct vc4_hdmi_connector_state *old_state = 311 conn_state_to_vc4_hdmi_conn_state(connector->state); 312 struct vc4_hdmi_connector_state *new_state = 313 kzalloc(sizeof(*new_state), GFP_KERNEL); 314 315 if (connector->state) 316 __drm_atomic_helper_connector_destroy_state(connector->state); 317 318 kfree(old_state); 319 __drm_atomic_helper_connector_reset(connector, &new_state->base); 320 321 if (!new_state) 322 return; 323 324 new_state->base.max_bpc = 8; 325 new_state->base.max_requested_bpc = 8; 326 drm_atomic_helper_connector_tv_reset(connector); 327 } 328 329 static struct drm_connector_state * 330 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 331 { 332 struct drm_connector_state *conn_state = connector->state; 333 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 334 struct vc4_hdmi_connector_state *new_state; 335 336 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 337 if (!new_state) 338 return NULL; 339 340 new_state->pixel_rate = vc4_state->pixel_rate; 341 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 342 343 return &new_state->base; 344 } 345 346 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 347 .detect = vc4_hdmi_connector_detect, 348 .fill_modes = drm_helper_probe_single_connector_modes, 349 .destroy = vc4_hdmi_connector_destroy, 350 .reset = vc4_hdmi_connector_reset, 351 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 352 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 353 }; 354 355 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 356 .get_modes = vc4_hdmi_connector_get_modes, 357 .atomic_check = vc4_hdmi_connector_atomic_check, 358 }; 359 360 static int vc4_hdmi_connector_init(struct drm_device *dev, 361 struct vc4_hdmi *vc4_hdmi) 362 { 363 struct drm_connector *connector = &vc4_hdmi->connector; 364 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 365 int ret; 366 367 drm_connector_init_with_ddc(dev, connector, 368 &vc4_hdmi_connector_funcs, 369 DRM_MODE_CONNECTOR_HDMIA, 370 vc4_hdmi->ddc); 371 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 372 373 /* 374 * Some of the properties below require access to state, like bpc. 375 * Allocate some default initial connector state with our reset helper. 376 */ 377 if (connector->funcs->reset) 378 connector->funcs->reset(connector); 379 380 /* Create and attach TV margin props to this connector. */ 381 ret = drm_mode_create_tv_margin_properties(dev); 382 if (ret) 383 return ret; 384 385 ret = drm_mode_create_hdmi_colorspace_property(connector); 386 if (ret) 387 return ret; 388 389 drm_connector_attach_colorspace_property(connector); 390 drm_connector_attach_tv_margin_properties(connector); 391 drm_connector_attach_max_bpc_property(connector, 8, 12); 392 393 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 394 DRM_CONNECTOR_POLL_DISCONNECT); 395 396 connector->interlace_allowed = 1; 397 connector->doublescan_allowed = 0; 398 399 if (vc4_hdmi->variant->supports_hdr) 400 drm_connector_attach_hdr_output_metadata_property(connector); 401 402 drm_connector_attach_encoder(connector, encoder); 403 404 return 0; 405 } 406 407 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 408 enum hdmi_infoframe_type type, 409 bool poll) 410 { 411 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 412 u32 packet_id = type - 0x80; 413 unsigned long flags; 414 415 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 416 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 417 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 418 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 419 420 if (!poll) 421 return 0; 422 423 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 424 BIT(packet_id)), 100); 425 } 426 427 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 428 union hdmi_infoframe *frame) 429 { 430 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 431 u32 packet_id = frame->any.type - 0x80; 432 const struct vc4_hdmi_register *ram_packet_start = 433 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 434 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 435 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 436 ram_packet_start->reg); 437 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 438 unsigned long flags; 439 ssize_t len, i; 440 int ret; 441 442 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 443 VC4_HDMI_RAM_PACKET_ENABLE), 444 "Packet RAM has to be on to store the packet."); 445 446 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 447 if (len < 0) 448 return; 449 450 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 451 if (ret) { 452 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 453 return; 454 } 455 456 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 457 458 for (i = 0; i < len; i += 7) { 459 writel(buffer[i + 0] << 0 | 460 buffer[i + 1] << 8 | 461 buffer[i + 2] << 16, 462 base + packet_reg); 463 packet_reg += 4; 464 465 writel(buffer[i + 3] << 0 | 466 buffer[i + 4] << 8 | 467 buffer[i + 5] << 16 | 468 buffer[i + 6] << 24, 469 base + packet_reg); 470 packet_reg += 4; 471 } 472 473 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 474 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 475 476 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 477 478 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 479 BIT(packet_id)), 100); 480 if (ret) 481 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 482 } 483 484 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 485 { 486 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 487 struct drm_connector *connector = &vc4_hdmi->connector; 488 struct drm_connector_state *cstate = connector->state; 489 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 490 union hdmi_infoframe frame; 491 int ret; 492 493 lockdep_assert_held(&vc4_hdmi->mutex); 494 495 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 496 connector, mode); 497 if (ret < 0) { 498 DRM_ERROR("couldn't fill AVI infoframe\n"); 499 return; 500 } 501 502 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 503 connector, mode, 504 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 505 HDMI_QUANTIZATION_RANGE_FULL : 506 HDMI_QUANTIZATION_RANGE_LIMITED); 507 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 508 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 509 510 vc4_hdmi_write_infoframe(encoder, &frame); 511 } 512 513 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 514 { 515 union hdmi_infoframe frame; 516 int ret; 517 518 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 519 if (ret < 0) { 520 DRM_ERROR("couldn't fill SPD infoframe\n"); 521 return; 522 } 523 524 frame.spd.sdi = HDMI_SPD_SDI_PC; 525 526 vc4_hdmi_write_infoframe(encoder, &frame); 527 } 528 529 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 530 { 531 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 532 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 533 union hdmi_infoframe frame; 534 535 memcpy(&frame.audio, audio, sizeof(*audio)); 536 vc4_hdmi_write_infoframe(encoder, &frame); 537 } 538 539 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 540 { 541 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 542 struct drm_connector *connector = &vc4_hdmi->connector; 543 struct drm_connector_state *conn_state = connector->state; 544 union hdmi_infoframe frame; 545 546 lockdep_assert_held(&vc4_hdmi->mutex); 547 548 if (!vc4_hdmi->variant->supports_hdr) 549 return; 550 551 if (!conn_state->hdr_output_metadata) 552 return; 553 554 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 555 return; 556 557 vc4_hdmi_write_infoframe(encoder, &frame); 558 } 559 560 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 561 { 562 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 563 564 lockdep_assert_held(&vc4_hdmi->mutex); 565 566 vc4_hdmi_set_avi_infoframe(encoder); 567 vc4_hdmi_set_spd_infoframe(encoder); 568 /* 569 * If audio was streaming, then we need to reenabled the audio 570 * infoframe here during encoder_enable. 571 */ 572 if (vc4_hdmi->audio.streaming) 573 vc4_hdmi_set_audio_infoframe(encoder); 574 575 vc4_hdmi_set_hdr_infoframe(encoder); 576 } 577 578 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 579 struct drm_display_mode *mode) 580 { 581 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 582 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 583 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 584 585 lockdep_assert_held(&vc4_hdmi->mutex); 586 587 if (!vc4_encoder->hdmi_monitor) 588 return false; 589 590 if (!display->hdmi.scdc.supported || 591 !display->hdmi.scdc.scrambling.supported) 592 return false; 593 594 return true; 595 } 596 597 #define SCRAMBLING_POLLING_DELAY_MS 1000 598 599 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 600 { 601 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 602 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 603 unsigned long flags; 604 605 lockdep_assert_held(&vc4_hdmi->mutex); 606 607 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 608 return; 609 610 if (!vc4_hdmi_mode_needs_scrambling(mode)) 611 return; 612 613 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 614 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 615 616 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 617 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 618 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 619 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 620 621 vc4_hdmi->scdc_enabled = true; 622 623 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 624 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 625 } 626 627 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 628 { 629 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 630 unsigned long flags; 631 632 lockdep_assert_held(&vc4_hdmi->mutex); 633 634 if (!vc4_hdmi->scdc_enabled) 635 return; 636 637 vc4_hdmi->scdc_enabled = false; 638 639 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 640 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 641 642 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 643 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 644 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 645 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 646 647 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 648 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 649 } 650 651 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 652 { 653 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 654 struct vc4_hdmi, 655 scrambling_work); 656 657 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 658 return; 659 660 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 661 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 662 663 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 664 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 665 } 666 667 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 668 struct drm_atomic_state *state) 669 { 670 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 671 unsigned long flags; 672 673 mutex_lock(&vc4_hdmi->mutex); 674 675 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 676 677 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 678 679 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 680 681 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 682 683 mdelay(1); 684 685 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 686 HDMI_WRITE(HDMI_VID_CTL, 687 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 688 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 689 690 vc4_hdmi_disable_scrambling(encoder); 691 692 mutex_unlock(&vc4_hdmi->mutex); 693 } 694 695 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 696 struct drm_atomic_state *state) 697 { 698 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 699 unsigned long flags; 700 int ret; 701 702 mutex_lock(&vc4_hdmi->mutex); 703 704 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 705 HDMI_WRITE(HDMI_VID_CTL, 706 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 707 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 708 709 if (vc4_hdmi->variant->phy_disable) 710 vc4_hdmi->variant->phy_disable(vc4_hdmi); 711 712 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 713 clk_disable_unprepare(vc4_hdmi->pixel_clock); 714 715 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 716 if (ret < 0) 717 DRM_ERROR("Failed to release power domain: %d\n", ret); 718 719 mutex_unlock(&vc4_hdmi->mutex); 720 } 721 722 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 723 { 724 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 725 726 mutex_lock(&vc4_hdmi->mutex); 727 vc4_hdmi->output_enabled = false; 728 mutex_unlock(&vc4_hdmi->mutex); 729 } 730 731 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 732 struct drm_connector_state *state, 733 const struct drm_display_mode *mode) 734 { 735 unsigned long flags; 736 u32 csc_ctl; 737 738 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 739 740 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 741 VC4_HD_CSC_CTL_ORDER); 742 743 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 744 /* CEA VICs other than #1 requre limited range RGB 745 * output unless overridden by an AVI infoframe. 746 * Apply a colorspace conversion to squash 0-255 down 747 * to 16-235. The matrix here is: 748 * 749 * [ 0 0 0.8594 16] 750 * [ 0 0.8594 0 16] 751 * [ 0.8594 0 0 16] 752 * [ 0 0 0 1] 753 */ 754 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 755 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 756 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 757 VC4_HD_CSC_CTL_MODE); 758 759 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 760 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 761 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 762 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 763 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 764 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 765 } 766 767 /* The RGB order applies even when CSC is disabled. */ 768 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 769 770 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 771 } 772 773 /* 774 * If we need to output Full Range RGB, then use the unity matrix 775 * 776 * [ 1 0 0 0] 777 * [ 0 1 0 0] 778 * [ 0 0 1 0] 779 * 780 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 781 */ 782 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 783 { 0x2000, 0x0000, 0x0000, 0x0000 }, 784 { 0x0000, 0x2000, 0x0000, 0x0000 }, 785 { 0x0000, 0x0000, 0x2000, 0x0000 }, 786 }; 787 788 /* 789 * CEA VICs other than #1 require limited range RGB output unless 790 * overridden by an AVI infoframe. Apply a colorspace conversion to 791 * squash 0-255 down to 16-235. The matrix here is: 792 * 793 * [ 0.8594 0 0 16] 794 * [ 0 0.8594 0 16] 795 * [ 0 0 0.8594 16] 796 * 797 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 798 */ 799 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 800 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 801 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 802 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 803 }; 804 805 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 806 const u16 coeffs[3][4]) 807 { 808 lockdep_assert_held(&vc4_hdmi->hw_lock); 809 810 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 811 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 812 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 813 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 814 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 815 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 816 } 817 818 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 819 struct drm_connector_state *state, 820 const struct drm_display_mode *mode) 821 { 822 unsigned long flags; 823 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 824 VC5_MT_CP_CSC_CTL_MODE); 825 826 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 827 828 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 829 830 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 831 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 832 else 833 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 834 835 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 836 837 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 838 } 839 840 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 841 struct drm_connector_state *state, 842 struct drm_display_mode *mode) 843 { 844 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 845 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 846 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 847 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 848 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 849 VC4_HDMI_VERTA_VSP) | 850 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 851 VC4_HDMI_VERTA_VFP) | 852 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 853 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 854 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 855 VC4_HDMI_VERTB_VBP)); 856 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 857 VC4_SET_FIELD(mode->crtc_vtotal - 858 mode->crtc_vsync_end - 859 interlaced, 860 VC4_HDMI_VERTB_VBP)); 861 unsigned long flags; 862 863 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 864 865 HDMI_WRITE(HDMI_HORZA, 866 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 867 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 868 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 869 VC4_HDMI_HORZA_HAP)); 870 871 HDMI_WRITE(HDMI_HORZB, 872 VC4_SET_FIELD((mode->htotal - 873 mode->hsync_end) * pixel_rep, 874 VC4_HDMI_HORZB_HBP) | 875 VC4_SET_FIELD((mode->hsync_end - 876 mode->hsync_start) * pixel_rep, 877 VC4_HDMI_HORZB_HSP) | 878 VC4_SET_FIELD((mode->hsync_start - 879 mode->hdisplay) * pixel_rep, 880 VC4_HDMI_HORZB_HFP)); 881 882 HDMI_WRITE(HDMI_VERTA0, verta); 883 HDMI_WRITE(HDMI_VERTA1, verta); 884 885 HDMI_WRITE(HDMI_VERTB0, vertb_even); 886 HDMI_WRITE(HDMI_VERTB1, vertb); 887 888 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 889 } 890 891 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 892 struct drm_connector_state *state, 893 struct drm_display_mode *mode) 894 { 895 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 896 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 897 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 898 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 899 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 900 VC5_HDMI_VERTA_VSP) | 901 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 902 VC5_HDMI_VERTA_VFP) | 903 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 904 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 905 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 906 VC4_HDMI_VERTB_VBP)); 907 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 908 VC4_SET_FIELD(mode->crtc_vtotal - 909 mode->crtc_vsync_end - 910 interlaced, 911 VC4_HDMI_VERTB_VBP)); 912 unsigned long flags; 913 unsigned char gcp; 914 bool gcp_en; 915 u32 reg; 916 917 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 918 919 HDMI_WRITE(HDMI_HORZA, 920 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 921 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 922 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 923 VC5_HDMI_HORZA_HAP) | 924 VC4_SET_FIELD((mode->hsync_start - 925 mode->hdisplay) * pixel_rep, 926 VC5_HDMI_HORZA_HFP)); 927 928 HDMI_WRITE(HDMI_HORZB, 929 VC4_SET_FIELD((mode->htotal - 930 mode->hsync_end) * pixel_rep, 931 VC5_HDMI_HORZB_HBP) | 932 VC4_SET_FIELD((mode->hsync_end - 933 mode->hsync_start) * pixel_rep, 934 VC5_HDMI_HORZB_HSP)); 935 936 HDMI_WRITE(HDMI_VERTA0, verta); 937 HDMI_WRITE(HDMI_VERTA1, verta); 938 939 HDMI_WRITE(HDMI_VERTB0, vertb_even); 940 HDMI_WRITE(HDMI_VERTB1, vertb); 941 942 switch (state->max_bpc) { 943 case 12: 944 gcp = 6; 945 gcp_en = true; 946 break; 947 case 10: 948 gcp = 5; 949 gcp_en = true; 950 break; 951 case 8: 952 default: 953 gcp = 4; 954 gcp_en = false; 955 break; 956 } 957 958 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 959 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 960 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 961 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 962 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 963 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 964 965 reg = HDMI_READ(HDMI_GCP_WORD_1); 966 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 967 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 968 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 969 970 reg = HDMI_READ(HDMI_GCP_CONFIG); 971 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 972 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 973 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 974 975 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 976 977 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 978 } 979 980 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 981 { 982 unsigned long flags; 983 u32 drift; 984 int ret; 985 986 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 987 988 drift = HDMI_READ(HDMI_FIFO_CTL); 989 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 990 991 HDMI_WRITE(HDMI_FIFO_CTL, 992 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 993 HDMI_WRITE(HDMI_FIFO_CTL, 994 drift | VC4_HDMI_FIFO_CTL_RECENTER); 995 996 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 997 998 usleep_range(1000, 1100); 999 1000 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1001 1002 HDMI_WRITE(HDMI_FIFO_CTL, 1003 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1004 HDMI_WRITE(HDMI_FIFO_CTL, 1005 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1006 1007 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1008 1009 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1010 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1011 WARN_ONCE(ret, "Timeout waiting for " 1012 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1013 } 1014 1015 static struct drm_connector_state * 1016 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder, 1017 struct drm_atomic_state *state) 1018 { 1019 struct drm_connector_state *conn_state; 1020 struct drm_connector *connector; 1021 unsigned int i; 1022 1023 for_each_new_connector_in_state(state, connector, conn_state, i) { 1024 if (conn_state->best_encoder == encoder) 1025 return conn_state; 1026 } 1027 1028 return NULL; 1029 } 1030 1031 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1032 struct drm_atomic_state *state) 1033 { 1034 struct drm_connector_state *conn_state = 1035 vc4_hdmi_encoder_get_connector_state(encoder, state); 1036 struct vc4_hdmi_connector_state *vc4_conn_state = 1037 conn_state_to_vc4_hdmi_conn_state(conn_state); 1038 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1039 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1040 unsigned long pixel_rate = vc4_conn_state->pixel_rate; 1041 unsigned long bvb_rate, hsm_rate; 1042 unsigned long flags; 1043 int ret; 1044 1045 mutex_lock(&vc4_hdmi->mutex); 1046 1047 /* 1048 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1049 * be faster than pixel clock, infinitesimally faster, tested in 1050 * simulation. Otherwise, exact value is unimportant for HDMI 1051 * operation." This conflicts with bcm2835's vc4 documentation, which 1052 * states HSM's clock has to be at least 108% of the pixel clock. 1053 * 1054 * Real life tests reveal that vc4's firmware statement holds up, and 1055 * users are able to use pixel clocks closer to HSM's, namely for 1056 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1057 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1058 * 162MHz. 1059 * 1060 * Additionally, the AXI clock needs to be at least 25% of 1061 * pixel clock, but HSM ends up being the limiting factor. 1062 */ 1063 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 1064 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1065 if (ret) { 1066 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1067 goto out; 1068 } 1069 1070 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1071 if (ret < 0) { 1072 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1073 goto out; 1074 } 1075 1076 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 1077 if (ret) { 1078 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1079 goto err_put_runtime_pm; 1080 } 1081 1082 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1083 if (ret) { 1084 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1085 goto err_put_runtime_pm; 1086 } 1087 1088 1089 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1090 1091 if (pixel_rate > 297000000) 1092 bvb_rate = 300000000; 1093 else if (pixel_rate > 148500000) 1094 bvb_rate = 150000000; 1095 else 1096 bvb_rate = 75000000; 1097 1098 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1099 if (ret) { 1100 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1101 goto err_disable_pixel_clock; 1102 } 1103 1104 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1105 if (ret) { 1106 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1107 goto err_disable_pixel_clock; 1108 } 1109 1110 if (vc4_hdmi->variant->phy_init) 1111 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1112 1113 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1114 1115 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1116 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1117 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1118 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1119 1120 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1121 1122 if (vc4_hdmi->variant->set_timings) 1123 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1124 1125 mutex_unlock(&vc4_hdmi->mutex); 1126 1127 return; 1128 1129 err_disable_pixel_clock: 1130 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1131 err_put_runtime_pm: 1132 pm_runtime_put(&vc4_hdmi->pdev->dev); 1133 out: 1134 mutex_unlock(&vc4_hdmi->mutex); 1135 return; 1136 } 1137 1138 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1139 struct drm_atomic_state *state) 1140 { 1141 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1142 struct drm_connector *connector = &vc4_hdmi->connector; 1143 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1144 struct drm_connector_state *conn_state = 1145 drm_atomic_get_new_connector_state(state, connector); 1146 unsigned long flags; 1147 1148 mutex_lock(&vc4_hdmi->mutex); 1149 1150 if (vc4_hdmi->variant->csc_setup) 1151 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1152 1153 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1154 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1155 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1156 1157 mutex_unlock(&vc4_hdmi->mutex); 1158 } 1159 1160 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1161 struct drm_atomic_state *state) 1162 { 1163 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1164 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1165 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1166 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1167 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1168 unsigned long flags; 1169 int ret; 1170 1171 mutex_lock(&vc4_hdmi->mutex); 1172 1173 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1174 1175 HDMI_WRITE(HDMI_VID_CTL, 1176 VC4_HD_VID_CTL_ENABLE | 1177 VC4_HD_VID_CTL_CLRRGB | 1178 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1179 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1180 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1181 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1182 1183 HDMI_WRITE(HDMI_VID_CTL, 1184 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1185 1186 if (vc4_encoder->hdmi_monitor) { 1187 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1188 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1189 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1190 1191 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1192 1193 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1194 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1195 WARN_ONCE(ret, "Timeout waiting for " 1196 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1197 } else { 1198 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1199 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1200 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1201 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1202 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1203 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1204 1205 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1206 1207 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1208 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1209 WARN_ONCE(ret, "Timeout waiting for " 1210 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1211 } 1212 1213 if (vc4_encoder->hdmi_monitor) { 1214 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1215 1216 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1217 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1218 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1219 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1220 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1221 1222 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1223 VC4_HDMI_RAM_PACKET_ENABLE); 1224 1225 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1226 1227 vc4_hdmi_set_infoframes(encoder); 1228 } 1229 1230 vc4_hdmi_recenter_fifo(vc4_hdmi); 1231 vc4_hdmi_enable_scrambling(encoder); 1232 1233 mutex_unlock(&vc4_hdmi->mutex); 1234 } 1235 1236 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1237 { 1238 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1239 1240 mutex_lock(&vc4_hdmi->mutex); 1241 vc4_hdmi->output_enabled = true; 1242 mutex_unlock(&vc4_hdmi->mutex); 1243 } 1244 1245 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1246 struct drm_crtc_state *crtc_state, 1247 struct drm_connector_state *conn_state) 1248 { 1249 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1250 1251 mutex_lock(&vc4_hdmi->mutex); 1252 memcpy(&vc4_hdmi->saved_adjusted_mode, 1253 &crtc_state->adjusted_mode, 1254 sizeof(vc4_hdmi->saved_adjusted_mode)); 1255 mutex_unlock(&vc4_hdmi->mutex); 1256 } 1257 1258 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1259 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1260 1261 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1262 struct drm_crtc_state *crtc_state, 1263 struct drm_connector_state *conn_state) 1264 { 1265 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1266 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1267 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1268 unsigned long long pixel_rate = mode->clock * 1000; 1269 unsigned long long tmds_rate; 1270 1271 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1272 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1273 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1274 (mode->hsync_end % 2) || (mode->htotal % 2))) 1275 return -EINVAL; 1276 1277 /* 1278 * The 1440p@60 pixel rate is in the same range than the first 1279 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1280 * bandwidth). Slightly lower the frequency to bring it out of 1281 * the WiFi range. 1282 */ 1283 tmds_rate = pixel_rate * 10; 1284 if (vc4_hdmi->disable_wifi_frequencies && 1285 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1286 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1287 mode->clock = 238560; 1288 pixel_rate = mode->clock * 1000; 1289 } 1290 1291 if (conn_state->max_bpc == 12) { 1292 pixel_rate = pixel_rate * 150; 1293 do_div(pixel_rate, 100); 1294 } else if (conn_state->max_bpc == 10) { 1295 pixel_rate = pixel_rate * 125; 1296 do_div(pixel_rate, 100); 1297 } 1298 1299 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1300 pixel_rate = pixel_rate * 2; 1301 1302 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 1303 return -EINVAL; 1304 1305 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK)) 1306 return -EINVAL; 1307 1308 vc4_state->pixel_rate = pixel_rate; 1309 1310 return 0; 1311 } 1312 1313 static enum drm_mode_status 1314 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1315 const struct drm_display_mode *mode) 1316 { 1317 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1318 1319 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1320 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1321 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1322 (mode->hsync_end % 2) || (mode->htotal % 2))) 1323 return MODE_H_ILLEGAL; 1324 1325 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 1326 return MODE_CLOCK_HIGH; 1327 1328 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode)) 1329 return MODE_CLOCK_HIGH; 1330 1331 return MODE_OK; 1332 } 1333 1334 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1335 .atomic_check = vc4_hdmi_encoder_atomic_check, 1336 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1337 .mode_valid = vc4_hdmi_encoder_mode_valid, 1338 .disable = vc4_hdmi_encoder_disable, 1339 .enable = vc4_hdmi_encoder_enable, 1340 }; 1341 1342 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1343 { 1344 int i; 1345 u32 channel_map = 0; 1346 1347 for (i = 0; i < 8; i++) { 1348 if (channel_mask & BIT(i)) 1349 channel_map |= i << (3 * i); 1350 } 1351 return channel_map; 1352 } 1353 1354 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1355 { 1356 int i; 1357 u32 channel_map = 0; 1358 1359 for (i = 0; i < 8; i++) { 1360 if (channel_mask & BIT(i)) 1361 channel_map |= i << (4 * i); 1362 } 1363 return channel_map; 1364 } 1365 1366 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1367 { 1368 unsigned long flags; 1369 u32 hotplug; 1370 1371 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1372 hotplug = HDMI_READ(HDMI_HOTPLUG); 1373 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1374 1375 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1376 } 1377 1378 /* HDMI audio codec callbacks */ 1379 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1380 unsigned int samplerate) 1381 { 1382 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1383 unsigned long flags; 1384 unsigned long n, m; 1385 1386 rational_best_approximation(hsm_clock, samplerate, 1387 VC4_HD_MAI_SMP_N_MASK >> 1388 VC4_HD_MAI_SMP_N_SHIFT, 1389 (VC4_HD_MAI_SMP_M_MASK >> 1390 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1391 &n, &m); 1392 1393 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1394 HDMI_WRITE(HDMI_MAI_SMP, 1395 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1396 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1397 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1398 } 1399 1400 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1401 { 1402 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1403 u32 n, cts; 1404 u64 tmp; 1405 1406 lockdep_assert_held(&vc4_hdmi->mutex); 1407 lockdep_assert_held(&vc4_hdmi->hw_lock); 1408 1409 n = 128 * samplerate / 1000; 1410 tmp = (u64)(mode->clock * 1000) * n; 1411 do_div(tmp, 128 * samplerate); 1412 cts = tmp; 1413 1414 HDMI_WRITE(HDMI_CRP_CFG, 1415 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1416 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1417 1418 /* 1419 * We could get slightly more accurate clocks in some cases by 1420 * providing a CTS_1 value. The two CTS values are alternated 1421 * between based on the period fields 1422 */ 1423 HDMI_WRITE(HDMI_CTS_0, cts); 1424 HDMI_WRITE(HDMI_CTS_1, cts); 1425 } 1426 1427 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1428 { 1429 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1430 1431 return snd_soc_card_get_drvdata(card); 1432 } 1433 1434 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1435 { 1436 lockdep_assert_held(&vc4_hdmi->mutex); 1437 1438 /* 1439 * If the controller is disabled, prevent any ALSA output. 1440 */ 1441 if (!vc4_hdmi->output_enabled) 1442 return false; 1443 1444 /* 1445 * If the encoder is currently in DVI mode, treat the codec DAI 1446 * as missing. 1447 */ 1448 if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE)) 1449 return false; 1450 1451 return true; 1452 } 1453 1454 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1455 { 1456 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1457 unsigned long flags; 1458 1459 mutex_lock(&vc4_hdmi->mutex); 1460 1461 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1462 mutex_unlock(&vc4_hdmi->mutex); 1463 return -ENODEV; 1464 } 1465 1466 vc4_hdmi->audio.streaming = true; 1467 1468 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1469 HDMI_WRITE(HDMI_MAI_CTL, 1470 VC4_HD_MAI_CTL_RESET | 1471 VC4_HD_MAI_CTL_FLUSH | 1472 VC4_HD_MAI_CTL_DLATE | 1473 VC4_HD_MAI_CTL_ERRORE | 1474 VC4_HD_MAI_CTL_ERRORF); 1475 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1476 1477 if (vc4_hdmi->variant->phy_rng_enable) 1478 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1479 1480 mutex_unlock(&vc4_hdmi->mutex); 1481 1482 return 0; 1483 } 1484 1485 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1486 { 1487 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1488 struct device *dev = &vc4_hdmi->pdev->dev; 1489 unsigned long flags; 1490 int ret; 1491 1492 lockdep_assert_held(&vc4_hdmi->mutex); 1493 1494 vc4_hdmi->audio.streaming = false; 1495 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1496 if (ret) 1497 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1498 1499 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1500 1501 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1502 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1503 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1504 1505 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1506 } 1507 1508 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1509 { 1510 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1511 unsigned long flags; 1512 1513 mutex_lock(&vc4_hdmi->mutex); 1514 1515 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1516 1517 HDMI_WRITE(HDMI_MAI_CTL, 1518 VC4_HD_MAI_CTL_DLATE | 1519 VC4_HD_MAI_CTL_ERRORE | 1520 VC4_HD_MAI_CTL_ERRORF); 1521 1522 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1523 1524 if (vc4_hdmi->variant->phy_rng_disable) 1525 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1526 1527 vc4_hdmi->audio.streaming = false; 1528 vc4_hdmi_audio_reset(vc4_hdmi); 1529 1530 mutex_unlock(&vc4_hdmi->mutex); 1531 } 1532 1533 static int sample_rate_to_mai_fmt(int samplerate) 1534 { 1535 switch (samplerate) { 1536 case 8000: 1537 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1538 case 11025: 1539 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1540 case 12000: 1541 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1542 case 16000: 1543 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1544 case 22050: 1545 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1546 case 24000: 1547 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1548 case 32000: 1549 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1550 case 44100: 1551 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1552 case 48000: 1553 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1554 case 64000: 1555 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1556 case 88200: 1557 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1558 case 96000: 1559 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1560 case 128000: 1561 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 1562 case 176400: 1563 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 1564 case 192000: 1565 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 1566 default: 1567 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 1568 } 1569 } 1570 1571 /* HDMI audio codec callbacks */ 1572 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 1573 struct hdmi_codec_daifmt *daifmt, 1574 struct hdmi_codec_params *params) 1575 { 1576 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1577 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1578 unsigned int sample_rate = params->sample_rate; 1579 unsigned int channels = params->channels; 1580 unsigned long flags; 1581 u32 audio_packet_config, channel_mask; 1582 u32 channel_map; 1583 u32 mai_audio_format; 1584 u32 mai_sample_rate; 1585 1586 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1587 sample_rate, params->sample_width, channels); 1588 1589 mutex_lock(&vc4_hdmi->mutex); 1590 1591 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1592 mutex_unlock(&vc4_hdmi->mutex); 1593 return -EINVAL; 1594 } 1595 1596 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 1597 1598 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1599 HDMI_WRITE(HDMI_MAI_CTL, 1600 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 1601 VC4_HD_MAI_CTL_WHOLSMP | 1602 VC4_HD_MAI_CTL_CHALIGN | 1603 VC4_HD_MAI_CTL_ENABLE); 1604 1605 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 1606 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 1607 params->channels == 8) 1608 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 1609 else 1610 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 1611 HDMI_WRITE(HDMI_MAI_FMT, 1612 VC4_SET_FIELD(mai_sample_rate, 1613 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 1614 VC4_SET_FIELD(mai_audio_format, 1615 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 1616 1617 /* The B frame identifier should match the value used by alsa-lib (8) */ 1618 audio_packet_config = 1619 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1620 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1621 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1622 1623 channel_mask = GENMASK(channels - 1, 0); 1624 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1625 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1626 1627 /* Set the MAI threshold */ 1628 HDMI_WRITE(HDMI_MAI_THR, 1629 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1630 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1631 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1632 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1633 1634 HDMI_WRITE(HDMI_MAI_CONFIG, 1635 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1636 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 1637 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1638 1639 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1640 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1641 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1642 1643 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 1644 1645 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1646 1647 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 1648 vc4_hdmi_set_audio_infoframe(encoder); 1649 1650 mutex_unlock(&vc4_hdmi->mutex); 1651 1652 return 0; 1653 } 1654 1655 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1656 .name = "vc4-hdmi-cpu-dai-component", 1657 }; 1658 1659 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1660 { 1661 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1662 1663 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1664 1665 return 0; 1666 } 1667 1668 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1669 .name = "vc4-hdmi-cpu-dai", 1670 .probe = vc4_hdmi_audio_cpu_dai_probe, 1671 .playback = { 1672 .stream_name = "Playback", 1673 .channels_min = 1, 1674 .channels_max = 8, 1675 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1676 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1677 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1678 SNDRV_PCM_RATE_192000, 1679 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1680 }, 1681 }; 1682 1683 static const struct snd_dmaengine_pcm_config pcm_conf = { 1684 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1685 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1686 }; 1687 1688 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 1689 uint8_t *buf, size_t len) 1690 { 1691 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1692 struct drm_connector *connector = &vc4_hdmi->connector; 1693 1694 mutex_lock(&vc4_hdmi->mutex); 1695 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1696 mutex_unlock(&vc4_hdmi->mutex); 1697 1698 return 0; 1699 } 1700 1701 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 1702 .get_eld = vc4_hdmi_audio_get_eld, 1703 .prepare = vc4_hdmi_audio_prepare, 1704 .audio_shutdown = vc4_hdmi_audio_shutdown, 1705 .audio_startup = vc4_hdmi_audio_startup, 1706 }; 1707 1708 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 1709 .ops = &vc4_hdmi_codec_ops, 1710 .max_i2s_channels = 8, 1711 .i2s = 1, 1712 }; 1713 1714 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1715 { 1716 const struct vc4_hdmi_register *mai_data = 1717 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1718 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1719 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1720 struct device *dev = &vc4_hdmi->pdev->dev; 1721 struct platform_device *codec_pdev; 1722 const __be32 *addr; 1723 int index; 1724 int ret; 1725 1726 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1727 dev_warn(dev, 1728 "'dmas' DT property is missing, no HDMI audio\n"); 1729 return 0; 1730 } 1731 1732 if (mai_data->reg != VC4_HD) { 1733 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1734 return -EINVAL; 1735 } 1736 1737 /* 1738 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1739 * the bus address specified in the DT, because the physical address 1740 * (the one returned by platform_get_resource()) is not appropriate 1741 * for DMA transfers. 1742 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1743 */ 1744 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1745 /* Before BCM2711, we don't have a named register range */ 1746 if (index < 0) 1747 index = 1; 1748 1749 addr = of_get_address(dev->of_node, index, NULL, NULL); 1750 1751 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1752 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1753 vc4_hdmi->audio.dma_data.maxburst = 2; 1754 1755 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1756 if (ret) { 1757 dev_err(dev, "Could not register PCM component: %d\n", ret); 1758 return ret; 1759 } 1760 1761 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1762 &vc4_hdmi_audio_cpu_dai_drv, 1); 1763 if (ret) { 1764 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1765 return ret; 1766 } 1767 1768 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1769 PLATFORM_DEVID_AUTO, 1770 &vc4_hdmi_codec_pdata, 1771 sizeof(vc4_hdmi_codec_pdata)); 1772 if (IS_ERR(codec_pdev)) { 1773 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 1774 return PTR_ERR(codec_pdev); 1775 } 1776 1777 dai_link->cpus = &vc4_hdmi->audio.cpu; 1778 dai_link->codecs = &vc4_hdmi->audio.codec; 1779 dai_link->platforms = &vc4_hdmi->audio.platform; 1780 1781 dai_link->num_cpus = 1; 1782 dai_link->num_codecs = 1; 1783 dai_link->num_platforms = 1; 1784 1785 dai_link->name = "MAI"; 1786 dai_link->stream_name = "MAI PCM"; 1787 dai_link->codecs->dai_name = "i2s-hifi"; 1788 dai_link->cpus->dai_name = dev_name(dev); 1789 dai_link->codecs->name = dev_name(&codec_pdev->dev); 1790 dai_link->platforms->name = dev_name(dev); 1791 1792 card->dai_link = dai_link; 1793 card->num_links = 1; 1794 card->name = vc4_hdmi->variant->card_name; 1795 card->driver_name = "vc4-hdmi"; 1796 card->dev = dev; 1797 card->owner = THIS_MODULE; 1798 1799 /* 1800 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1801 * stores a pointer to the snd card object in dev->driver_data. This 1802 * means we cannot use it for something else. The hdmi back-pointer is 1803 * now stored in card->drvdata and should be retrieved with 1804 * snd_soc_card_get_drvdata() if needed. 1805 */ 1806 snd_soc_card_set_drvdata(card, vc4_hdmi); 1807 ret = devm_snd_soc_register_card(dev, card); 1808 if (ret) 1809 dev_err_probe(dev, ret, "Could not register sound card\n"); 1810 1811 return ret; 1812 1813 } 1814 1815 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 1816 { 1817 struct vc4_hdmi *vc4_hdmi = priv; 1818 struct drm_connector *connector = &vc4_hdmi->connector; 1819 struct drm_device *dev = connector->dev; 1820 1821 if (dev && dev->registered) 1822 drm_connector_helper_hpd_irq_event(connector); 1823 1824 return IRQ_HANDLED; 1825 } 1826 1827 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 1828 { 1829 struct drm_connector *connector = &vc4_hdmi->connector; 1830 struct platform_device *pdev = vc4_hdmi->pdev; 1831 int ret; 1832 1833 if (vc4_hdmi->variant->external_irq_controller) { 1834 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 1835 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 1836 1837 ret = request_threaded_irq(hpd_con, 1838 NULL, 1839 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1840 "vc4 hdmi hpd connected", vc4_hdmi); 1841 if (ret) 1842 return ret; 1843 1844 ret = request_threaded_irq(hpd_rm, 1845 NULL, 1846 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1847 "vc4 hdmi hpd disconnected", vc4_hdmi); 1848 if (ret) { 1849 free_irq(hpd_con, vc4_hdmi); 1850 return ret; 1851 } 1852 1853 connector->polled = DRM_CONNECTOR_POLL_HPD; 1854 } 1855 1856 return 0; 1857 } 1858 1859 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi) 1860 { 1861 struct platform_device *pdev = vc4_hdmi->pdev; 1862 1863 if (vc4_hdmi->variant->external_irq_controller) { 1864 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi); 1865 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi); 1866 } 1867 } 1868 1869 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1870 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 1871 { 1872 struct vc4_hdmi *vc4_hdmi = priv; 1873 1874 if (vc4_hdmi->cec_rx_msg.len) 1875 cec_received_msg(vc4_hdmi->cec_adap, 1876 &vc4_hdmi->cec_rx_msg); 1877 1878 return IRQ_HANDLED; 1879 } 1880 1881 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 1882 { 1883 struct vc4_hdmi *vc4_hdmi = priv; 1884 1885 if (vc4_hdmi->cec_tx_ok) { 1886 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1887 0, 0, 0, 0); 1888 } else { 1889 /* 1890 * This CEC implementation makes 1 retry, so if we 1891 * get a NACK, then that means it made 2 attempts. 1892 */ 1893 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1894 0, 2, 0, 0); 1895 } 1896 return IRQ_HANDLED; 1897 } 1898 1899 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1900 { 1901 struct vc4_hdmi *vc4_hdmi = priv; 1902 irqreturn_t ret; 1903 1904 if (vc4_hdmi->cec_irq_was_rx) 1905 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 1906 else 1907 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 1908 1909 return ret; 1910 } 1911 1912 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1913 { 1914 struct drm_device *dev = vc4_hdmi->connector.dev; 1915 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1916 unsigned int i; 1917 1918 lockdep_assert_held(&vc4_hdmi->hw_lock); 1919 1920 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1921 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1922 1923 if (msg->len > 16) { 1924 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 1925 return; 1926 } 1927 1928 for (i = 0; i < msg->len; i += 4) { 1929 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 1930 1931 msg->msg[i] = val & 0xff; 1932 msg->msg[i + 1] = (val >> 8) & 0xff; 1933 msg->msg[i + 2] = (val >> 16) & 0xff; 1934 msg->msg[i + 3] = (val >> 24) & 0xff; 1935 } 1936 } 1937 1938 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1939 { 1940 u32 cntrl1; 1941 1942 lockdep_assert_held(&vc4_hdmi->hw_lock); 1943 1944 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1945 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1946 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1947 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1948 1949 return IRQ_WAKE_THREAD; 1950 } 1951 1952 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 1953 { 1954 struct vc4_hdmi *vc4_hdmi = priv; 1955 irqreturn_t ret; 1956 1957 spin_lock(&vc4_hdmi->hw_lock); 1958 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 1959 spin_unlock(&vc4_hdmi->hw_lock); 1960 1961 return ret; 1962 } 1963 1964 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1965 { 1966 u32 cntrl1; 1967 1968 lockdep_assert_held(&vc4_hdmi->hw_lock); 1969 1970 vc4_hdmi->cec_rx_msg.len = 0; 1971 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1972 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1973 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1974 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1975 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1976 1977 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1978 1979 return IRQ_WAKE_THREAD; 1980 } 1981 1982 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 1983 { 1984 struct vc4_hdmi *vc4_hdmi = priv; 1985 irqreturn_t ret; 1986 1987 spin_lock(&vc4_hdmi->hw_lock); 1988 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 1989 spin_unlock(&vc4_hdmi->hw_lock); 1990 1991 return ret; 1992 } 1993 1994 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1995 { 1996 struct vc4_hdmi *vc4_hdmi = priv; 1997 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1998 irqreturn_t ret; 1999 u32 cntrl5; 2000 2001 if (!(stat & VC4_HDMI_CPU_CEC)) 2002 return IRQ_NONE; 2003 2004 spin_lock(&vc4_hdmi->hw_lock); 2005 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2006 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2007 if (vc4_hdmi->cec_irq_was_rx) 2008 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2009 else 2010 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2011 2012 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2013 spin_unlock(&vc4_hdmi->hw_lock); 2014 2015 return ret; 2016 } 2017 2018 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2019 { 2020 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2021 /* clock period in microseconds */ 2022 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2023 unsigned long flags; 2024 u32 val; 2025 int ret; 2026 2027 /* 2028 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2029 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2030 * .detect or .get_modes might call .adap_enable, which leads to this 2031 * function being called with that mutex held. 2032 * 2033 * Concurrency is not an issue for the moment since we don't share any 2034 * state with KMS, so we can ignore the lock for now, but we need to 2035 * keep it in mind if we were to change that assumption. 2036 */ 2037 2038 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2039 if (ret) 2040 return ret; 2041 2042 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2043 2044 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2045 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2046 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2047 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2048 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2049 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2050 2051 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2052 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2053 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2054 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2055 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2056 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2057 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2058 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2059 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2060 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2061 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2062 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2063 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2064 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2065 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2066 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2067 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2068 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2069 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2070 2071 if (!vc4_hdmi->variant->external_irq_controller) 2072 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2073 2074 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2075 2076 return 0; 2077 } 2078 2079 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2080 { 2081 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2082 unsigned long flags; 2083 2084 /* 2085 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2086 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2087 * .detect or .get_modes might call .adap_enable, which leads to this 2088 * function being called with that mutex held. 2089 * 2090 * Concurrency is not an issue for the moment since we don't share any 2091 * state with KMS, so we can ignore the lock for now, but we need to 2092 * keep it in mind if we were to change that assumption. 2093 */ 2094 2095 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2096 2097 if (!vc4_hdmi->variant->external_irq_controller) 2098 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2099 2100 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2101 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2102 2103 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2104 2105 pm_runtime_put(&vc4_hdmi->pdev->dev); 2106 2107 return 0; 2108 } 2109 2110 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2111 { 2112 if (enable) 2113 return vc4_hdmi_cec_enable(adap); 2114 else 2115 return vc4_hdmi_cec_disable(adap); 2116 } 2117 2118 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2119 { 2120 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2121 unsigned long flags; 2122 2123 /* 2124 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2125 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2126 * .detect or .get_modes might call .adap_enable, which leads to this 2127 * function being called with that mutex held. 2128 * 2129 * Concurrency is not an issue for the moment since we don't share any 2130 * state with KMS, so we can ignore the lock for now, but we need to 2131 * keep it in mind if we were to change that assumption. 2132 */ 2133 2134 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2135 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2136 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2137 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2138 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2139 2140 return 0; 2141 } 2142 2143 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2144 u32 signal_free_time, struct cec_msg *msg) 2145 { 2146 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2147 struct drm_device *dev = vc4_hdmi->connector.dev; 2148 unsigned long flags; 2149 u32 val; 2150 unsigned int i; 2151 2152 /* 2153 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2154 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2155 * .detect or .get_modes might call .adap_enable, which leads to this 2156 * function being called with that mutex held. 2157 * 2158 * Concurrency is not an issue for the moment since we don't share any 2159 * state with KMS, so we can ignore the lock for now, but we need to 2160 * keep it in mind if we were to change that assumption. 2161 */ 2162 2163 if (msg->len > 16) { 2164 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2165 return -ENOMEM; 2166 } 2167 2168 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2169 2170 for (i = 0; i < msg->len; i += 4) 2171 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2172 (msg->msg[i]) | 2173 (msg->msg[i + 1] << 8) | 2174 (msg->msg[i + 2] << 16) | 2175 (msg->msg[i + 3] << 24)); 2176 2177 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2178 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2179 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2180 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2181 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2182 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2183 2184 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2185 2186 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2187 2188 return 0; 2189 } 2190 2191 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2192 .adap_enable = vc4_hdmi_cec_adap_enable, 2193 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2194 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2195 }; 2196 2197 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2198 { 2199 struct cec_connector_info conn_info; 2200 struct platform_device *pdev = vc4_hdmi->pdev; 2201 struct device *dev = &pdev->dev; 2202 unsigned long flags; 2203 u32 value; 2204 int ret; 2205 2206 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 2207 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2208 return 0; 2209 } 2210 2211 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2212 vc4_hdmi, "vc4", 2213 CEC_CAP_DEFAULTS | 2214 CEC_CAP_CONNECTOR_INFO, 1); 2215 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2216 if (ret < 0) 2217 return ret; 2218 2219 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2220 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2221 2222 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2223 value = HDMI_READ(HDMI_CEC_CNTRL_1); 2224 /* Set the logical address to Unregistered */ 2225 value |= VC4_HDMI_CEC_ADDR_MASK; 2226 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 2227 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2228 2229 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 2230 2231 if (vc4_hdmi->variant->external_irq_controller) { 2232 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"), 2233 vc4_cec_irq_handler_rx_bare, 2234 vc4_cec_irq_handler_rx_thread, 0, 2235 "vc4 hdmi cec rx", vc4_hdmi); 2236 if (ret) 2237 goto err_delete_cec_adap; 2238 2239 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"), 2240 vc4_cec_irq_handler_tx_bare, 2241 vc4_cec_irq_handler_tx_thread, 0, 2242 "vc4 hdmi cec tx", vc4_hdmi); 2243 if (ret) 2244 goto err_remove_cec_rx_handler; 2245 } else { 2246 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2247 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 2248 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2249 2250 ret = request_threaded_irq(platform_get_irq(pdev, 0), 2251 vc4_cec_irq_handler, 2252 vc4_cec_irq_handler_thread, 0, 2253 "vc4 hdmi cec", vc4_hdmi); 2254 if (ret) 2255 goto err_delete_cec_adap; 2256 } 2257 2258 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2259 if (ret < 0) 2260 goto err_remove_handlers; 2261 2262 return 0; 2263 2264 err_remove_handlers: 2265 if (vc4_hdmi->variant->external_irq_controller) 2266 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2267 else 2268 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2269 2270 err_remove_cec_rx_handler: 2271 if (vc4_hdmi->variant->external_irq_controller) 2272 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2273 2274 err_delete_cec_adap: 2275 cec_delete_adapter(vc4_hdmi->cec_adap); 2276 2277 return ret; 2278 } 2279 2280 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 2281 { 2282 struct platform_device *pdev = vc4_hdmi->pdev; 2283 2284 if (vc4_hdmi->variant->external_irq_controller) { 2285 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2286 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2287 } else { 2288 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2289 } 2290 2291 cec_unregister_adapter(vc4_hdmi->cec_adap); 2292 } 2293 #else 2294 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2295 { 2296 return 0; 2297 } 2298 2299 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 2300 2301 #endif 2302 2303 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 2304 struct debugfs_regset32 *regset, 2305 enum vc4_hdmi_regs reg) 2306 { 2307 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2308 struct debugfs_reg32 *regs, *new_regs; 2309 unsigned int count = 0; 2310 unsigned int i; 2311 2312 regs = kcalloc(variant->num_registers, sizeof(*regs), 2313 GFP_KERNEL); 2314 if (!regs) 2315 return -ENOMEM; 2316 2317 for (i = 0; i < variant->num_registers; i++) { 2318 const struct vc4_hdmi_register *field = &variant->registers[i]; 2319 2320 if (field->reg != reg) 2321 continue; 2322 2323 regs[count].name = field->name; 2324 regs[count].offset = field->offset; 2325 count++; 2326 } 2327 2328 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2329 if (!new_regs) 2330 return -ENOMEM; 2331 2332 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2333 regset->regs = new_regs; 2334 regset->nregs = count; 2335 2336 return 0; 2337 } 2338 2339 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2340 { 2341 struct platform_device *pdev = vc4_hdmi->pdev; 2342 struct device *dev = &pdev->dev; 2343 int ret; 2344 2345 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2346 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2347 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2348 2349 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2350 if (IS_ERR(vc4_hdmi->hd_regs)) 2351 return PTR_ERR(vc4_hdmi->hd_regs); 2352 2353 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2354 if (ret) 2355 return ret; 2356 2357 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2358 if (ret) 2359 return ret; 2360 2361 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2362 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2363 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2364 if (ret != -EPROBE_DEFER) 2365 DRM_ERROR("Failed to get pixel clock\n"); 2366 return ret; 2367 } 2368 2369 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2370 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2371 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2372 return PTR_ERR(vc4_hdmi->hsm_clock); 2373 } 2374 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2375 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2376 2377 return 0; 2378 } 2379 2380 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2381 { 2382 struct platform_device *pdev = vc4_hdmi->pdev; 2383 struct device *dev = &pdev->dev; 2384 struct resource *res; 2385 2386 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2387 if (!res) 2388 return -ENODEV; 2389 2390 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2391 resource_size(res)); 2392 if (!vc4_hdmi->hdmicore_regs) 2393 return -ENOMEM; 2394 2395 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2396 if (!res) 2397 return -ENODEV; 2398 2399 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2400 if (!vc4_hdmi->hd_regs) 2401 return -ENOMEM; 2402 2403 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2404 if (!res) 2405 return -ENODEV; 2406 2407 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2408 if (!vc4_hdmi->cec_regs) 2409 return -ENOMEM; 2410 2411 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2412 if (!res) 2413 return -ENODEV; 2414 2415 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2416 if (!vc4_hdmi->csc_regs) 2417 return -ENOMEM; 2418 2419 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2420 if (!res) 2421 return -ENODEV; 2422 2423 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2424 if (!vc4_hdmi->dvp_regs) 2425 return -ENOMEM; 2426 2427 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2428 if (!res) 2429 return -ENODEV; 2430 2431 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2432 if (!vc4_hdmi->phy_regs) 2433 return -ENOMEM; 2434 2435 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2436 if (!res) 2437 return -ENODEV; 2438 2439 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2440 if (!vc4_hdmi->ram_regs) 2441 return -ENOMEM; 2442 2443 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2444 if (!res) 2445 return -ENODEV; 2446 2447 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2448 if (!vc4_hdmi->rm_regs) 2449 return -ENOMEM; 2450 2451 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2452 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2453 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2454 return PTR_ERR(vc4_hdmi->hsm_clock); 2455 } 2456 2457 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2458 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2459 DRM_ERROR("Failed to get pixel bvb clock\n"); 2460 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2461 } 2462 2463 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2464 if (IS_ERR(vc4_hdmi->audio_clock)) { 2465 DRM_ERROR("Failed to get audio clock\n"); 2466 return PTR_ERR(vc4_hdmi->audio_clock); 2467 } 2468 2469 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2470 if (IS_ERR(vc4_hdmi->cec_clock)) { 2471 DRM_ERROR("Failed to get CEC clock\n"); 2472 return PTR_ERR(vc4_hdmi->cec_clock); 2473 } 2474 2475 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2476 if (IS_ERR(vc4_hdmi->reset)) { 2477 DRM_ERROR("Failed to get HDMI reset line\n"); 2478 return PTR_ERR(vc4_hdmi->reset); 2479 } 2480 2481 return 0; 2482 } 2483 2484 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev) 2485 { 2486 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2487 2488 clk_disable_unprepare(vc4_hdmi->hsm_clock); 2489 2490 return 0; 2491 } 2492 2493 static int vc4_hdmi_runtime_resume(struct device *dev) 2494 { 2495 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2496 int ret; 2497 2498 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 2499 if (ret) 2500 return ret; 2501 2502 return 0; 2503 } 2504 2505 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2506 { 2507 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2508 struct platform_device *pdev = to_platform_device(dev); 2509 struct drm_device *drm = dev_get_drvdata(master); 2510 struct vc4_hdmi *vc4_hdmi; 2511 struct drm_encoder *encoder; 2512 struct device_node *ddc_node; 2513 int ret; 2514 2515 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2516 if (!vc4_hdmi) 2517 return -ENOMEM; 2518 mutex_init(&vc4_hdmi->mutex); 2519 spin_lock_init(&vc4_hdmi->hw_lock); 2520 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2521 2522 dev_set_drvdata(dev, vc4_hdmi); 2523 encoder = &vc4_hdmi->encoder.base.base; 2524 vc4_hdmi->encoder.base.type = variant->encoder_type; 2525 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2526 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2527 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2528 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2529 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2530 vc4_hdmi->pdev = pdev; 2531 vc4_hdmi->variant = variant; 2532 2533 /* 2534 * Since we don't know the state of the controller and its 2535 * display (if any), let's assume it's always enabled. 2536 * vc4_hdmi_disable_scrambling() will thus run at boot, make 2537 * sure it's disabled, and avoid any inconsistency. 2538 */ 2539 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 2540 vc4_hdmi->scdc_enabled = true; 2541 2542 ret = variant->init_resources(vc4_hdmi); 2543 if (ret) 2544 return ret; 2545 2546 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2547 if (!ddc_node) { 2548 DRM_ERROR("Failed to find ddc node in device tree\n"); 2549 return -ENODEV; 2550 } 2551 2552 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2553 of_node_put(ddc_node); 2554 if (!vc4_hdmi->ddc) { 2555 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2556 return -EPROBE_DEFER; 2557 } 2558 2559 /* Only use the GPIO HPD pin if present in the DT, otherwise 2560 * we'll use the HDMI core's register. 2561 */ 2562 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2563 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2564 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2565 goto err_put_ddc; 2566 } 2567 2568 vc4_hdmi->disable_wifi_frequencies = 2569 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2570 2571 if (variant->max_pixel_clock == 600000000) { 2572 struct vc4_dev *vc4 = to_vc4_dev(drm); 2573 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2574 2575 if (max_rate < 550000000) 2576 vc4_hdmi->disable_4kp60 = true; 2577 } 2578 2579 /* 2580 * If we boot without any cable connected to the HDMI connector, 2581 * the firmware will skip the HSM initialization and leave it 2582 * with a rate of 0, resulting in a bus lockup when we're 2583 * accessing the registers even if it's enabled. 2584 * 2585 * Let's put a sensible default at runtime_resume so that we 2586 * don't end up in this situation. 2587 */ 2588 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ); 2589 if (ret) 2590 goto err_put_ddc; 2591 2592 /* 2593 * We need to have the device powered up at this point to call 2594 * our reset hook and for the CEC init. 2595 */ 2596 ret = vc4_hdmi_runtime_resume(dev); 2597 if (ret) 2598 goto err_put_ddc; 2599 2600 pm_runtime_get_noresume(dev); 2601 pm_runtime_set_active(dev); 2602 pm_runtime_enable(dev); 2603 2604 if (vc4_hdmi->variant->reset) 2605 vc4_hdmi->variant->reset(vc4_hdmi); 2606 2607 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2608 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2609 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2610 clk_prepare_enable(vc4_hdmi->pixel_clock); 2611 clk_prepare_enable(vc4_hdmi->hsm_clock); 2612 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2613 } 2614 2615 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2616 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2617 2618 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2619 if (ret) 2620 goto err_destroy_encoder; 2621 2622 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 2623 if (ret) 2624 goto err_destroy_conn; 2625 2626 ret = vc4_hdmi_cec_init(vc4_hdmi); 2627 if (ret) 2628 goto err_free_hotplug; 2629 2630 ret = vc4_hdmi_audio_init(vc4_hdmi); 2631 if (ret) 2632 goto err_free_cec; 2633 2634 vc4_debugfs_add_file(drm, variant->debugfs_name, 2635 vc4_hdmi_debugfs_regs, 2636 vc4_hdmi); 2637 2638 pm_runtime_put_sync(dev); 2639 2640 return 0; 2641 2642 err_free_cec: 2643 vc4_hdmi_cec_exit(vc4_hdmi); 2644 err_free_hotplug: 2645 vc4_hdmi_hotplug_exit(vc4_hdmi); 2646 err_destroy_conn: 2647 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2648 err_destroy_encoder: 2649 drm_encoder_cleanup(encoder); 2650 pm_runtime_put_sync(dev); 2651 pm_runtime_disable(dev); 2652 err_put_ddc: 2653 put_device(&vc4_hdmi->ddc->dev); 2654 2655 return ret; 2656 } 2657 2658 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2659 void *data) 2660 { 2661 struct vc4_hdmi *vc4_hdmi; 2662 2663 /* 2664 * ASoC makes it a bit hard to retrieve a pointer to the 2665 * vc4_hdmi structure. Registering the card will overwrite our 2666 * device drvdata with a pointer to the snd_soc_card structure, 2667 * which can then be used to retrieve whatever drvdata we want 2668 * to associate. 2669 * 2670 * However, that doesn't fly in the case where we wouldn't 2671 * register an ASoC card (because of an old DT that is missing 2672 * the dmas properties for example), then the card isn't 2673 * registered and the device drvdata wouldn't be set. 2674 * 2675 * We can deal with both cases by making sure a snd_soc_card 2676 * pointer and a vc4_hdmi structure are pointing to the same 2677 * memory address, so we can treat them indistinctly without any 2678 * issue. 2679 */ 2680 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2681 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2682 vc4_hdmi = dev_get_drvdata(dev); 2683 2684 kfree(vc4_hdmi->hdmi_regset.regs); 2685 kfree(vc4_hdmi->hd_regset.regs); 2686 2687 vc4_hdmi_cec_exit(vc4_hdmi); 2688 vc4_hdmi_hotplug_exit(vc4_hdmi); 2689 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2690 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 2691 2692 pm_runtime_disable(dev); 2693 2694 put_device(&vc4_hdmi->ddc->dev); 2695 } 2696 2697 static const struct component_ops vc4_hdmi_ops = { 2698 .bind = vc4_hdmi_bind, 2699 .unbind = vc4_hdmi_unbind, 2700 }; 2701 2702 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 2703 { 2704 return component_add(&pdev->dev, &vc4_hdmi_ops); 2705 } 2706 2707 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 2708 { 2709 component_del(&pdev->dev, &vc4_hdmi_ops); 2710 return 0; 2711 } 2712 2713 static const struct vc4_hdmi_variant bcm2835_variant = { 2714 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2715 .debugfs_name = "hdmi_regs", 2716 .card_name = "vc4-hdmi", 2717 .max_pixel_clock = 162000000, 2718 .registers = vc4_hdmi_fields, 2719 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 2720 2721 .init_resources = vc4_hdmi_init_resources, 2722 .csc_setup = vc4_hdmi_csc_setup, 2723 .reset = vc4_hdmi_reset, 2724 .set_timings = vc4_hdmi_set_timings, 2725 .phy_init = vc4_hdmi_phy_init, 2726 .phy_disable = vc4_hdmi_phy_disable, 2727 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 2728 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 2729 .channel_map = vc4_hdmi_channel_map, 2730 .supports_hdr = false, 2731 }; 2732 2733 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 2734 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2735 .debugfs_name = "hdmi0_regs", 2736 .card_name = "vc4-hdmi-0", 2737 .max_pixel_clock = 600000000, 2738 .registers = vc5_hdmi_hdmi0_fields, 2739 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 2740 .phy_lane_mapping = { 2741 PHY_LANE_0, 2742 PHY_LANE_1, 2743 PHY_LANE_2, 2744 PHY_LANE_CK, 2745 }, 2746 .unsupported_odd_h_timings = true, 2747 .external_irq_controller = true, 2748 2749 .init_resources = vc5_hdmi_init_resources, 2750 .csc_setup = vc5_hdmi_csc_setup, 2751 .reset = vc5_hdmi_reset, 2752 .set_timings = vc5_hdmi_set_timings, 2753 .phy_init = vc5_hdmi_phy_init, 2754 .phy_disable = vc5_hdmi_phy_disable, 2755 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2756 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2757 .channel_map = vc5_hdmi_channel_map, 2758 .supports_hdr = true, 2759 .hp_detect = vc5_hdmi_hp_detect, 2760 }; 2761 2762 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 2763 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 2764 .debugfs_name = "hdmi1_regs", 2765 .card_name = "vc4-hdmi-1", 2766 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2767 .registers = vc5_hdmi_hdmi1_fields, 2768 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 2769 .phy_lane_mapping = { 2770 PHY_LANE_1, 2771 PHY_LANE_0, 2772 PHY_LANE_CK, 2773 PHY_LANE_2, 2774 }, 2775 .unsupported_odd_h_timings = true, 2776 .external_irq_controller = true, 2777 2778 .init_resources = vc5_hdmi_init_resources, 2779 .csc_setup = vc5_hdmi_csc_setup, 2780 .reset = vc5_hdmi_reset, 2781 .set_timings = vc5_hdmi_set_timings, 2782 .phy_init = vc5_hdmi_phy_init, 2783 .phy_disable = vc5_hdmi_phy_disable, 2784 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2785 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2786 .channel_map = vc5_hdmi_channel_map, 2787 .supports_hdr = true, 2788 .hp_detect = vc5_hdmi_hp_detect, 2789 }; 2790 2791 static const struct of_device_id vc4_hdmi_dt_match[] = { 2792 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 2793 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 2794 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 2795 {} 2796 }; 2797 2798 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 2799 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 2800 vc4_hdmi_runtime_resume, 2801 NULL) 2802 }; 2803 2804 struct platform_driver vc4_hdmi_driver = { 2805 .probe = vc4_hdmi_dev_probe, 2806 .remove = vc4_hdmi_dev_remove, 2807 .driver = { 2808 .name = "vc4_hdmi", 2809 .of_match_table = vc4_hdmi_dt_match, 2810 .pm = &vc4_hdmi_pm_ops, 2811 }, 2812 }; 2813