1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <linux/clk.h> 38 #include <linux/component.h> 39 #include <linux/i2c.h> 40 #include <linux/of_address.h> 41 #include <linux/of_gpio.h> 42 #include <linux/of_platform.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/rational.h> 45 #include <sound/dmaengine_pcm.h> 46 #include <sound/pcm_drm_eld.h> 47 #include <sound/pcm_params.h> 48 #include <sound/soc.h> 49 #include "media/cec.h" 50 #include "vc4_drv.h" 51 #include "vc4_regs.h" 52 53 #define HSM_CLOCK_FREQ 163682864 54 #define CEC_CLOCK_FREQ 40000 55 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ) 56 57 /* HDMI audio information */ 58 struct vc4_hdmi_audio { 59 struct snd_soc_card card; 60 struct snd_soc_dai_link link; 61 struct snd_soc_dai_link_component cpu; 62 struct snd_soc_dai_link_component codec; 63 int samplerate; 64 int channels; 65 struct snd_dmaengine_dai_dma_data dma_data; 66 struct snd_pcm_substream *substream; 67 }; 68 69 /* General HDMI hardware state. */ 70 struct vc4_hdmi { 71 struct platform_device *pdev; 72 73 struct drm_encoder *encoder; 74 struct drm_connector *connector; 75 76 struct vc4_hdmi_audio audio; 77 78 struct i2c_adapter *ddc; 79 void __iomem *hdmicore_regs; 80 void __iomem *hd_regs; 81 int hpd_gpio; 82 bool hpd_active_low; 83 84 struct cec_adapter *cec_adap; 85 struct cec_msg cec_rx_msg; 86 bool cec_tx_ok; 87 bool cec_irq_was_rx; 88 89 struct clk *pixel_clock; 90 struct clk *hsm_clock; 91 92 struct debugfs_regset32 hdmi_regset; 93 struct debugfs_regset32 hd_regset; 94 }; 95 96 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 97 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 98 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 99 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 100 101 /* VC4 HDMI encoder KMS struct */ 102 struct vc4_hdmi_encoder { 103 struct vc4_encoder base; 104 bool hdmi_monitor; 105 bool limited_rgb_range; 106 }; 107 108 static inline struct vc4_hdmi_encoder * 109 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 110 { 111 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 112 } 113 114 /* VC4 HDMI connector KMS struct */ 115 struct vc4_hdmi_connector { 116 struct drm_connector base; 117 118 /* Since the connector is attached to just the one encoder, 119 * this is the reference to it so we can do the best_encoder() 120 * hook. 121 */ 122 struct drm_encoder *encoder; 123 }; 124 125 static inline struct vc4_hdmi_connector * 126 to_vc4_hdmi_connector(struct drm_connector *connector) 127 { 128 return container_of(connector, struct vc4_hdmi_connector, base); 129 } 130 131 static const struct debugfs_reg32 hdmi_regs[] = { 132 VC4_REG32(VC4_HDMI_CORE_REV), 133 VC4_REG32(VC4_HDMI_SW_RESET_CONTROL), 134 VC4_REG32(VC4_HDMI_HOTPLUG_INT), 135 VC4_REG32(VC4_HDMI_HOTPLUG), 136 VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP), 137 VC4_REG32(VC4_HDMI_MAI_CONFIG), 138 VC4_REG32(VC4_HDMI_MAI_FORMAT), 139 VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG), 140 VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG), 141 VC4_REG32(VC4_HDMI_HORZA), 142 VC4_REG32(VC4_HDMI_HORZB), 143 VC4_REG32(VC4_HDMI_FIFO_CTL), 144 VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL), 145 VC4_REG32(VC4_HDMI_VERTA0), 146 VC4_REG32(VC4_HDMI_VERTA1), 147 VC4_REG32(VC4_HDMI_VERTB0), 148 VC4_REG32(VC4_HDMI_VERTB1), 149 VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL), 150 VC4_REG32(VC4_HDMI_TX_PHY_CTL0), 151 152 VC4_REG32(VC4_HDMI_CEC_CNTRL_1), 153 VC4_REG32(VC4_HDMI_CEC_CNTRL_2), 154 VC4_REG32(VC4_HDMI_CEC_CNTRL_3), 155 VC4_REG32(VC4_HDMI_CEC_CNTRL_4), 156 VC4_REG32(VC4_HDMI_CEC_CNTRL_5), 157 VC4_REG32(VC4_HDMI_CPU_STATUS), 158 VC4_REG32(VC4_HDMI_CPU_MASK_STATUS), 159 160 VC4_REG32(VC4_HDMI_CEC_RX_DATA_1), 161 VC4_REG32(VC4_HDMI_CEC_RX_DATA_2), 162 VC4_REG32(VC4_HDMI_CEC_RX_DATA_3), 163 VC4_REG32(VC4_HDMI_CEC_RX_DATA_4), 164 VC4_REG32(VC4_HDMI_CEC_TX_DATA_1), 165 VC4_REG32(VC4_HDMI_CEC_TX_DATA_2), 166 VC4_REG32(VC4_HDMI_CEC_TX_DATA_3), 167 VC4_REG32(VC4_HDMI_CEC_TX_DATA_4), 168 }; 169 170 static const struct debugfs_reg32 hd_regs[] = { 171 VC4_REG32(VC4_HD_M_CTL), 172 VC4_REG32(VC4_HD_MAI_CTL), 173 VC4_REG32(VC4_HD_MAI_THR), 174 VC4_REG32(VC4_HD_MAI_FMT), 175 VC4_REG32(VC4_HD_MAI_SMP), 176 VC4_REG32(VC4_HD_VID_CTL), 177 VC4_REG32(VC4_HD_CSC_CTL), 178 VC4_REG32(VC4_HD_FRAME_COUNT), 179 }; 180 181 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 182 { 183 struct drm_info_node *node = (struct drm_info_node *)m->private; 184 struct drm_device *dev = node->minor->dev; 185 struct vc4_dev *vc4 = to_vc4_dev(dev); 186 struct vc4_hdmi *hdmi = vc4->hdmi; 187 struct drm_printer p = drm_seq_file_printer(m); 188 189 drm_print_regset32(&p, &hdmi->hdmi_regset); 190 drm_print_regset32(&p, &hdmi->hd_regset); 191 192 return 0; 193 } 194 195 static enum drm_connector_status 196 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 197 { 198 struct drm_device *dev = connector->dev; 199 struct vc4_dev *vc4 = to_vc4_dev(dev); 200 201 if (vc4->hdmi->hpd_gpio) { 202 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 203 vc4->hdmi->hpd_active_low) 204 return connector_status_connected; 205 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 206 return connector_status_disconnected; 207 } 208 209 if (drm_probe_ddc(vc4->hdmi->ddc)) 210 return connector_status_connected; 211 212 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 213 return connector_status_connected; 214 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 215 return connector_status_disconnected; 216 } 217 218 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 219 { 220 drm_connector_unregister(connector); 221 drm_connector_cleanup(connector); 222 } 223 224 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 225 { 226 struct vc4_hdmi_connector *vc4_connector = 227 to_vc4_hdmi_connector(connector); 228 struct drm_encoder *encoder = vc4_connector->encoder; 229 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 230 struct drm_device *dev = connector->dev; 231 struct vc4_dev *vc4 = to_vc4_dev(dev); 232 int ret = 0; 233 struct edid *edid; 234 235 edid = drm_get_edid(connector, vc4->hdmi->ddc); 236 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid); 237 if (!edid) 238 return -ENODEV; 239 240 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 241 242 drm_connector_update_edid_property(connector, edid); 243 ret = drm_add_edid_modes(connector, edid); 244 kfree(edid); 245 246 return ret; 247 } 248 249 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 250 .detect = vc4_hdmi_connector_detect, 251 .fill_modes = drm_helper_probe_single_connector_modes, 252 .destroy = vc4_hdmi_connector_destroy, 253 .reset = drm_atomic_helper_connector_reset, 254 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 255 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 256 }; 257 258 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 259 .get_modes = vc4_hdmi_connector_get_modes, 260 }; 261 262 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 263 struct drm_encoder *encoder) 264 { 265 struct drm_connector *connector; 266 struct vc4_hdmi_connector *hdmi_connector; 267 int ret; 268 269 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 270 GFP_KERNEL); 271 if (!hdmi_connector) 272 return ERR_PTR(-ENOMEM); 273 connector = &hdmi_connector->base; 274 275 hdmi_connector->encoder = encoder; 276 277 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, 278 DRM_MODE_CONNECTOR_HDMIA); 279 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 280 281 /* Create and attach TV margin props to this connector. */ 282 ret = drm_mode_create_tv_margin_properties(dev); 283 if (ret) 284 return ERR_PTR(ret); 285 286 drm_connector_attach_tv_margin_properties(connector); 287 288 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 289 DRM_CONNECTOR_POLL_DISCONNECT); 290 291 connector->interlace_allowed = 1; 292 connector->doublescan_allowed = 0; 293 294 drm_connector_attach_encoder(connector, encoder); 295 296 return connector; 297 } 298 299 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) 300 { 301 drm_encoder_cleanup(encoder); 302 } 303 304 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 305 .destroy = vc4_hdmi_encoder_destroy, 306 }; 307 308 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 309 enum hdmi_infoframe_type type) 310 { 311 struct drm_device *dev = encoder->dev; 312 struct vc4_dev *vc4 = to_vc4_dev(dev); 313 u32 packet_id = type - 0x80; 314 315 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 316 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 317 318 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 319 BIT(packet_id)), 100); 320 } 321 322 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 323 union hdmi_infoframe *frame) 324 { 325 struct drm_device *dev = encoder->dev; 326 struct vc4_dev *vc4 = to_vc4_dev(dev); 327 u32 packet_id = frame->any.type - 0x80; 328 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id); 329 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 330 ssize_t len, i; 331 int ret; 332 333 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 334 VC4_HDMI_RAM_PACKET_ENABLE), 335 "Packet RAM has to be on to store the packet."); 336 337 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 338 if (len < 0) 339 return; 340 341 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 342 if (ret) { 343 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 344 return; 345 } 346 347 for (i = 0; i < len; i += 7) { 348 HDMI_WRITE(packet_reg, 349 buffer[i + 0] << 0 | 350 buffer[i + 1] << 8 | 351 buffer[i + 2] << 16); 352 packet_reg += 4; 353 354 HDMI_WRITE(packet_reg, 355 buffer[i + 3] << 0 | 356 buffer[i + 4] << 8 | 357 buffer[i + 5] << 16 | 358 buffer[i + 6] << 24); 359 packet_reg += 4; 360 } 361 362 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 363 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 364 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 365 BIT(packet_id)), 100); 366 if (ret) 367 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 368 } 369 370 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 371 { 372 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 373 struct vc4_dev *vc4 = encoder->dev->dev_private; 374 struct vc4_hdmi *hdmi = vc4->hdmi; 375 struct drm_connector_state *cstate = hdmi->connector->state; 376 struct drm_crtc *crtc = encoder->crtc; 377 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 378 union hdmi_infoframe frame; 379 int ret; 380 381 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 382 hdmi->connector, mode); 383 if (ret < 0) { 384 DRM_ERROR("couldn't fill AVI infoframe\n"); 385 return; 386 } 387 388 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 389 hdmi->connector, mode, 390 vc4_encoder->limited_rgb_range ? 391 HDMI_QUANTIZATION_RANGE_LIMITED : 392 HDMI_QUANTIZATION_RANGE_FULL); 393 394 frame.avi.right_bar = cstate->tv.margins.right; 395 frame.avi.left_bar = cstate->tv.margins.left; 396 frame.avi.top_bar = cstate->tv.margins.top; 397 frame.avi.bottom_bar = cstate->tv.margins.bottom; 398 399 vc4_hdmi_write_infoframe(encoder, &frame); 400 } 401 402 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 403 { 404 union hdmi_infoframe frame; 405 int ret; 406 407 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 408 if (ret < 0) { 409 DRM_ERROR("couldn't fill SPD infoframe\n"); 410 return; 411 } 412 413 frame.spd.sdi = HDMI_SPD_SDI_PC; 414 415 vc4_hdmi_write_infoframe(encoder, &frame); 416 } 417 418 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 419 { 420 struct drm_device *drm = encoder->dev; 421 struct vc4_dev *vc4 = drm->dev_private; 422 struct vc4_hdmi *hdmi = vc4->hdmi; 423 union hdmi_infoframe frame; 424 int ret; 425 426 ret = hdmi_audio_infoframe_init(&frame.audio); 427 428 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 429 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 430 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 431 frame.audio.channels = hdmi->audio.channels; 432 433 vc4_hdmi_write_infoframe(encoder, &frame); 434 } 435 436 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 437 { 438 vc4_hdmi_set_avi_infoframe(encoder); 439 vc4_hdmi_set_spd_infoframe(encoder); 440 } 441 442 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 443 { 444 struct drm_device *dev = encoder->dev; 445 struct vc4_dev *vc4 = to_vc4_dev(dev); 446 struct vc4_hdmi *hdmi = vc4->hdmi; 447 int ret; 448 449 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); 450 451 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 452 HD_WRITE(VC4_HD_VID_CTL, 453 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 454 455 clk_disable_unprepare(hdmi->pixel_clock); 456 457 ret = pm_runtime_put(&hdmi->pdev->dev); 458 if (ret < 0) 459 DRM_ERROR("Failed to release power domain: %d\n", ret); 460 } 461 462 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 463 { 464 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 465 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 466 struct drm_device *dev = encoder->dev; 467 struct vc4_dev *vc4 = to_vc4_dev(dev); 468 struct vc4_hdmi *hdmi = vc4->hdmi; 469 bool debug_dump_regs = false; 470 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 471 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 472 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 473 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 474 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 475 VC4_HDMI_VERTA_VSP) | 476 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 477 VC4_HDMI_VERTA_VFP) | 478 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 479 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 480 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 481 VC4_HDMI_VERTB_VBP)); 482 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 483 VC4_SET_FIELD(mode->crtc_vtotal - 484 mode->crtc_vsync_end - 485 interlaced, 486 VC4_HDMI_VERTB_VBP)); 487 u32 csc_ctl; 488 int ret; 489 490 ret = pm_runtime_get_sync(&hdmi->pdev->dev); 491 if (ret < 0) { 492 DRM_ERROR("Failed to retain power domain: %d\n", ret); 493 return; 494 } 495 496 ret = clk_set_rate(hdmi->pixel_clock, 497 mode->clock * 1000 * 498 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1)); 499 if (ret) { 500 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 501 return; 502 } 503 504 ret = clk_prepare_enable(hdmi->pixel_clock); 505 if (ret) { 506 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 507 return; 508 } 509 510 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 511 VC4_HDMI_SW_RESET_HDMI | 512 VC4_HDMI_SW_RESET_FORMAT_DETECT); 513 514 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 515 516 /* PHY should be in reset, like 517 * vc4_hdmi_encoder_disable() does. 518 */ 519 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 520 521 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 522 523 if (debug_dump_regs) { 524 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 525 526 dev_info(&hdmi->pdev->dev, "HDMI regs before:\n"); 527 drm_print_regset32(&p, &hdmi->hdmi_regset); 528 drm_print_regset32(&p, &hdmi->hd_regset); 529 } 530 531 HD_WRITE(VC4_HD_VID_CTL, 0); 532 533 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 534 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 535 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 536 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 537 538 HDMI_WRITE(VC4_HDMI_HORZA, 539 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 540 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 541 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 542 VC4_HDMI_HORZA_HAP)); 543 544 HDMI_WRITE(VC4_HDMI_HORZB, 545 VC4_SET_FIELD((mode->htotal - 546 mode->hsync_end) * pixel_rep, 547 VC4_HDMI_HORZB_HBP) | 548 VC4_SET_FIELD((mode->hsync_end - 549 mode->hsync_start) * pixel_rep, 550 VC4_HDMI_HORZB_HSP) | 551 VC4_SET_FIELD((mode->hsync_start - 552 mode->hdisplay) * pixel_rep, 553 VC4_HDMI_HORZB_HFP)); 554 555 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 556 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 557 558 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); 559 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 560 561 HD_WRITE(VC4_HD_VID_CTL, 562 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 563 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 564 565 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 566 VC4_HD_CSC_CTL_ORDER); 567 568 if (vc4_encoder->hdmi_monitor && 569 drm_default_rgb_quant_range(mode) == 570 HDMI_QUANTIZATION_RANGE_LIMITED) { 571 /* CEA VICs other than #1 requre limited range RGB 572 * output unless overridden by an AVI infoframe. 573 * Apply a colorspace conversion to squash 0-255 down 574 * to 16-235. The matrix here is: 575 * 576 * [ 0 0 0.8594 16] 577 * [ 0 0.8594 0 16] 578 * [ 0.8594 0 0 16] 579 * [ 0 0 0 1] 580 */ 581 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 582 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 583 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 584 VC4_HD_CSC_CTL_MODE); 585 586 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); 587 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); 588 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); 589 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); 590 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); 591 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); 592 vc4_encoder->limited_rgb_range = true; 593 } else { 594 vc4_encoder->limited_rgb_range = false; 595 } 596 597 /* The RGB order applies even when CSC is disabled. */ 598 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); 599 600 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 601 602 if (debug_dump_regs) { 603 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 604 605 dev_info(&hdmi->pdev->dev, "HDMI regs after:\n"); 606 drm_print_regset32(&p, &hdmi->hdmi_regset); 607 drm_print_regset32(&p, &hdmi->hd_regset); 608 } 609 610 HD_WRITE(VC4_HD_VID_CTL, 611 HD_READ(VC4_HD_VID_CTL) | 612 VC4_HD_VID_CTL_ENABLE | 613 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 614 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 615 616 if (vc4_encoder->hdmi_monitor) { 617 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 618 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 619 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 620 621 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 622 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 623 WARN_ONCE(ret, "Timeout waiting for " 624 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 625 } else { 626 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 627 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 628 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 629 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 630 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 631 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 632 633 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 634 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 635 WARN_ONCE(ret, "Timeout waiting for " 636 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 637 } 638 639 if (vc4_encoder->hdmi_monitor) { 640 u32 drift; 641 642 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 643 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 644 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 645 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 646 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 647 648 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 649 VC4_HDMI_RAM_PACKET_ENABLE); 650 651 vc4_hdmi_set_infoframes(encoder); 652 653 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 654 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 655 656 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 657 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 658 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 659 drift | VC4_HDMI_FIFO_CTL_RECENTER); 660 usleep_range(1000, 1100); 661 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 662 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 663 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 664 drift | VC4_HDMI_FIFO_CTL_RECENTER); 665 666 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 667 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 668 WARN_ONCE(ret, "Timeout waiting for " 669 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 670 } 671 } 672 673 static enum drm_mode_status 674 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc, 675 const struct drm_display_mode *mode) 676 { 677 /* HSM clock must be 108% of the pixel clock. Additionally, 678 * the AXI clock needs to be at least 25% of pixel clock, but 679 * HSM ends up being the limiting factor. 680 */ 681 if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100)) 682 return MODE_CLOCK_HIGH; 683 684 return MODE_OK; 685 } 686 687 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 688 .mode_valid = vc4_hdmi_encoder_mode_valid, 689 .disable = vc4_hdmi_encoder_disable, 690 .enable = vc4_hdmi_encoder_enable, 691 }; 692 693 /* HDMI audio codec callbacks */ 694 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi) 695 { 696 struct drm_device *drm = hdmi->encoder->dev; 697 struct vc4_dev *vc4 = to_vc4_dev(drm); 698 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock); 699 unsigned long n, m; 700 701 rational_best_approximation(hsm_clock, hdmi->audio.samplerate, 702 VC4_HD_MAI_SMP_N_MASK >> 703 VC4_HD_MAI_SMP_N_SHIFT, 704 (VC4_HD_MAI_SMP_M_MASK >> 705 VC4_HD_MAI_SMP_M_SHIFT) + 1, 706 &n, &m); 707 708 HD_WRITE(VC4_HD_MAI_SMP, 709 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 710 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 711 } 712 713 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi) 714 { 715 struct drm_encoder *encoder = hdmi->encoder; 716 struct drm_crtc *crtc = encoder->crtc; 717 struct drm_device *drm = encoder->dev; 718 struct vc4_dev *vc4 = to_vc4_dev(drm); 719 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 720 u32 samplerate = hdmi->audio.samplerate; 721 u32 n, cts; 722 u64 tmp; 723 724 n = 128 * samplerate / 1000; 725 tmp = (u64)(mode->clock * 1000) * n; 726 do_div(tmp, 128 * samplerate); 727 cts = tmp; 728 729 HDMI_WRITE(VC4_HDMI_CRP_CFG, 730 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 731 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 732 733 /* 734 * We could get slightly more accurate clocks in some cases by 735 * providing a CTS_1 value. The two CTS values are alternated 736 * between based on the period fields 737 */ 738 HDMI_WRITE(VC4_HDMI_CTS_0, cts); 739 HDMI_WRITE(VC4_HDMI_CTS_1, cts); 740 } 741 742 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 743 { 744 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 745 746 return snd_soc_card_get_drvdata(card); 747 } 748 749 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 750 struct snd_soc_dai *dai) 751 { 752 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 753 struct drm_encoder *encoder = hdmi->encoder; 754 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev); 755 int ret; 756 757 if (hdmi->audio.substream && hdmi->audio.substream != substream) 758 return -EINVAL; 759 760 hdmi->audio.substream = substream; 761 762 /* 763 * If the HDMI encoder hasn't probed, or the encoder is 764 * currently in DVI mode, treat the codec dai as missing. 765 */ 766 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 767 VC4_HDMI_RAM_PACKET_ENABLE)) 768 return -ENODEV; 769 770 ret = snd_pcm_hw_constraint_eld(substream->runtime, 771 hdmi->connector->eld); 772 if (ret) 773 return ret; 774 775 return 0; 776 } 777 778 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 779 { 780 return 0; 781 } 782 783 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi) 784 { 785 struct drm_encoder *encoder = hdmi->encoder; 786 struct drm_device *drm = encoder->dev; 787 struct device *dev = &hdmi->pdev->dev; 788 struct vc4_dev *vc4 = to_vc4_dev(drm); 789 int ret; 790 791 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 792 if (ret) 793 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 794 795 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET); 796 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 797 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 798 } 799 800 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 801 struct snd_soc_dai *dai) 802 { 803 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 804 805 if (substream != hdmi->audio.substream) 806 return; 807 808 vc4_hdmi_audio_reset(hdmi); 809 810 hdmi->audio.substream = NULL; 811 } 812 813 /* HDMI audio codec callbacks */ 814 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 815 struct snd_pcm_hw_params *params, 816 struct snd_soc_dai *dai) 817 { 818 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 819 struct drm_encoder *encoder = hdmi->encoder; 820 struct drm_device *drm = encoder->dev; 821 struct device *dev = &hdmi->pdev->dev; 822 struct vc4_dev *vc4 = to_vc4_dev(drm); 823 u32 audio_packet_config, channel_mask; 824 u32 channel_map, i; 825 826 if (substream != hdmi->audio.substream) 827 return -EINVAL; 828 829 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 830 params_rate(params), params_width(params), 831 params_channels(params)); 832 833 hdmi->audio.channels = params_channels(params); 834 hdmi->audio.samplerate = params_rate(params); 835 836 HD_WRITE(VC4_HD_MAI_CTL, 837 VC4_HD_MAI_CTL_RESET | 838 VC4_HD_MAI_CTL_FLUSH | 839 VC4_HD_MAI_CTL_DLATE | 840 VC4_HD_MAI_CTL_ERRORE | 841 VC4_HD_MAI_CTL_ERRORF); 842 843 vc4_hdmi_audio_set_mai_clock(hdmi); 844 845 audio_packet_config = 846 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 847 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 848 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 849 850 channel_mask = GENMASK(hdmi->audio.channels - 1, 0); 851 audio_packet_config |= VC4_SET_FIELD(channel_mask, 852 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 853 854 /* Set the MAI threshold. This logic mimics the firmware's. */ 855 if (hdmi->audio.samplerate > 96000) { 856 HD_WRITE(VC4_HD_MAI_THR, 857 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 858 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 859 } else if (hdmi->audio.samplerate > 48000) { 860 HD_WRITE(VC4_HD_MAI_THR, 861 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 862 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 863 } else { 864 HD_WRITE(VC4_HD_MAI_THR, 865 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 866 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 867 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 868 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 869 } 870 871 HDMI_WRITE(VC4_HDMI_MAI_CONFIG, 872 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 873 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 874 875 channel_map = 0; 876 for (i = 0; i < 8; i++) { 877 if (channel_mask & BIT(i)) 878 channel_map |= i << (3 * i); 879 } 880 881 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map); 882 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 883 vc4_hdmi_set_n_cts(hdmi); 884 885 return 0; 886 } 887 888 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 889 struct snd_soc_dai *dai) 890 { 891 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 892 struct drm_encoder *encoder = hdmi->encoder; 893 struct drm_device *drm = encoder->dev; 894 struct vc4_dev *vc4 = to_vc4_dev(drm); 895 896 switch (cmd) { 897 case SNDRV_PCM_TRIGGER_START: 898 vc4_hdmi_set_audio_infoframe(encoder); 899 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 900 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) & 901 ~VC4_HDMI_TX_PHY_RNG_PWRDN); 902 HD_WRITE(VC4_HD_MAI_CTL, 903 VC4_SET_FIELD(hdmi->audio.channels, 904 VC4_HD_MAI_CTL_CHNUM) | 905 VC4_HD_MAI_CTL_ENABLE); 906 break; 907 case SNDRV_PCM_TRIGGER_STOP: 908 HD_WRITE(VC4_HD_MAI_CTL, 909 VC4_HD_MAI_CTL_DLATE | 910 VC4_HD_MAI_CTL_ERRORE | 911 VC4_HD_MAI_CTL_ERRORF); 912 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 913 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) | 914 VC4_HDMI_TX_PHY_RNG_PWRDN); 915 break; 916 default: 917 break; 918 } 919 920 return 0; 921 } 922 923 static inline struct vc4_hdmi * 924 snd_component_to_hdmi(struct snd_soc_component *component) 925 { 926 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 927 928 return snd_soc_card_get_drvdata(card); 929 } 930 931 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 932 struct snd_ctl_elem_info *uinfo) 933 { 934 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 935 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 936 937 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 938 uinfo->count = sizeof(hdmi->connector->eld); 939 940 return 0; 941 } 942 943 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 944 struct snd_ctl_elem_value *ucontrol) 945 { 946 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 947 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 948 949 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld, 950 sizeof(hdmi->connector->eld)); 951 952 return 0; 953 } 954 955 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 956 { 957 .access = SNDRV_CTL_ELEM_ACCESS_READ | 958 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 959 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 960 .name = "ELD", 961 .info = vc4_hdmi_audio_eld_ctl_info, 962 .get = vc4_hdmi_audio_eld_ctl_get, 963 }, 964 }; 965 966 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 967 SND_SOC_DAPM_OUTPUT("TX"), 968 }; 969 970 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 971 { "TX", NULL, "Playback" }, 972 }; 973 974 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 975 .controls = vc4_hdmi_audio_controls, 976 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 977 .dapm_widgets = vc4_hdmi_audio_widgets, 978 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 979 .dapm_routes = vc4_hdmi_audio_routes, 980 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 981 .idle_bias_on = 1, 982 .use_pmdown_time = 1, 983 .endianness = 1, 984 .non_legacy_dai_naming = 1, 985 }; 986 987 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 988 .startup = vc4_hdmi_audio_startup, 989 .shutdown = vc4_hdmi_audio_shutdown, 990 .hw_params = vc4_hdmi_audio_hw_params, 991 .set_fmt = vc4_hdmi_audio_set_fmt, 992 .trigger = vc4_hdmi_audio_trigger, 993 }; 994 995 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 996 .name = "vc4-hdmi-hifi", 997 .playback = { 998 .stream_name = "Playback", 999 .channels_min = 2, 1000 .channels_max = 8, 1001 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1002 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1003 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1004 SNDRV_PCM_RATE_192000, 1005 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1006 }, 1007 }; 1008 1009 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1010 .name = "vc4-hdmi-cpu-dai-component", 1011 }; 1012 1013 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1014 { 1015 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 1016 1017 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL); 1018 1019 return 0; 1020 } 1021 1022 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1023 .name = "vc4-hdmi-cpu-dai", 1024 .probe = vc4_hdmi_audio_cpu_dai_probe, 1025 .playback = { 1026 .stream_name = "Playback", 1027 .channels_min = 1, 1028 .channels_max = 8, 1029 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1030 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1031 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1032 SNDRV_PCM_RATE_192000, 1033 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1034 }, 1035 .ops = &vc4_hdmi_audio_dai_ops, 1036 }; 1037 1038 static const struct snd_dmaengine_pcm_config pcm_conf = { 1039 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1040 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1041 }; 1042 1043 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi) 1044 { 1045 struct snd_soc_dai_link *dai_link = &hdmi->audio.link; 1046 struct snd_soc_card *card = &hdmi->audio.card; 1047 struct device *dev = &hdmi->pdev->dev; 1048 const __be32 *addr; 1049 int ret; 1050 1051 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1052 dev_warn(dev, 1053 "'dmas' DT property is missing, no HDMI audio\n"); 1054 return 0; 1055 } 1056 1057 /* 1058 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1059 * the bus address specified in the DT, because the physical address 1060 * (the one returned by platform_get_resource()) is not appropriate 1061 * for DMA transfers. 1062 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1063 */ 1064 addr = of_get_address(dev->of_node, 1, NULL, NULL); 1065 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA; 1066 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1067 hdmi->audio.dma_data.maxburst = 2; 1068 1069 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1070 if (ret) { 1071 dev_err(dev, "Could not register PCM component: %d\n", ret); 1072 return ret; 1073 } 1074 1075 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1076 &vc4_hdmi_audio_cpu_dai_drv, 1); 1077 if (ret) { 1078 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1079 return ret; 1080 } 1081 1082 /* register component and codec dai */ 1083 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1084 &vc4_hdmi_audio_codec_dai_drv, 1); 1085 if (ret) { 1086 dev_err(dev, "Could not register component: %d\n", ret); 1087 return ret; 1088 } 1089 1090 dai_link->cpus = &hdmi->audio.cpu; 1091 dai_link->codecs = &hdmi->audio.codec; 1092 1093 dai_link->num_cpus = 1; 1094 dai_link->num_codecs = 1; 1095 1096 dai_link->name = "MAI"; 1097 dai_link->stream_name = "MAI PCM"; 1098 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1099 dai_link->cpus->dai_name = dev_name(dev); 1100 dai_link->codecs->name = dev_name(dev); 1101 1102 card->dai_link = dai_link; 1103 card->num_links = 1; 1104 card->name = "vc4-hdmi"; 1105 card->dev = dev; 1106 1107 /* 1108 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1109 * stores a pointer to the snd card object in dev->driver_data. This 1110 * means we cannot use it for something else. The hdmi back-pointer is 1111 * now stored in card->drvdata and should be retrieved with 1112 * snd_soc_card_get_drvdata() if needed. 1113 */ 1114 snd_soc_card_set_drvdata(card, hdmi); 1115 ret = devm_snd_soc_register_card(dev, card); 1116 if (ret) 1117 dev_err(dev, "Could not register sound card: %d\n", ret); 1118 1119 return ret; 1120 1121 } 1122 1123 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1124 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1125 { 1126 struct vc4_dev *vc4 = priv; 1127 struct vc4_hdmi *hdmi = vc4->hdmi; 1128 1129 if (hdmi->cec_irq_was_rx) { 1130 if (hdmi->cec_rx_msg.len) 1131 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg); 1132 } else if (hdmi->cec_tx_ok) { 1133 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK, 1134 0, 0, 0, 0); 1135 } else { 1136 /* 1137 * This CEC implementation makes 1 retry, so if we 1138 * get a NACK, then that means it made 2 attempts. 1139 */ 1140 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK, 1141 0, 2, 0, 0); 1142 } 1143 return IRQ_HANDLED; 1144 } 1145 1146 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1) 1147 { 1148 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg; 1149 unsigned int i; 1150 1151 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1152 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1153 for (i = 0; i < msg->len; i += 4) { 1154 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i); 1155 1156 msg->msg[i] = val & 0xff; 1157 msg->msg[i + 1] = (val >> 8) & 0xff; 1158 msg->msg[i + 2] = (val >> 16) & 0xff; 1159 msg->msg[i + 3] = (val >> 24) & 0xff; 1160 } 1161 } 1162 1163 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1164 { 1165 struct vc4_dev *vc4 = priv; 1166 struct vc4_hdmi *hdmi = vc4->hdmi; 1167 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS); 1168 u32 cntrl1, cntrl5; 1169 1170 if (!(stat & VC4_HDMI_CPU_CEC)) 1171 return IRQ_NONE; 1172 hdmi->cec_rx_msg.len = 0; 1173 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1174 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1175 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1176 if (hdmi->cec_irq_was_rx) { 1177 vc4_cec_read_msg(vc4, cntrl1); 1178 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1179 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1180 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1181 } else { 1182 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1183 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1184 } 1185 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1186 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1187 1188 return IRQ_WAKE_THREAD; 1189 } 1190 1191 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1192 { 1193 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1194 /* clock period in microseconds */ 1195 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1196 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1197 1198 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1199 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1200 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1201 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1202 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1203 1204 if (enable) { 1205 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1206 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1207 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val); 1208 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2, 1209 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1210 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1211 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1212 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1213 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1214 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3, 1215 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1216 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1217 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1218 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1219 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4, 1220 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1221 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1222 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1223 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1224 1225 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1226 } else { 1227 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1228 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1229 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1230 } 1231 return 0; 1232 } 1233 1234 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1235 { 1236 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1237 1238 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, 1239 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1240 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1241 return 0; 1242 } 1243 1244 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1245 u32 signal_free_time, struct cec_msg *msg) 1246 { 1247 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1248 u32 val; 1249 unsigned int i; 1250 1251 for (i = 0; i < msg->len; i += 4) 1252 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i, 1253 (msg->msg[i]) | 1254 (msg->msg[i + 1] << 8) | 1255 (msg->msg[i + 2] << 16) | 1256 (msg->msg[i + 3] << 24)); 1257 1258 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1259 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1260 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1261 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1262 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1263 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1264 1265 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1266 return 0; 1267 } 1268 1269 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1270 .adap_enable = vc4_hdmi_cec_adap_enable, 1271 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1272 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1273 }; 1274 #endif 1275 1276 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1277 { 1278 struct platform_device *pdev = to_platform_device(dev); 1279 struct drm_device *drm = dev_get_drvdata(master); 1280 struct vc4_dev *vc4 = drm->dev_private; 1281 struct vc4_hdmi *hdmi; 1282 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 1283 struct device_node *ddc_node; 1284 u32 value; 1285 int ret; 1286 1287 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1288 if (!hdmi) 1289 return -ENOMEM; 1290 1291 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 1292 GFP_KERNEL); 1293 if (!vc4_hdmi_encoder) 1294 return -ENOMEM; 1295 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 1296 hdmi->encoder = &vc4_hdmi_encoder->base.base; 1297 1298 hdmi->pdev = pdev; 1299 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1300 if (IS_ERR(hdmi->hdmicore_regs)) 1301 return PTR_ERR(hdmi->hdmicore_regs); 1302 1303 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1304 if (IS_ERR(hdmi->hd_regs)) 1305 return PTR_ERR(hdmi->hd_regs); 1306 1307 hdmi->hdmi_regset.base = hdmi->hdmicore_regs; 1308 hdmi->hdmi_regset.regs = hdmi_regs; 1309 hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs); 1310 hdmi->hd_regset.base = hdmi->hd_regs; 1311 hdmi->hd_regset.regs = hd_regs; 1312 hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs); 1313 1314 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1315 if (IS_ERR(hdmi->pixel_clock)) { 1316 DRM_ERROR("Failed to get pixel clock\n"); 1317 return PTR_ERR(hdmi->pixel_clock); 1318 } 1319 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1320 if (IS_ERR(hdmi->hsm_clock)) { 1321 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1322 return PTR_ERR(hdmi->hsm_clock); 1323 } 1324 1325 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1326 if (!ddc_node) { 1327 DRM_ERROR("Failed to find ddc node in device tree\n"); 1328 return -ENODEV; 1329 } 1330 1331 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1332 of_node_put(ddc_node); 1333 if (!hdmi->ddc) { 1334 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1335 return -EPROBE_DEFER; 1336 } 1337 1338 /* This is the rate that is set by the firmware. The number 1339 * needs to be a bit higher than the pixel clock rate 1340 * (generally 148.5Mhz). 1341 */ 1342 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ); 1343 if (ret) { 1344 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1345 goto err_put_i2c; 1346 } 1347 1348 ret = clk_prepare_enable(hdmi->hsm_clock); 1349 if (ret) { 1350 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 1351 ret); 1352 goto err_put_i2c; 1353 } 1354 1355 /* Only use the GPIO HPD pin if present in the DT, otherwise 1356 * we'll use the HDMI core's register. 1357 */ 1358 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1359 enum of_gpio_flags hpd_gpio_flags; 1360 1361 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1362 "hpd-gpios", 0, 1363 &hpd_gpio_flags); 1364 if (hdmi->hpd_gpio < 0) { 1365 ret = hdmi->hpd_gpio; 1366 goto err_unprepare_hsm; 1367 } 1368 1369 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1370 } 1371 1372 vc4->hdmi = hdmi; 1373 1374 /* HDMI core must be enabled. */ 1375 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { 1376 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 1377 udelay(1); 1378 HD_WRITE(VC4_HD_M_CTL, 0); 1379 1380 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 1381 } 1382 pm_runtime_enable(dev); 1383 1384 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, 1385 DRM_MODE_ENCODER_TMDS, NULL); 1386 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 1387 1388 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); 1389 if (IS_ERR(hdmi->connector)) { 1390 ret = PTR_ERR(hdmi->connector); 1391 goto err_destroy_encoder; 1392 } 1393 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1394 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1395 vc4, "vc4", 1396 CEC_CAP_TRANSMIT | 1397 CEC_CAP_LOG_ADDRS | 1398 CEC_CAP_PASSTHROUGH | 1399 CEC_CAP_RC, 1); 1400 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 1401 if (ret < 0) 1402 goto err_destroy_conn; 1403 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff); 1404 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1405 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 1406 /* 1407 * Set the logical address to Unregistered and set the clock 1408 * divider: the hsm_clock rate and this divider setting will 1409 * give a 40 kHz CEC clock. 1410 */ 1411 value |= VC4_HDMI_CEC_ADDR_MASK | 1412 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT); 1413 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value); 1414 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 1415 vc4_cec_irq_handler, 1416 vc4_cec_irq_handler_thread, 0, 1417 "vc4 hdmi cec", vc4); 1418 if (ret) 1419 goto err_delete_cec_adap; 1420 ret = cec_register_adapter(hdmi->cec_adap, dev); 1421 if (ret < 0) 1422 goto err_delete_cec_adap; 1423 #endif 1424 1425 ret = vc4_hdmi_audio_init(hdmi); 1426 if (ret) 1427 goto err_destroy_encoder; 1428 1429 vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi); 1430 1431 return 0; 1432 1433 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1434 err_delete_cec_adap: 1435 cec_delete_adapter(hdmi->cec_adap); 1436 err_destroy_conn: 1437 vc4_hdmi_connector_destroy(hdmi->connector); 1438 #endif 1439 err_destroy_encoder: 1440 vc4_hdmi_encoder_destroy(hdmi->encoder); 1441 err_unprepare_hsm: 1442 clk_disable_unprepare(hdmi->hsm_clock); 1443 pm_runtime_disable(dev); 1444 err_put_i2c: 1445 put_device(&hdmi->ddc->dev); 1446 1447 return ret; 1448 } 1449 1450 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1451 void *data) 1452 { 1453 struct drm_device *drm = dev_get_drvdata(master); 1454 struct vc4_dev *vc4 = drm->dev_private; 1455 struct vc4_hdmi *hdmi = vc4->hdmi; 1456 1457 cec_unregister_adapter(hdmi->cec_adap); 1458 vc4_hdmi_connector_destroy(hdmi->connector); 1459 vc4_hdmi_encoder_destroy(hdmi->encoder); 1460 1461 clk_disable_unprepare(hdmi->hsm_clock); 1462 pm_runtime_disable(dev); 1463 1464 put_device(&hdmi->ddc->dev); 1465 1466 vc4->hdmi = NULL; 1467 } 1468 1469 static const struct component_ops vc4_hdmi_ops = { 1470 .bind = vc4_hdmi_bind, 1471 .unbind = vc4_hdmi_unbind, 1472 }; 1473 1474 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1475 { 1476 return component_add(&pdev->dev, &vc4_hdmi_ops); 1477 } 1478 1479 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1480 { 1481 component_del(&pdev->dev, &vc4_hdmi_ops); 1482 return 0; 1483 } 1484 1485 static const struct of_device_id vc4_hdmi_dt_match[] = { 1486 { .compatible = "brcm,bcm2835-hdmi" }, 1487 {} 1488 }; 1489 1490 struct platform_driver vc4_hdmi_driver = { 1491 .probe = vc4_hdmi_dev_probe, 1492 .remove = vc4_hdmi_dev_remove, 1493 .driver = { 1494 .name = "vc4_hdmi", 1495 .of_match_table = vc4_hdmi_dt_match, 1496 }, 1497 }; 1498