xref: /linux/drivers/gpu/drm/vc4/vc4_hdmi.c (revision 52a9dab6d892763b2a8334a568bd4e2c1a6fde66)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2015 Broadcom
4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5  * Copyright (C) 2013 Red Hat
6  * Author: Rob Clark <robdclark@gmail.com>
7  */
8 
9 /**
10  * DOC: VC4 Falcon HDMI module
11  *
12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
13  * the unit operates off of the HSM clock from CPRMAN.  It also
14  * internally uses the PLLH_PIX clock for the PHY.
15  *
16  * HDMI infoframes are kept within a small packet ram, where each
17  * packet can be individually enabled for including in a frame.
18  *
19  * HDMI audio is implemented entirely within the HDMI IP block.  A
20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
21  * and transfers them over an internal MAI (multi-channel audio
22  * interconnect) bus to the encoder side for insertion into the video
23  * blank regions.
24  *
25  * The driver's HDMI encoder does not yet support power management.
26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27  * continuously running, and only the HDMI logic and packet ram are
28  * powered off/on at disable/enable time.
29  *
30  * The driver does not yet support CEC control, though the HDMI
31  * encoder block has CEC support.
32  */
33 
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <drm/drm_simple_kms_helper.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <linux/clk.h>
40 #include <linux/component.h>
41 #include <linux/i2c.h>
42 #include <linux/of_address.h>
43 #include <linux/of_gpio.h>
44 #include <linux/of_platform.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/rational.h>
47 #include <linux/reset.h>
48 #include <sound/dmaengine_pcm.h>
49 #include <sound/hdmi-codec.h>
50 #include <sound/pcm_drm_eld.h>
51 #include <sound/pcm_params.h>
52 #include <sound/soc.h>
53 #include "media/cec.h"
54 #include "vc4_drv.h"
55 #include "vc4_hdmi.h"
56 #include "vc4_hdmi_regs.h"
57 #include "vc4_regs.h"
58 
59 #define VC5_HDMI_HORZA_HFP_SHIFT		16
60 #define VC5_HDMI_HORZA_HFP_MASK			VC4_MASK(28, 16)
61 #define VC5_HDMI_HORZA_VPOS			BIT(15)
62 #define VC5_HDMI_HORZA_HPOS			BIT(14)
63 #define VC5_HDMI_HORZA_HAP_SHIFT		0
64 #define VC5_HDMI_HORZA_HAP_MASK			VC4_MASK(13, 0)
65 
66 #define VC5_HDMI_HORZB_HBP_SHIFT		16
67 #define VC5_HDMI_HORZB_HBP_MASK			VC4_MASK(26, 16)
68 #define VC5_HDMI_HORZB_HSP_SHIFT		0
69 #define VC5_HDMI_HORZB_HSP_MASK			VC4_MASK(10, 0)
70 
71 #define VC5_HDMI_VERTA_VSP_SHIFT		24
72 #define VC5_HDMI_VERTA_VSP_MASK			VC4_MASK(28, 24)
73 #define VC5_HDMI_VERTA_VFP_SHIFT		16
74 #define VC5_HDMI_VERTA_VFP_MASK			VC4_MASK(22, 16)
75 #define VC5_HDMI_VERTA_VAL_SHIFT		0
76 #define VC5_HDMI_VERTA_VAL_MASK			VC4_MASK(12, 0)
77 
78 #define VC5_HDMI_VERTB_VSPO_SHIFT		16
79 #define VC5_HDMI_VERTB_VSPO_MASK		VC4_MASK(29, 16)
80 
81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE		BIT(0)
82 
83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT	8
84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK	VC4_MASK(10, 8)
85 
86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT		0
87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK		VC4_MASK(3, 0)
88 
89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE		BIT(31)
90 
91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT	8
92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK	VC4_MASK(15, 8)
93 
94 # define VC4_HD_M_SW_RST			BIT(2)
95 # define VC4_HD_M_ENABLE			BIT(0)
96 
97 #define HSM_MIN_CLOCK_FREQ	120000000
98 #define CEC_CLOCK_FREQ 40000
99 
100 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
101 
102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
103 {
104 	return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
105 }
106 
107 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
108 {
109 	struct drm_info_node *node = (struct drm_info_node *)m->private;
110 	struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
111 	struct drm_printer p = drm_seq_file_printer(m);
112 
113 	drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
114 	drm_print_regset32(&p, &vc4_hdmi->hd_regset);
115 
116 	return 0;
117 }
118 
119 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
120 {
121 	unsigned long flags;
122 
123 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
124 
125 	HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
126 	udelay(1);
127 	HDMI_WRITE(HDMI_M_CTL, 0);
128 
129 	HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
130 
131 	HDMI_WRITE(HDMI_SW_RESET_CONTROL,
132 		   VC4_HDMI_SW_RESET_HDMI |
133 		   VC4_HDMI_SW_RESET_FORMAT_DETECT);
134 
135 	HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
136 
137 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
138 }
139 
140 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
141 {
142 	unsigned long flags;
143 
144 	reset_control_reset(vc4_hdmi->reset);
145 
146 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
147 
148 	HDMI_WRITE(HDMI_DVP_CTL, 0);
149 
150 	HDMI_WRITE(HDMI_CLOCK_STOP,
151 		   HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
152 
153 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
154 }
155 
156 #ifdef CONFIG_DRM_VC4_HDMI_CEC
157 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
158 {
159 	unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
160 	unsigned long flags;
161 	u16 clk_cnt;
162 	u32 value;
163 
164 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
165 
166 	value = HDMI_READ(HDMI_CEC_CNTRL_1);
167 	value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
168 
169 	/*
170 	 * Set the clock divider: the hsm_clock rate and this divider
171 	 * setting will give a 40 kHz CEC clock.
172 	 */
173 	clk_cnt = cec_rate / CEC_CLOCK_FREQ;
174 	value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
175 	HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
176 
177 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
178 }
179 #else
180 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
181 #endif
182 
183 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
184 
185 static enum drm_connector_status
186 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
187 {
188 	struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
189 	bool connected = false;
190 
191 	mutex_lock(&vc4_hdmi->mutex);
192 
193 	WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
194 
195 	if (vc4_hdmi->hpd_gpio) {
196 		if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
197 			connected = true;
198 	} else {
199 		if (vc4_hdmi->variant->hp_detect &&
200 		    vc4_hdmi->variant->hp_detect(vc4_hdmi))
201 			connected = true;
202 	}
203 
204 	if (connected) {
205 		if (connector->status != connector_status_connected) {
206 			struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
207 
208 			if (edid) {
209 				cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
210 				vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
211 				kfree(edid);
212 			}
213 		}
214 
215 		vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
216 		pm_runtime_put(&vc4_hdmi->pdev->dev);
217 		mutex_unlock(&vc4_hdmi->mutex);
218 		return connector_status_connected;
219 	}
220 
221 	cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
222 	pm_runtime_put(&vc4_hdmi->pdev->dev);
223 	mutex_unlock(&vc4_hdmi->mutex);
224 	return connector_status_disconnected;
225 }
226 
227 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
228 {
229 	drm_connector_unregister(connector);
230 	drm_connector_cleanup(connector);
231 }
232 
233 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
234 {
235 	struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
236 	struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
237 	int ret = 0;
238 	struct edid *edid;
239 
240 	mutex_lock(&vc4_hdmi->mutex);
241 
242 	edid = drm_get_edid(connector, vc4_hdmi->ddc);
243 	cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
244 	if (!edid) {
245 		ret = -ENODEV;
246 		goto out;
247 	}
248 
249 	vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
250 
251 	drm_connector_update_edid_property(connector, edid);
252 	ret = drm_add_edid_modes(connector, edid);
253 	kfree(edid);
254 
255 	if (vc4_hdmi->disable_4kp60) {
256 		struct drm_device *drm = connector->dev;
257 		struct drm_display_mode *mode;
258 
259 		list_for_each_entry(mode, &connector->probed_modes, head) {
260 			if (vc4_hdmi_mode_needs_scrambling(mode)) {
261 				drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
262 				drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
263 			}
264 		}
265 	}
266 
267 out:
268 	mutex_unlock(&vc4_hdmi->mutex);
269 
270 	return ret;
271 }
272 
273 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
274 					   struct drm_atomic_state *state)
275 {
276 	struct drm_connector_state *old_state =
277 		drm_atomic_get_old_connector_state(state, connector);
278 	struct drm_connector_state *new_state =
279 		drm_atomic_get_new_connector_state(state, connector);
280 	struct drm_crtc *crtc = new_state->crtc;
281 
282 	if (!crtc)
283 		return 0;
284 
285 	if (old_state->colorspace != new_state->colorspace ||
286 	    !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
287 		struct drm_crtc_state *crtc_state;
288 
289 		crtc_state = drm_atomic_get_crtc_state(state, crtc);
290 		if (IS_ERR(crtc_state))
291 			return PTR_ERR(crtc_state);
292 
293 		crtc_state->mode_changed = true;
294 	}
295 
296 	return 0;
297 }
298 
299 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
300 {
301 	struct vc4_hdmi_connector_state *old_state =
302 		conn_state_to_vc4_hdmi_conn_state(connector->state);
303 	struct vc4_hdmi_connector_state *new_state =
304 		kzalloc(sizeof(*new_state), GFP_KERNEL);
305 
306 	if (connector->state)
307 		__drm_atomic_helper_connector_destroy_state(connector->state);
308 
309 	kfree(old_state);
310 	__drm_atomic_helper_connector_reset(connector, &new_state->base);
311 
312 	if (!new_state)
313 		return;
314 
315 	new_state->base.max_bpc = 8;
316 	new_state->base.max_requested_bpc = 8;
317 	drm_atomic_helper_connector_tv_reset(connector);
318 }
319 
320 static struct drm_connector_state *
321 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
322 {
323 	struct drm_connector_state *conn_state = connector->state;
324 	struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
325 	struct vc4_hdmi_connector_state *new_state;
326 
327 	new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
328 	if (!new_state)
329 		return NULL;
330 
331 	new_state->pixel_rate = vc4_state->pixel_rate;
332 	__drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
333 
334 	return &new_state->base;
335 }
336 
337 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
338 	.detect = vc4_hdmi_connector_detect,
339 	.fill_modes = drm_helper_probe_single_connector_modes,
340 	.destroy = vc4_hdmi_connector_destroy,
341 	.reset = vc4_hdmi_connector_reset,
342 	.atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
343 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
344 };
345 
346 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
347 	.get_modes = vc4_hdmi_connector_get_modes,
348 	.atomic_check = vc4_hdmi_connector_atomic_check,
349 };
350 
351 static int vc4_hdmi_connector_init(struct drm_device *dev,
352 				   struct vc4_hdmi *vc4_hdmi)
353 {
354 	struct drm_connector *connector = &vc4_hdmi->connector;
355 	struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
356 	int ret;
357 
358 	drm_connector_init_with_ddc(dev, connector,
359 				    &vc4_hdmi_connector_funcs,
360 				    DRM_MODE_CONNECTOR_HDMIA,
361 				    vc4_hdmi->ddc);
362 	drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
363 
364 	/*
365 	 * Some of the properties below require access to state, like bpc.
366 	 * Allocate some default initial connector state with our reset helper.
367 	 */
368 	if (connector->funcs->reset)
369 		connector->funcs->reset(connector);
370 
371 	/* Create and attach TV margin props to this connector. */
372 	ret = drm_mode_create_tv_margin_properties(dev);
373 	if (ret)
374 		return ret;
375 
376 	ret = drm_mode_create_hdmi_colorspace_property(connector);
377 	if (ret)
378 		return ret;
379 
380 	drm_connector_attach_colorspace_property(connector);
381 	drm_connector_attach_tv_margin_properties(connector);
382 	drm_connector_attach_max_bpc_property(connector, 8, 12);
383 
384 	connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
385 			     DRM_CONNECTOR_POLL_DISCONNECT);
386 
387 	connector->interlace_allowed = 1;
388 	connector->doublescan_allowed = 0;
389 
390 	if (vc4_hdmi->variant->supports_hdr)
391 		drm_connector_attach_hdr_output_metadata_property(connector);
392 
393 	drm_connector_attach_encoder(connector, encoder);
394 
395 	return 0;
396 }
397 
398 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
399 				enum hdmi_infoframe_type type,
400 				bool poll)
401 {
402 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
403 	u32 packet_id = type - 0x80;
404 	unsigned long flags;
405 
406 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
407 	HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
408 		   HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
409 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
410 
411 	if (!poll)
412 		return 0;
413 
414 	return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
415 			  BIT(packet_id)), 100);
416 }
417 
418 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
419 				     union hdmi_infoframe *frame)
420 {
421 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
422 	u32 packet_id = frame->any.type - 0x80;
423 	const struct vc4_hdmi_register *ram_packet_start =
424 		&vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
425 	u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
426 	void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
427 						       ram_packet_start->reg);
428 	uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
429 	unsigned long flags;
430 	ssize_t len, i;
431 	int ret;
432 
433 	WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
434 		    VC4_HDMI_RAM_PACKET_ENABLE),
435 		  "Packet RAM has to be on to store the packet.");
436 
437 	len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
438 	if (len < 0)
439 		return;
440 
441 	ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
442 	if (ret) {
443 		DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
444 		return;
445 	}
446 
447 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
448 
449 	for (i = 0; i < len; i += 7) {
450 		writel(buffer[i + 0] << 0 |
451 		       buffer[i + 1] << 8 |
452 		       buffer[i + 2] << 16,
453 		       base + packet_reg);
454 		packet_reg += 4;
455 
456 		writel(buffer[i + 3] << 0 |
457 		       buffer[i + 4] << 8 |
458 		       buffer[i + 5] << 16 |
459 		       buffer[i + 6] << 24,
460 		       base + packet_reg);
461 		packet_reg += 4;
462 	}
463 
464 	HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
465 		   HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
466 
467 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
468 
469 	ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
470 			BIT(packet_id)), 100);
471 	if (ret)
472 		DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
473 }
474 
475 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
476 {
477 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
478 	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
479 	struct drm_connector *connector = &vc4_hdmi->connector;
480 	struct drm_connector_state *cstate = connector->state;
481 	const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
482 	union hdmi_infoframe frame;
483 	int ret;
484 
485 	lockdep_assert_held(&vc4_hdmi->mutex);
486 
487 	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
488 						       connector, mode);
489 	if (ret < 0) {
490 		DRM_ERROR("couldn't fill AVI infoframe\n");
491 		return;
492 	}
493 
494 	drm_hdmi_avi_infoframe_quant_range(&frame.avi,
495 					   connector, mode,
496 					   vc4_encoder->limited_rgb_range ?
497 					   HDMI_QUANTIZATION_RANGE_LIMITED :
498 					   HDMI_QUANTIZATION_RANGE_FULL);
499 	drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
500 	drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
501 
502 	vc4_hdmi_write_infoframe(encoder, &frame);
503 }
504 
505 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
506 {
507 	union hdmi_infoframe frame;
508 	int ret;
509 
510 	ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
511 	if (ret < 0) {
512 		DRM_ERROR("couldn't fill SPD infoframe\n");
513 		return;
514 	}
515 
516 	frame.spd.sdi = HDMI_SPD_SDI_PC;
517 
518 	vc4_hdmi_write_infoframe(encoder, &frame);
519 }
520 
521 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
522 {
523 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
524 	struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
525 	union hdmi_infoframe frame;
526 
527 	memcpy(&frame.audio, audio, sizeof(*audio));
528 	vc4_hdmi_write_infoframe(encoder, &frame);
529 }
530 
531 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
532 {
533 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
534 	struct drm_connector *connector = &vc4_hdmi->connector;
535 	struct drm_connector_state *conn_state = connector->state;
536 	union hdmi_infoframe frame;
537 
538 	lockdep_assert_held(&vc4_hdmi->mutex);
539 
540 	if (!vc4_hdmi->variant->supports_hdr)
541 		return;
542 
543 	if (!conn_state->hdr_output_metadata)
544 		return;
545 
546 	if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
547 		return;
548 
549 	vc4_hdmi_write_infoframe(encoder, &frame);
550 }
551 
552 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
553 {
554 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
555 
556 	lockdep_assert_held(&vc4_hdmi->mutex);
557 
558 	vc4_hdmi_set_avi_infoframe(encoder);
559 	vc4_hdmi_set_spd_infoframe(encoder);
560 	/*
561 	 * If audio was streaming, then we need to reenabled the audio
562 	 * infoframe here during encoder_enable.
563 	 */
564 	if (vc4_hdmi->audio.streaming)
565 		vc4_hdmi_set_audio_infoframe(encoder);
566 
567 	vc4_hdmi_set_hdr_infoframe(encoder);
568 }
569 
570 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
571 					 struct drm_display_mode *mode)
572 {
573 	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
574 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
575 	struct drm_display_info *display = &vc4_hdmi->connector.display_info;
576 
577 	lockdep_assert_held(&vc4_hdmi->mutex);
578 
579 	if (!vc4_encoder->hdmi_monitor)
580 		return false;
581 
582 	if (!display->hdmi.scdc.supported ||
583 	    !display->hdmi.scdc.scrambling.supported)
584 		return false;
585 
586 	return true;
587 }
588 
589 #define SCRAMBLING_POLLING_DELAY_MS	1000
590 
591 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
592 {
593 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
594 	struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
595 	unsigned long flags;
596 
597 	lockdep_assert_held(&vc4_hdmi->mutex);
598 
599 	if (!vc4_hdmi_supports_scrambling(encoder, mode))
600 		return;
601 
602 	if (!vc4_hdmi_mode_needs_scrambling(mode))
603 		return;
604 
605 	drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
606 	drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
607 
608 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
609 	HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
610 		   VC5_HDMI_SCRAMBLER_CTL_ENABLE);
611 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
612 
613 	vc4_hdmi->scdc_enabled = true;
614 
615 	queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
616 			   msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
617 }
618 
619 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
620 {
621 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
622 	unsigned long flags;
623 
624 	lockdep_assert_held(&vc4_hdmi->mutex);
625 
626 	if (!vc4_hdmi->scdc_enabled)
627 		return;
628 
629 	vc4_hdmi->scdc_enabled = false;
630 
631 	if (delayed_work_pending(&vc4_hdmi->scrambling_work))
632 		cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
633 
634 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
635 	HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
636 		   ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
637 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
638 
639 	drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
640 	drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
641 }
642 
643 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
644 {
645 	struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
646 						 struct vc4_hdmi,
647 						 scrambling_work);
648 
649 	if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
650 		return;
651 
652 	drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
653 	drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
654 
655 	queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
656 			   msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
657 }
658 
659 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
660 					       struct drm_atomic_state *state)
661 {
662 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
663 	unsigned long flags;
664 
665 	mutex_lock(&vc4_hdmi->mutex);
666 
667 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
668 
669 	HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
670 
671 	HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
672 
673 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
674 
675 	mdelay(1);
676 
677 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
678 	HDMI_WRITE(HDMI_VID_CTL,
679 		   HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
680 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
681 
682 	vc4_hdmi_disable_scrambling(encoder);
683 
684 	mutex_unlock(&vc4_hdmi->mutex);
685 }
686 
687 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
688 						 struct drm_atomic_state *state)
689 {
690 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
691 	unsigned long flags;
692 	int ret;
693 
694 	mutex_lock(&vc4_hdmi->mutex);
695 
696 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
697 	HDMI_WRITE(HDMI_VID_CTL,
698 		   HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
699 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
700 
701 	if (vc4_hdmi->variant->phy_disable)
702 		vc4_hdmi->variant->phy_disable(vc4_hdmi);
703 
704 	clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
705 	clk_disable_unprepare(vc4_hdmi->pixel_clock);
706 
707 	ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
708 	if (ret < 0)
709 		DRM_ERROR("Failed to release power domain: %d\n", ret);
710 
711 	mutex_unlock(&vc4_hdmi->mutex);
712 }
713 
714 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
715 {
716 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
717 
718 	mutex_lock(&vc4_hdmi->mutex);
719 	vc4_hdmi->output_enabled = false;
720 	mutex_unlock(&vc4_hdmi->mutex);
721 }
722 
723 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
724 {
725 	unsigned long flags;
726 	u32 csc_ctl;
727 
728 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
729 
730 	csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
731 				VC4_HD_CSC_CTL_ORDER);
732 
733 	if (enable) {
734 		/* CEA VICs other than #1 requre limited range RGB
735 		 * output unless overridden by an AVI infoframe.
736 		 * Apply a colorspace conversion to squash 0-255 down
737 		 * to 16-235.  The matrix here is:
738 		 *
739 		 * [ 0      0      0.8594 16]
740 		 * [ 0      0.8594 0      16]
741 		 * [ 0.8594 0      0      16]
742 		 * [ 0      0      0       1]
743 		 */
744 		csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
745 		csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
746 		csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
747 					 VC4_HD_CSC_CTL_MODE);
748 
749 		HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
750 		HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
751 		HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
752 		HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
753 		HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
754 		HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
755 	}
756 
757 	/* The RGB order applies even when CSC is disabled. */
758 	HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
759 
760 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
761 }
762 
763 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
764 {
765 	unsigned long flags;
766 	u32 csc_ctl;
767 
768 	csc_ctl = 0x07;	/* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
769 
770 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
771 
772 	if (enable) {
773 		/* CEA VICs other than #1 requre limited range RGB
774 		 * output unless overridden by an AVI infoframe.
775 		 * Apply a colorspace conversion to squash 0-255 down
776 		 * to 16-235.  The matrix here is:
777 		 *
778 		 * [ 0.8594 0      0      16]
779 		 * [ 0      0.8594 0      16]
780 		 * [ 0      0      0.8594 16]
781 		 * [ 0      0      0       1]
782 		 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
783 		 */
784 		HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
785 		HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
786 		HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
787 		HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
788 		HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
789 		HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
790 	} else {
791 		/* Still use the matrix for full range, but make it unity.
792 		 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
793 		 */
794 		HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
795 		HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
796 		HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
797 		HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
798 		HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
799 		HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
800 	}
801 
802 	HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
803 
804 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
805 }
806 
807 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
808 				 struct drm_connector_state *state,
809 				 struct drm_display_mode *mode)
810 {
811 	bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
812 	bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
813 	bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
814 	u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
815 	u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
816 				   VC4_HDMI_VERTA_VSP) |
817 		     VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
818 				   VC4_HDMI_VERTA_VFP) |
819 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
820 	u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
821 		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
822 				   VC4_HDMI_VERTB_VBP));
823 	u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
824 			  VC4_SET_FIELD(mode->crtc_vtotal -
825 					mode->crtc_vsync_end -
826 					interlaced,
827 					VC4_HDMI_VERTB_VBP));
828 	unsigned long flags;
829 
830 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
831 
832 	HDMI_WRITE(HDMI_HORZA,
833 		   (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
834 		   (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
835 		   VC4_SET_FIELD(mode->hdisplay * pixel_rep,
836 				 VC4_HDMI_HORZA_HAP));
837 
838 	HDMI_WRITE(HDMI_HORZB,
839 		   VC4_SET_FIELD((mode->htotal -
840 				  mode->hsync_end) * pixel_rep,
841 				 VC4_HDMI_HORZB_HBP) |
842 		   VC4_SET_FIELD((mode->hsync_end -
843 				  mode->hsync_start) * pixel_rep,
844 				 VC4_HDMI_HORZB_HSP) |
845 		   VC4_SET_FIELD((mode->hsync_start -
846 				  mode->hdisplay) * pixel_rep,
847 				 VC4_HDMI_HORZB_HFP));
848 
849 	HDMI_WRITE(HDMI_VERTA0, verta);
850 	HDMI_WRITE(HDMI_VERTA1, verta);
851 
852 	HDMI_WRITE(HDMI_VERTB0, vertb_even);
853 	HDMI_WRITE(HDMI_VERTB1, vertb);
854 
855 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
856 }
857 
858 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
859 				 struct drm_connector_state *state,
860 				 struct drm_display_mode *mode)
861 {
862 	bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
863 	bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
864 	bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
865 	u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
866 	u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
867 				   VC5_HDMI_VERTA_VSP) |
868 		     VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
869 				   VC5_HDMI_VERTA_VFP) |
870 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
871 	u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
872 		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
873 				   VC4_HDMI_VERTB_VBP));
874 	u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
875 			  VC4_SET_FIELD(mode->crtc_vtotal -
876 					mode->crtc_vsync_end -
877 					interlaced,
878 					VC4_HDMI_VERTB_VBP));
879 	unsigned long flags;
880 	unsigned char gcp;
881 	bool gcp_en;
882 	u32 reg;
883 
884 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
885 
886 	HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
887 	HDMI_WRITE(HDMI_HORZA,
888 		   (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
889 		   (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
890 		   VC4_SET_FIELD(mode->hdisplay * pixel_rep,
891 				 VC5_HDMI_HORZA_HAP) |
892 		   VC4_SET_FIELD((mode->hsync_start -
893 				  mode->hdisplay) * pixel_rep,
894 				 VC5_HDMI_HORZA_HFP));
895 
896 	HDMI_WRITE(HDMI_HORZB,
897 		   VC4_SET_FIELD((mode->htotal -
898 				  mode->hsync_end) * pixel_rep,
899 				 VC5_HDMI_HORZB_HBP) |
900 		   VC4_SET_FIELD((mode->hsync_end -
901 				  mode->hsync_start) * pixel_rep,
902 				 VC5_HDMI_HORZB_HSP));
903 
904 	HDMI_WRITE(HDMI_VERTA0, verta);
905 	HDMI_WRITE(HDMI_VERTA1, verta);
906 
907 	HDMI_WRITE(HDMI_VERTB0, vertb_even);
908 	HDMI_WRITE(HDMI_VERTB1, vertb);
909 
910 	switch (state->max_bpc) {
911 	case 12:
912 		gcp = 6;
913 		gcp_en = true;
914 		break;
915 	case 10:
916 		gcp = 5;
917 		gcp_en = true;
918 		break;
919 	case 8:
920 	default:
921 		gcp = 4;
922 		gcp_en = false;
923 		break;
924 	}
925 
926 	reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
927 	reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
928 		 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
929 	reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
930 	       VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
931 	HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
932 
933 	reg = HDMI_READ(HDMI_GCP_WORD_1);
934 	reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
935 	reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
936 	HDMI_WRITE(HDMI_GCP_WORD_1, reg);
937 
938 	reg = HDMI_READ(HDMI_GCP_CONFIG);
939 	reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
940 	reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
941 	HDMI_WRITE(HDMI_GCP_CONFIG, reg);
942 
943 	HDMI_WRITE(HDMI_CLOCK_STOP, 0);
944 
945 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
946 }
947 
948 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
949 {
950 	unsigned long flags;
951 	u32 drift;
952 	int ret;
953 
954 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
955 
956 	drift = HDMI_READ(HDMI_FIFO_CTL);
957 	drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
958 
959 	HDMI_WRITE(HDMI_FIFO_CTL,
960 		   drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
961 	HDMI_WRITE(HDMI_FIFO_CTL,
962 		   drift | VC4_HDMI_FIFO_CTL_RECENTER);
963 
964 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
965 
966 	usleep_range(1000, 1100);
967 
968 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
969 
970 	HDMI_WRITE(HDMI_FIFO_CTL,
971 		   drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
972 	HDMI_WRITE(HDMI_FIFO_CTL,
973 		   drift | VC4_HDMI_FIFO_CTL_RECENTER);
974 
975 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
976 
977 	ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
978 		       VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
979 	WARN_ONCE(ret, "Timeout waiting for "
980 		  "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
981 }
982 
983 static struct drm_connector_state *
984 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
985 				     struct drm_atomic_state *state)
986 {
987 	struct drm_connector_state *conn_state;
988 	struct drm_connector *connector;
989 	unsigned int i;
990 
991 	for_each_new_connector_in_state(state, connector, conn_state, i) {
992 		if (conn_state->best_encoder == encoder)
993 			return conn_state;
994 	}
995 
996 	return NULL;
997 }
998 
999 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1000 						struct drm_atomic_state *state)
1001 {
1002 	struct drm_connector_state *conn_state =
1003 		vc4_hdmi_encoder_get_connector_state(encoder, state);
1004 	struct vc4_hdmi_connector_state *vc4_conn_state =
1005 		conn_state_to_vc4_hdmi_conn_state(conn_state);
1006 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1007 	struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1008 	unsigned long pixel_rate = vc4_conn_state->pixel_rate;
1009 	unsigned long bvb_rate, hsm_rate;
1010 	unsigned long flags;
1011 	int ret;
1012 
1013 	mutex_lock(&vc4_hdmi->mutex);
1014 
1015 	/*
1016 	 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1017 	 * be faster than pixel clock, infinitesimally faster, tested in
1018 	 * simulation. Otherwise, exact value is unimportant for HDMI
1019 	 * operation." This conflicts with bcm2835's vc4 documentation, which
1020 	 * states HSM's clock has to be at least 108% of the pixel clock.
1021 	 *
1022 	 * Real life tests reveal that vc4's firmware statement holds up, and
1023 	 * users are able to use pixel clocks closer to HSM's, namely for
1024 	 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1025 	 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1026 	 * 162MHz.
1027 	 *
1028 	 * Additionally, the AXI clock needs to be at least 25% of
1029 	 * pixel clock, but HSM ends up being the limiting factor.
1030 	 */
1031 	hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1032 	ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1033 	if (ret) {
1034 		DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1035 		goto out;
1036 	}
1037 
1038 	ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1039 	if (ret < 0) {
1040 		DRM_ERROR("Failed to retain power domain: %d\n", ret);
1041 		goto out;
1042 	}
1043 
1044 	ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
1045 	if (ret) {
1046 		DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1047 		goto err_put_runtime_pm;
1048 	}
1049 
1050 	ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1051 	if (ret) {
1052 		DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1053 		goto err_put_runtime_pm;
1054 	}
1055 
1056 
1057 	vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1058 
1059 	if (pixel_rate > 297000000)
1060 		bvb_rate = 300000000;
1061 	else if (pixel_rate > 148500000)
1062 		bvb_rate = 150000000;
1063 	else
1064 		bvb_rate = 75000000;
1065 
1066 	ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1067 	if (ret) {
1068 		DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1069 		goto err_disable_pixel_clock;
1070 	}
1071 
1072 	ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1073 	if (ret) {
1074 		DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1075 		goto err_disable_pixel_clock;
1076 	}
1077 
1078 	if (vc4_hdmi->variant->phy_init)
1079 		vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1080 
1081 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1082 
1083 	HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1084 		   HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1085 		   VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1086 		   VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1087 
1088 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1089 
1090 	if (vc4_hdmi->variant->set_timings)
1091 		vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1092 
1093 	mutex_unlock(&vc4_hdmi->mutex);
1094 
1095 	return;
1096 
1097 err_disable_pixel_clock:
1098 	clk_disable_unprepare(vc4_hdmi->pixel_clock);
1099 err_put_runtime_pm:
1100 	pm_runtime_put(&vc4_hdmi->pdev->dev);
1101 out:
1102 	mutex_unlock(&vc4_hdmi->mutex);
1103 	return;
1104 }
1105 
1106 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1107 					     struct drm_atomic_state *state)
1108 {
1109 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1110 	struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1111 	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1112 	unsigned long flags;
1113 
1114 	mutex_lock(&vc4_hdmi->mutex);
1115 
1116 	if (vc4_encoder->hdmi_monitor &&
1117 	    drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
1118 		if (vc4_hdmi->variant->csc_setup)
1119 			vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1120 
1121 		vc4_encoder->limited_rgb_range = true;
1122 	} else {
1123 		if (vc4_hdmi->variant->csc_setup)
1124 			vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1125 
1126 		vc4_encoder->limited_rgb_range = false;
1127 	}
1128 
1129 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1130 	HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1131 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1132 
1133 	mutex_unlock(&vc4_hdmi->mutex);
1134 }
1135 
1136 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1137 					      struct drm_atomic_state *state)
1138 {
1139 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1140 	struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1141 	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1142 	bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1143 	bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1144 	unsigned long flags;
1145 	int ret;
1146 
1147 	mutex_lock(&vc4_hdmi->mutex);
1148 
1149 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1150 
1151 	HDMI_WRITE(HDMI_VID_CTL,
1152 		   VC4_HD_VID_CTL_ENABLE |
1153 		   VC4_HD_VID_CTL_CLRRGB |
1154 		   VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1155 		   VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1156 		   (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1157 		   (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1158 
1159 	HDMI_WRITE(HDMI_VID_CTL,
1160 		   HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1161 
1162 	if (vc4_encoder->hdmi_monitor) {
1163 		HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1164 			   HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1165 			   VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1166 
1167 		spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1168 
1169 		ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1170 			       VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1171 		WARN_ONCE(ret, "Timeout waiting for "
1172 			  "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1173 	} else {
1174 		HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1175 			   HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1176 			   ~(VC4_HDMI_RAM_PACKET_ENABLE));
1177 		HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1178 			   HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1179 			   ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1180 
1181 		spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1182 
1183 		ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1184 				 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1185 		WARN_ONCE(ret, "Timeout waiting for "
1186 			  "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1187 	}
1188 
1189 	if (vc4_encoder->hdmi_monitor) {
1190 		spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1191 
1192 		WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1193 			  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1194 		HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1195 			   HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1196 			   VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1197 
1198 		HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1199 			   VC4_HDMI_RAM_PACKET_ENABLE);
1200 
1201 		spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1202 
1203 		vc4_hdmi_set_infoframes(encoder);
1204 	}
1205 
1206 	vc4_hdmi_recenter_fifo(vc4_hdmi);
1207 	vc4_hdmi_enable_scrambling(encoder);
1208 
1209 	mutex_unlock(&vc4_hdmi->mutex);
1210 }
1211 
1212 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1213 {
1214 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1215 
1216 	mutex_lock(&vc4_hdmi->mutex);
1217 	vc4_hdmi->output_enabled = true;
1218 	mutex_unlock(&vc4_hdmi->mutex);
1219 }
1220 
1221 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1222 					     struct drm_crtc_state *crtc_state,
1223 					     struct drm_connector_state *conn_state)
1224 {
1225 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1226 
1227 	mutex_lock(&vc4_hdmi->mutex);
1228 	memcpy(&vc4_hdmi->saved_adjusted_mode,
1229 	       &crtc_state->adjusted_mode,
1230 	       sizeof(vc4_hdmi->saved_adjusted_mode));
1231 	mutex_unlock(&vc4_hdmi->mutex);
1232 }
1233 
1234 #define WIFI_2_4GHz_CH1_MIN_FREQ	2400000000ULL
1235 #define WIFI_2_4GHz_CH1_MAX_FREQ	2422000000ULL
1236 
1237 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1238 					 struct drm_crtc_state *crtc_state,
1239 					 struct drm_connector_state *conn_state)
1240 {
1241 	struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1242 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1243 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1244 	unsigned long long pixel_rate = mode->clock * 1000;
1245 	unsigned long long tmds_rate;
1246 
1247 	if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1248 	    !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1249 	    ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1250 	     (mode->hsync_end % 2) || (mode->htotal % 2)))
1251 		return -EINVAL;
1252 
1253 	/*
1254 	 * The 1440p@60 pixel rate is in the same range than the first
1255 	 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1256 	 * bandwidth). Slightly lower the frequency to bring it out of
1257 	 * the WiFi range.
1258 	 */
1259 	tmds_rate = pixel_rate * 10;
1260 	if (vc4_hdmi->disable_wifi_frequencies &&
1261 	    (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1262 	     tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1263 		mode->clock = 238560;
1264 		pixel_rate = mode->clock * 1000;
1265 	}
1266 
1267 	if (conn_state->max_bpc == 12) {
1268 		pixel_rate = pixel_rate * 150;
1269 		do_div(pixel_rate, 100);
1270 	} else if (conn_state->max_bpc == 10) {
1271 		pixel_rate = pixel_rate * 125;
1272 		do_div(pixel_rate, 100);
1273 	}
1274 
1275 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1276 		pixel_rate = pixel_rate * 2;
1277 
1278 	if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1279 		return -EINVAL;
1280 
1281 	if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1282 		return -EINVAL;
1283 
1284 	vc4_state->pixel_rate = pixel_rate;
1285 
1286 	return 0;
1287 }
1288 
1289 static enum drm_mode_status
1290 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1291 			    const struct drm_display_mode *mode)
1292 {
1293 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1294 
1295 	if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1296 	    !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1297 	    ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1298 	     (mode->hsync_end % 2) || (mode->htotal % 2)))
1299 		return MODE_H_ILLEGAL;
1300 
1301 	if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1302 		return MODE_CLOCK_HIGH;
1303 
1304 	if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1305 		return MODE_CLOCK_HIGH;
1306 
1307 	return MODE_OK;
1308 }
1309 
1310 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1311 	.atomic_check = vc4_hdmi_encoder_atomic_check,
1312 	.atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1313 	.mode_valid = vc4_hdmi_encoder_mode_valid,
1314 	.disable = vc4_hdmi_encoder_disable,
1315 	.enable = vc4_hdmi_encoder_enable,
1316 };
1317 
1318 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1319 {
1320 	int i;
1321 	u32 channel_map = 0;
1322 
1323 	for (i = 0; i < 8; i++) {
1324 		if (channel_mask & BIT(i))
1325 			channel_map |= i << (3 * i);
1326 	}
1327 	return channel_map;
1328 }
1329 
1330 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1331 {
1332 	int i;
1333 	u32 channel_map = 0;
1334 
1335 	for (i = 0; i < 8; i++) {
1336 		if (channel_mask & BIT(i))
1337 			channel_map |= i << (4 * i);
1338 	}
1339 	return channel_map;
1340 }
1341 
1342 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1343 {
1344 	unsigned long flags;
1345 	u32 hotplug;
1346 
1347 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1348 	hotplug = HDMI_READ(HDMI_HOTPLUG);
1349 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1350 
1351 	return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1352 }
1353 
1354 /* HDMI audio codec callbacks */
1355 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1356 					 unsigned int samplerate)
1357 {
1358 	u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1359 	unsigned long flags;
1360 	unsigned long n, m;
1361 
1362 	rational_best_approximation(hsm_clock, samplerate,
1363 				    VC4_HD_MAI_SMP_N_MASK >>
1364 				    VC4_HD_MAI_SMP_N_SHIFT,
1365 				    (VC4_HD_MAI_SMP_M_MASK >>
1366 				     VC4_HD_MAI_SMP_M_SHIFT) + 1,
1367 				    &n, &m);
1368 
1369 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1370 	HDMI_WRITE(HDMI_MAI_SMP,
1371 		   VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1372 		   VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1373 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1374 }
1375 
1376 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1377 {
1378 	const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1379 	u32 n, cts;
1380 	u64 tmp;
1381 
1382 	lockdep_assert_held(&vc4_hdmi->mutex);
1383 	lockdep_assert_held(&vc4_hdmi->hw_lock);
1384 
1385 	n = 128 * samplerate / 1000;
1386 	tmp = (u64)(mode->clock * 1000) * n;
1387 	do_div(tmp, 128 * samplerate);
1388 	cts = tmp;
1389 
1390 	HDMI_WRITE(HDMI_CRP_CFG,
1391 		   VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1392 		   VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1393 
1394 	/*
1395 	 * We could get slightly more accurate clocks in some cases by
1396 	 * providing a CTS_1 value.  The two CTS values are alternated
1397 	 * between based on the period fields
1398 	 */
1399 	HDMI_WRITE(HDMI_CTS_0, cts);
1400 	HDMI_WRITE(HDMI_CTS_1, cts);
1401 }
1402 
1403 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1404 {
1405 	struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1406 
1407 	return snd_soc_card_get_drvdata(card);
1408 }
1409 
1410 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1411 {
1412 	lockdep_assert_held(&vc4_hdmi->mutex);
1413 
1414 	/*
1415 	 * If the controller is disabled, prevent any ALSA output.
1416 	 */
1417 	if (!vc4_hdmi->output_enabled)
1418 		return false;
1419 
1420 	/*
1421 	 * If the encoder is currently in DVI mode, treat the codec DAI
1422 	 * as missing.
1423 	 */
1424 	if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE))
1425 		return false;
1426 
1427 	return true;
1428 }
1429 
1430 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1431 {
1432 	struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1433 	unsigned long flags;
1434 
1435 	mutex_lock(&vc4_hdmi->mutex);
1436 
1437 	if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1438 		mutex_unlock(&vc4_hdmi->mutex);
1439 		return -ENODEV;
1440 	}
1441 
1442 	vc4_hdmi->audio.streaming = true;
1443 
1444 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1445 	HDMI_WRITE(HDMI_MAI_CTL,
1446 		   VC4_HD_MAI_CTL_RESET |
1447 		   VC4_HD_MAI_CTL_FLUSH |
1448 		   VC4_HD_MAI_CTL_DLATE |
1449 		   VC4_HD_MAI_CTL_ERRORE |
1450 		   VC4_HD_MAI_CTL_ERRORF);
1451 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1452 
1453 	if (vc4_hdmi->variant->phy_rng_enable)
1454 		vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1455 
1456 	mutex_unlock(&vc4_hdmi->mutex);
1457 
1458 	return 0;
1459 }
1460 
1461 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1462 {
1463 	struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1464 	struct device *dev = &vc4_hdmi->pdev->dev;
1465 	unsigned long flags;
1466 	int ret;
1467 
1468 	lockdep_assert_held(&vc4_hdmi->mutex);
1469 
1470 	vc4_hdmi->audio.streaming = false;
1471 	ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1472 	if (ret)
1473 		dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1474 
1475 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1476 
1477 	HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1478 	HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1479 	HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1480 
1481 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1482 }
1483 
1484 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1485 {
1486 	struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1487 	unsigned long flags;
1488 
1489 	mutex_lock(&vc4_hdmi->mutex);
1490 
1491 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1492 
1493 	HDMI_WRITE(HDMI_MAI_CTL,
1494 		   VC4_HD_MAI_CTL_DLATE |
1495 		   VC4_HD_MAI_CTL_ERRORE |
1496 		   VC4_HD_MAI_CTL_ERRORF);
1497 
1498 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1499 
1500 	if (vc4_hdmi->variant->phy_rng_disable)
1501 		vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1502 
1503 	vc4_hdmi->audio.streaming = false;
1504 	vc4_hdmi_audio_reset(vc4_hdmi);
1505 
1506 	mutex_unlock(&vc4_hdmi->mutex);
1507 }
1508 
1509 static int sample_rate_to_mai_fmt(int samplerate)
1510 {
1511 	switch (samplerate) {
1512 	case 8000:
1513 		return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1514 	case 11025:
1515 		return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1516 	case 12000:
1517 		return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1518 	case 16000:
1519 		return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1520 	case 22050:
1521 		return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1522 	case 24000:
1523 		return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1524 	case 32000:
1525 		return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1526 	case 44100:
1527 		return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1528 	case 48000:
1529 		return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1530 	case 64000:
1531 		return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1532 	case 88200:
1533 		return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1534 	case 96000:
1535 		return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1536 	case 128000:
1537 		return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1538 	case 176400:
1539 		return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1540 	case 192000:
1541 		return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1542 	default:
1543 		return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1544 	}
1545 }
1546 
1547 /* HDMI audio codec callbacks */
1548 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1549 				  struct hdmi_codec_daifmt *daifmt,
1550 				  struct hdmi_codec_params *params)
1551 {
1552 	struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1553 	struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1554 	unsigned int sample_rate = params->sample_rate;
1555 	unsigned int channels = params->channels;
1556 	unsigned long flags;
1557 	u32 audio_packet_config, channel_mask;
1558 	u32 channel_map;
1559 	u32 mai_audio_format;
1560 	u32 mai_sample_rate;
1561 
1562 	dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1563 		sample_rate, params->sample_width, channels);
1564 
1565 	mutex_lock(&vc4_hdmi->mutex);
1566 
1567 	if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1568 		mutex_unlock(&vc4_hdmi->mutex);
1569 		return -EINVAL;
1570 	}
1571 
1572 	vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1573 
1574 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1575 	HDMI_WRITE(HDMI_MAI_CTL,
1576 		   VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1577 		   VC4_HD_MAI_CTL_WHOLSMP |
1578 		   VC4_HD_MAI_CTL_CHALIGN |
1579 		   VC4_HD_MAI_CTL_ENABLE);
1580 
1581 	mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1582 	if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1583 	    params->channels == 8)
1584 		mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1585 	else
1586 		mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1587 	HDMI_WRITE(HDMI_MAI_FMT,
1588 		   VC4_SET_FIELD(mai_sample_rate,
1589 				 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1590 		   VC4_SET_FIELD(mai_audio_format,
1591 				 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1592 
1593 	/* The B frame identifier should match the value used by alsa-lib (8) */
1594 	audio_packet_config =
1595 		VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1596 		VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1597 		VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1598 
1599 	channel_mask = GENMASK(channels - 1, 0);
1600 	audio_packet_config |= VC4_SET_FIELD(channel_mask,
1601 					     VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1602 
1603 	/* Set the MAI threshold */
1604 	HDMI_WRITE(HDMI_MAI_THR,
1605 		   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1606 		   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1607 		   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1608 		   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1609 
1610 	HDMI_WRITE(HDMI_MAI_CONFIG,
1611 		   VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1612 		   VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1613 		   VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1614 
1615 	channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1616 	HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1617 	HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1618 
1619 	vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1620 
1621 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1622 
1623 	memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1624 	vc4_hdmi_set_audio_infoframe(encoder);
1625 
1626 	mutex_unlock(&vc4_hdmi->mutex);
1627 
1628 	return 0;
1629 }
1630 
1631 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1632 	.name = "vc4-hdmi-cpu-dai-component",
1633 };
1634 
1635 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1636 {
1637 	struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1638 
1639 	snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1640 
1641 	return 0;
1642 }
1643 
1644 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1645 	.name = "vc4-hdmi-cpu-dai",
1646 	.probe  = vc4_hdmi_audio_cpu_dai_probe,
1647 	.playback = {
1648 		.stream_name = "Playback",
1649 		.channels_min = 1,
1650 		.channels_max = 8,
1651 		.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1652 			 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1653 			 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1654 			 SNDRV_PCM_RATE_192000,
1655 		.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1656 	},
1657 };
1658 
1659 static const struct snd_dmaengine_pcm_config pcm_conf = {
1660 	.chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1661 	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1662 };
1663 
1664 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1665 				  uint8_t *buf, size_t len)
1666 {
1667 	struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1668 	struct drm_connector *connector = &vc4_hdmi->connector;
1669 
1670 	mutex_lock(&vc4_hdmi->mutex);
1671 	memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1672 	mutex_unlock(&vc4_hdmi->mutex);
1673 
1674 	return 0;
1675 }
1676 
1677 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1678 	.get_eld = vc4_hdmi_audio_get_eld,
1679 	.prepare = vc4_hdmi_audio_prepare,
1680 	.audio_shutdown = vc4_hdmi_audio_shutdown,
1681 	.audio_startup = vc4_hdmi_audio_startup,
1682 };
1683 
1684 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1685 	.ops = &vc4_hdmi_codec_ops,
1686 	.max_i2s_channels = 8,
1687 	.i2s = 1,
1688 };
1689 
1690 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1691 {
1692 	const struct vc4_hdmi_register *mai_data =
1693 		&vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1694 	struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1695 	struct snd_soc_card *card = &vc4_hdmi->audio.card;
1696 	struct device *dev = &vc4_hdmi->pdev->dev;
1697 	struct platform_device *codec_pdev;
1698 	const __be32 *addr;
1699 	int index;
1700 	int ret;
1701 
1702 	if (!of_find_property(dev->of_node, "dmas", NULL)) {
1703 		dev_warn(dev,
1704 			 "'dmas' DT property is missing, no HDMI audio\n");
1705 		return 0;
1706 	}
1707 
1708 	if (mai_data->reg != VC4_HD) {
1709 		WARN_ONCE(true, "MAI isn't in the HD block\n");
1710 		return -EINVAL;
1711 	}
1712 
1713 	/*
1714 	 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1715 	 * the bus address specified in the DT, because the physical address
1716 	 * (the one returned by platform_get_resource()) is not appropriate
1717 	 * for DMA transfers.
1718 	 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1719 	 */
1720 	index = of_property_match_string(dev->of_node, "reg-names", "hd");
1721 	/* Before BCM2711, we don't have a named register range */
1722 	if (index < 0)
1723 		index = 1;
1724 
1725 	addr = of_get_address(dev->of_node, index, NULL, NULL);
1726 
1727 	vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1728 	vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1729 	vc4_hdmi->audio.dma_data.maxburst = 2;
1730 
1731 	ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1732 	if (ret) {
1733 		dev_err(dev, "Could not register PCM component: %d\n", ret);
1734 		return ret;
1735 	}
1736 
1737 	ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1738 					      &vc4_hdmi_audio_cpu_dai_drv, 1);
1739 	if (ret) {
1740 		dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1741 		return ret;
1742 	}
1743 
1744 	codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1745 						   PLATFORM_DEVID_AUTO,
1746 						   &vc4_hdmi_codec_pdata,
1747 						   sizeof(vc4_hdmi_codec_pdata));
1748 	if (IS_ERR(codec_pdev)) {
1749 		dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1750 		return PTR_ERR(codec_pdev);
1751 	}
1752 
1753 	dai_link->cpus		= &vc4_hdmi->audio.cpu;
1754 	dai_link->codecs	= &vc4_hdmi->audio.codec;
1755 	dai_link->platforms	= &vc4_hdmi->audio.platform;
1756 
1757 	dai_link->num_cpus	= 1;
1758 	dai_link->num_codecs	= 1;
1759 	dai_link->num_platforms	= 1;
1760 
1761 	dai_link->name = "MAI";
1762 	dai_link->stream_name = "MAI PCM";
1763 	dai_link->codecs->dai_name = "i2s-hifi";
1764 	dai_link->cpus->dai_name = dev_name(dev);
1765 	dai_link->codecs->name = dev_name(&codec_pdev->dev);
1766 	dai_link->platforms->name = dev_name(dev);
1767 
1768 	card->dai_link = dai_link;
1769 	card->num_links = 1;
1770 	card->name = vc4_hdmi->variant->card_name;
1771 	card->driver_name = "vc4-hdmi";
1772 	card->dev = dev;
1773 	card->owner = THIS_MODULE;
1774 
1775 	/*
1776 	 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1777 	 * stores a pointer to the snd card object in dev->driver_data. This
1778 	 * means we cannot use it for something else. The hdmi back-pointer is
1779 	 * now stored in card->drvdata and should be retrieved with
1780 	 * snd_soc_card_get_drvdata() if needed.
1781 	 */
1782 	snd_soc_card_set_drvdata(card, vc4_hdmi);
1783 	ret = devm_snd_soc_register_card(dev, card);
1784 	if (ret)
1785 		dev_err_probe(dev, ret, "Could not register sound card\n");
1786 
1787 	return ret;
1788 
1789 }
1790 
1791 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1792 {
1793 	struct vc4_hdmi *vc4_hdmi = priv;
1794 	struct drm_connector *connector = &vc4_hdmi->connector;
1795 	struct drm_device *dev = connector->dev;
1796 
1797 	if (dev && dev->registered)
1798 		drm_connector_helper_hpd_irq_event(connector);
1799 
1800 	return IRQ_HANDLED;
1801 }
1802 
1803 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1804 {
1805 	struct drm_connector *connector = &vc4_hdmi->connector;
1806 	struct platform_device *pdev = vc4_hdmi->pdev;
1807 	int ret;
1808 
1809 	if (vc4_hdmi->variant->external_irq_controller) {
1810 		unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1811 		unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1812 
1813 		ret = request_threaded_irq(hpd_con,
1814 					   NULL,
1815 					   vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1816 					   "vc4 hdmi hpd connected", vc4_hdmi);
1817 		if (ret)
1818 			return ret;
1819 
1820 		ret = request_threaded_irq(hpd_rm,
1821 					   NULL,
1822 					   vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1823 					   "vc4 hdmi hpd disconnected", vc4_hdmi);
1824 		if (ret) {
1825 			free_irq(hpd_con, vc4_hdmi);
1826 			return ret;
1827 		}
1828 
1829 		connector->polled = DRM_CONNECTOR_POLL_HPD;
1830 	}
1831 
1832 	return 0;
1833 }
1834 
1835 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1836 {
1837 	struct platform_device *pdev = vc4_hdmi->pdev;
1838 
1839 	if (vc4_hdmi->variant->external_irq_controller) {
1840 		free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1841 		free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1842 	}
1843 }
1844 
1845 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1846 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1847 {
1848 	struct vc4_hdmi *vc4_hdmi = priv;
1849 
1850 	if (vc4_hdmi->cec_rx_msg.len)
1851 		cec_received_msg(vc4_hdmi->cec_adap,
1852 				 &vc4_hdmi->cec_rx_msg);
1853 
1854 	return IRQ_HANDLED;
1855 }
1856 
1857 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1858 {
1859 	struct vc4_hdmi *vc4_hdmi = priv;
1860 
1861 	if (vc4_hdmi->cec_tx_ok) {
1862 		cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1863 				  0, 0, 0, 0);
1864 	} else {
1865 		/*
1866 		 * This CEC implementation makes 1 retry, so if we
1867 		 * get a NACK, then that means it made 2 attempts.
1868 		 */
1869 		cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1870 				  0, 2, 0, 0);
1871 	}
1872 	return IRQ_HANDLED;
1873 }
1874 
1875 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1876 {
1877 	struct vc4_hdmi *vc4_hdmi = priv;
1878 	irqreturn_t ret;
1879 
1880 	if (vc4_hdmi->cec_irq_was_rx)
1881 		ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1882 	else
1883 		ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1884 
1885 	return ret;
1886 }
1887 
1888 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1889 {
1890 	struct drm_device *dev = vc4_hdmi->connector.dev;
1891 	struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1892 	unsigned int i;
1893 
1894 	lockdep_assert_held(&vc4_hdmi->hw_lock);
1895 
1896 	msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1897 					VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1898 
1899 	if (msg->len > 16) {
1900 		drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1901 		return;
1902 	}
1903 
1904 	for (i = 0; i < msg->len; i += 4) {
1905 		u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1906 
1907 		msg->msg[i] = val & 0xff;
1908 		msg->msg[i + 1] = (val >> 8) & 0xff;
1909 		msg->msg[i + 2] = (val >> 16) & 0xff;
1910 		msg->msg[i + 3] = (val >> 24) & 0xff;
1911 	}
1912 }
1913 
1914 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1915 {
1916 	u32 cntrl1;
1917 
1918 	lockdep_assert_held(&vc4_hdmi->hw_lock);
1919 
1920 	cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1921 	vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1922 	cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1923 	HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1924 
1925 	return IRQ_WAKE_THREAD;
1926 }
1927 
1928 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1929 {
1930 	struct vc4_hdmi *vc4_hdmi = priv;
1931 	irqreturn_t ret;
1932 
1933 	spin_lock(&vc4_hdmi->hw_lock);
1934 	ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1935 	spin_unlock(&vc4_hdmi->hw_lock);
1936 
1937 	return ret;
1938 }
1939 
1940 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1941 {
1942 	u32 cntrl1;
1943 
1944 	lockdep_assert_held(&vc4_hdmi->hw_lock);
1945 
1946 	vc4_hdmi->cec_rx_msg.len = 0;
1947 	cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1948 	vc4_cec_read_msg(vc4_hdmi, cntrl1);
1949 	cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1950 	HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1951 	cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1952 
1953 	HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1954 
1955 	return IRQ_WAKE_THREAD;
1956 }
1957 
1958 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1959 {
1960 	struct vc4_hdmi *vc4_hdmi = priv;
1961 	irqreturn_t ret;
1962 
1963 	spin_lock(&vc4_hdmi->hw_lock);
1964 	ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1965 	spin_unlock(&vc4_hdmi->hw_lock);
1966 
1967 	return ret;
1968 }
1969 
1970 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1971 {
1972 	struct vc4_hdmi *vc4_hdmi = priv;
1973 	u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1974 	irqreturn_t ret;
1975 	u32 cntrl5;
1976 
1977 	if (!(stat & VC4_HDMI_CPU_CEC))
1978 		return IRQ_NONE;
1979 
1980 	spin_lock(&vc4_hdmi->hw_lock);
1981 	cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1982 	vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1983 	if (vc4_hdmi->cec_irq_was_rx)
1984 		ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1985 	else
1986 		ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1987 
1988 	HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1989 	spin_unlock(&vc4_hdmi->hw_lock);
1990 
1991 	return ret;
1992 }
1993 
1994 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
1995 {
1996 	struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1997 	/* clock period in microseconds */
1998 	const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1999 	unsigned long flags;
2000 	u32 val;
2001 	int ret;
2002 
2003 	/*
2004 	 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2005 	 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2006 	 * .detect or .get_modes might call .adap_enable, which leads to this
2007 	 * function being called with that mutex held.
2008 	 *
2009 	 * Concurrency is not an issue for the moment since we don't share any
2010 	 * state with KMS, so we can ignore the lock for now, but we need to
2011 	 * keep it in mind if we were to change that assumption.
2012 	 */
2013 
2014 	ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2015 	if (ret)
2016 		return ret;
2017 
2018 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2019 
2020 	val = HDMI_READ(HDMI_CEC_CNTRL_5);
2021 	val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2022 		 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2023 		 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2024 	val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2025 	       ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2026 
2027 	HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2028 		   VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2029 	HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2030 	HDMI_WRITE(HDMI_CEC_CNTRL_2,
2031 		   ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2032 		   ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2033 		   ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2034 		   ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2035 		   ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2036 	HDMI_WRITE(HDMI_CEC_CNTRL_3,
2037 		   ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2038 		   ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2039 		   ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2040 		   ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2041 	HDMI_WRITE(HDMI_CEC_CNTRL_4,
2042 		   ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2043 		   ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2044 		   ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2045 		   ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2046 
2047 	if (!vc4_hdmi->variant->external_irq_controller)
2048 		HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2049 
2050 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2051 
2052 	return 0;
2053 }
2054 
2055 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2056 {
2057 	struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2058 	unsigned long flags;
2059 
2060 	/*
2061 	 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2062 	 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2063 	 * .detect or .get_modes might call .adap_enable, which leads to this
2064 	 * function being called with that mutex held.
2065 	 *
2066 	 * Concurrency is not an issue for the moment since we don't share any
2067 	 * state with KMS, so we can ignore the lock for now, but we need to
2068 	 * keep it in mind if we were to change that assumption.
2069 	 */
2070 
2071 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2072 
2073 	if (!vc4_hdmi->variant->external_irq_controller)
2074 		HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2075 
2076 	HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2077 		   VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2078 
2079 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2080 
2081 	pm_runtime_put(&vc4_hdmi->pdev->dev);
2082 
2083 	return 0;
2084 }
2085 
2086 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2087 {
2088 	if (enable)
2089 		return vc4_hdmi_cec_enable(adap);
2090 	else
2091 		return vc4_hdmi_cec_disable(adap);
2092 }
2093 
2094 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2095 {
2096 	struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2097 	unsigned long flags;
2098 
2099 	/*
2100 	 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2101 	 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2102 	 * .detect or .get_modes might call .adap_enable, which leads to this
2103 	 * function being called with that mutex held.
2104 	 *
2105 	 * Concurrency is not an issue for the moment since we don't share any
2106 	 * state with KMS, so we can ignore the lock for now, but we need to
2107 	 * keep it in mind if we were to change that assumption.
2108 	 */
2109 
2110 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2111 	HDMI_WRITE(HDMI_CEC_CNTRL_1,
2112 		   (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2113 		   (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2114 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2115 
2116 	return 0;
2117 }
2118 
2119 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2120 				      u32 signal_free_time, struct cec_msg *msg)
2121 {
2122 	struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2123 	struct drm_device *dev = vc4_hdmi->connector.dev;
2124 	unsigned long flags;
2125 	u32 val;
2126 	unsigned int i;
2127 
2128 	/*
2129 	 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2130 	 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2131 	 * .detect or .get_modes might call .adap_enable, which leads to this
2132 	 * function being called with that mutex held.
2133 	 *
2134 	 * Concurrency is not an issue for the moment since we don't share any
2135 	 * state with KMS, so we can ignore the lock for now, but we need to
2136 	 * keep it in mind if we were to change that assumption.
2137 	 */
2138 
2139 	if (msg->len > 16) {
2140 		drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2141 		return -ENOMEM;
2142 	}
2143 
2144 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2145 
2146 	for (i = 0; i < msg->len; i += 4)
2147 		HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2148 			   (msg->msg[i]) |
2149 			   (msg->msg[i + 1] << 8) |
2150 			   (msg->msg[i + 2] << 16) |
2151 			   (msg->msg[i + 3] << 24));
2152 
2153 	val = HDMI_READ(HDMI_CEC_CNTRL_1);
2154 	val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2155 	HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2156 	val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2157 	val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2158 	val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2159 
2160 	HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2161 
2162 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2163 
2164 	return 0;
2165 }
2166 
2167 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2168 	.adap_enable = vc4_hdmi_cec_adap_enable,
2169 	.adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2170 	.adap_transmit = vc4_hdmi_cec_adap_transmit,
2171 };
2172 
2173 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2174 {
2175 	struct cec_connector_info conn_info;
2176 	struct platform_device *pdev = vc4_hdmi->pdev;
2177 	struct device *dev = &pdev->dev;
2178 	unsigned long flags;
2179 	u32 value;
2180 	int ret;
2181 
2182 	if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2183 		dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2184 		return 0;
2185 	}
2186 
2187 	vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2188 						  vc4_hdmi, "vc4",
2189 						  CEC_CAP_DEFAULTS |
2190 						  CEC_CAP_CONNECTOR_INFO, 1);
2191 	ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2192 	if (ret < 0)
2193 		return ret;
2194 
2195 	cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2196 	cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2197 
2198 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2199 	value = HDMI_READ(HDMI_CEC_CNTRL_1);
2200 	/* Set the logical address to Unregistered */
2201 	value |= VC4_HDMI_CEC_ADDR_MASK;
2202 	HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
2203 	spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2204 
2205 	vc4_hdmi_cec_update_clk_div(vc4_hdmi);
2206 
2207 	if (vc4_hdmi->variant->external_irq_controller) {
2208 		ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
2209 					   vc4_cec_irq_handler_rx_bare,
2210 					   vc4_cec_irq_handler_rx_thread, 0,
2211 					   "vc4 hdmi cec rx", vc4_hdmi);
2212 		if (ret)
2213 			goto err_delete_cec_adap;
2214 
2215 		ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
2216 					   vc4_cec_irq_handler_tx_bare,
2217 					   vc4_cec_irq_handler_tx_thread, 0,
2218 					   "vc4 hdmi cec tx", vc4_hdmi);
2219 		if (ret)
2220 			goto err_remove_cec_rx_handler;
2221 	} else {
2222 		spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2223 		HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2224 		spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2225 
2226 		ret = request_threaded_irq(platform_get_irq(pdev, 0),
2227 					   vc4_cec_irq_handler,
2228 					   vc4_cec_irq_handler_thread, 0,
2229 					   "vc4 hdmi cec", vc4_hdmi);
2230 		if (ret)
2231 			goto err_delete_cec_adap;
2232 	}
2233 
2234 	ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2235 	if (ret < 0)
2236 		goto err_remove_handlers;
2237 
2238 	return 0;
2239 
2240 err_remove_handlers:
2241 	if (vc4_hdmi->variant->external_irq_controller)
2242 		free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2243 	else
2244 		free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2245 
2246 err_remove_cec_rx_handler:
2247 	if (vc4_hdmi->variant->external_irq_controller)
2248 		free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2249 
2250 err_delete_cec_adap:
2251 	cec_delete_adapter(vc4_hdmi->cec_adap);
2252 
2253 	return ret;
2254 }
2255 
2256 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
2257 {
2258 	struct platform_device *pdev = vc4_hdmi->pdev;
2259 
2260 	if (vc4_hdmi->variant->external_irq_controller) {
2261 		free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2262 		free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2263 	} else {
2264 		free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2265 	}
2266 
2267 	cec_unregister_adapter(vc4_hdmi->cec_adap);
2268 }
2269 #else
2270 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2271 {
2272 	return 0;
2273 }
2274 
2275 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
2276 
2277 #endif
2278 
2279 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
2280 				 struct debugfs_regset32 *regset,
2281 				 enum vc4_hdmi_regs reg)
2282 {
2283 	const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2284 	struct debugfs_reg32 *regs, *new_regs;
2285 	unsigned int count = 0;
2286 	unsigned int i;
2287 
2288 	regs = kcalloc(variant->num_registers, sizeof(*regs),
2289 		       GFP_KERNEL);
2290 	if (!regs)
2291 		return -ENOMEM;
2292 
2293 	for (i = 0; i < variant->num_registers; i++) {
2294 		const struct vc4_hdmi_register *field =	&variant->registers[i];
2295 
2296 		if (field->reg != reg)
2297 			continue;
2298 
2299 		regs[count].name = field->name;
2300 		regs[count].offset = field->offset;
2301 		count++;
2302 	}
2303 
2304 	new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2305 	if (!new_regs)
2306 		return -ENOMEM;
2307 
2308 	regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2309 	regset->regs = new_regs;
2310 	regset->nregs = count;
2311 
2312 	return 0;
2313 }
2314 
2315 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2316 {
2317 	struct platform_device *pdev = vc4_hdmi->pdev;
2318 	struct device *dev = &pdev->dev;
2319 	int ret;
2320 
2321 	vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2322 	if (IS_ERR(vc4_hdmi->hdmicore_regs))
2323 		return PTR_ERR(vc4_hdmi->hdmicore_regs);
2324 
2325 	vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2326 	if (IS_ERR(vc4_hdmi->hd_regs))
2327 		return PTR_ERR(vc4_hdmi->hd_regs);
2328 
2329 	ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2330 	if (ret)
2331 		return ret;
2332 
2333 	ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2334 	if (ret)
2335 		return ret;
2336 
2337 	vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2338 	if (IS_ERR(vc4_hdmi->pixel_clock)) {
2339 		ret = PTR_ERR(vc4_hdmi->pixel_clock);
2340 		if (ret != -EPROBE_DEFER)
2341 			DRM_ERROR("Failed to get pixel clock\n");
2342 		return ret;
2343 	}
2344 
2345 	vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2346 	if (IS_ERR(vc4_hdmi->hsm_clock)) {
2347 		DRM_ERROR("Failed to get HDMI state machine clock\n");
2348 		return PTR_ERR(vc4_hdmi->hsm_clock);
2349 	}
2350 	vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2351 	vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2352 
2353 	return 0;
2354 }
2355 
2356 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2357 {
2358 	struct platform_device *pdev = vc4_hdmi->pdev;
2359 	struct device *dev = &pdev->dev;
2360 	struct resource *res;
2361 
2362 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2363 	if (!res)
2364 		return -ENODEV;
2365 
2366 	vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2367 					       resource_size(res));
2368 	if (!vc4_hdmi->hdmicore_regs)
2369 		return -ENOMEM;
2370 
2371 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2372 	if (!res)
2373 		return -ENODEV;
2374 
2375 	vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2376 	if (!vc4_hdmi->hd_regs)
2377 		return -ENOMEM;
2378 
2379 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2380 	if (!res)
2381 		return -ENODEV;
2382 
2383 	vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2384 	if (!vc4_hdmi->cec_regs)
2385 		return -ENOMEM;
2386 
2387 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2388 	if (!res)
2389 		return -ENODEV;
2390 
2391 	vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2392 	if (!vc4_hdmi->csc_regs)
2393 		return -ENOMEM;
2394 
2395 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2396 	if (!res)
2397 		return -ENODEV;
2398 
2399 	vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2400 	if (!vc4_hdmi->dvp_regs)
2401 		return -ENOMEM;
2402 
2403 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2404 	if (!res)
2405 		return -ENODEV;
2406 
2407 	vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2408 	if (!vc4_hdmi->phy_regs)
2409 		return -ENOMEM;
2410 
2411 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2412 	if (!res)
2413 		return -ENODEV;
2414 
2415 	vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2416 	if (!vc4_hdmi->ram_regs)
2417 		return -ENOMEM;
2418 
2419 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2420 	if (!res)
2421 		return -ENODEV;
2422 
2423 	vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2424 	if (!vc4_hdmi->rm_regs)
2425 		return -ENOMEM;
2426 
2427 	vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2428 	if (IS_ERR(vc4_hdmi->hsm_clock)) {
2429 		DRM_ERROR("Failed to get HDMI state machine clock\n");
2430 		return PTR_ERR(vc4_hdmi->hsm_clock);
2431 	}
2432 
2433 	vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2434 	if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2435 		DRM_ERROR("Failed to get pixel bvb clock\n");
2436 		return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2437 	}
2438 
2439 	vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2440 	if (IS_ERR(vc4_hdmi->audio_clock)) {
2441 		DRM_ERROR("Failed to get audio clock\n");
2442 		return PTR_ERR(vc4_hdmi->audio_clock);
2443 	}
2444 
2445 	vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2446 	if (IS_ERR(vc4_hdmi->cec_clock)) {
2447 		DRM_ERROR("Failed to get CEC clock\n");
2448 		return PTR_ERR(vc4_hdmi->cec_clock);
2449 	}
2450 
2451 	vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2452 	if (IS_ERR(vc4_hdmi->reset)) {
2453 		DRM_ERROR("Failed to get HDMI reset line\n");
2454 		return PTR_ERR(vc4_hdmi->reset);
2455 	}
2456 
2457 	return 0;
2458 }
2459 
2460 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2461 {
2462 	struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2463 
2464 	clk_disable_unprepare(vc4_hdmi->hsm_clock);
2465 
2466 	return 0;
2467 }
2468 
2469 static int vc4_hdmi_runtime_resume(struct device *dev)
2470 {
2471 	struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2472 	int ret;
2473 
2474 	ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2475 	if (ret)
2476 		return ret;
2477 
2478 	return 0;
2479 }
2480 
2481 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2482 {
2483 	const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2484 	struct platform_device *pdev = to_platform_device(dev);
2485 	struct drm_device *drm = dev_get_drvdata(master);
2486 	struct vc4_hdmi *vc4_hdmi;
2487 	struct drm_encoder *encoder;
2488 	struct device_node *ddc_node;
2489 	int ret;
2490 
2491 	vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2492 	if (!vc4_hdmi)
2493 		return -ENOMEM;
2494 	mutex_init(&vc4_hdmi->mutex);
2495 	spin_lock_init(&vc4_hdmi->hw_lock);
2496 	INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2497 
2498 	dev_set_drvdata(dev, vc4_hdmi);
2499 	encoder = &vc4_hdmi->encoder.base.base;
2500 	vc4_hdmi->encoder.base.type = variant->encoder_type;
2501 	vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2502 	vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2503 	vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2504 	vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2505 	vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2506 	vc4_hdmi->pdev = pdev;
2507 	vc4_hdmi->variant = variant;
2508 
2509 	/*
2510 	 * Since we don't know the state of the controller and its
2511 	 * display (if any), let's assume it's always enabled.
2512 	 * vc4_hdmi_disable_scrambling() will thus run at boot, make
2513 	 * sure it's disabled, and avoid any inconsistency.
2514 	 */
2515 	if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
2516 		vc4_hdmi->scdc_enabled = true;
2517 
2518 	ret = variant->init_resources(vc4_hdmi);
2519 	if (ret)
2520 		return ret;
2521 
2522 	ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2523 	if (!ddc_node) {
2524 		DRM_ERROR("Failed to find ddc node in device tree\n");
2525 		return -ENODEV;
2526 	}
2527 
2528 	vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2529 	of_node_put(ddc_node);
2530 	if (!vc4_hdmi->ddc) {
2531 		DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2532 		return -EPROBE_DEFER;
2533 	}
2534 
2535 	/* Only use the GPIO HPD pin if present in the DT, otherwise
2536 	 * we'll use the HDMI core's register.
2537 	 */
2538 	vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2539 	if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2540 		ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2541 		goto err_put_ddc;
2542 	}
2543 
2544 	vc4_hdmi->disable_wifi_frequencies =
2545 		of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2546 
2547 	if (variant->max_pixel_clock == 600000000) {
2548 		struct vc4_dev *vc4 = to_vc4_dev(drm);
2549 		long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2550 
2551 		if (max_rate < 550000000)
2552 			vc4_hdmi->disable_4kp60 = true;
2553 	}
2554 
2555 	/*
2556 	 * If we boot without any cable connected to the HDMI connector,
2557 	 * the firmware will skip the HSM initialization and leave it
2558 	 * with a rate of 0, resulting in a bus lockup when we're
2559 	 * accessing the registers even if it's enabled.
2560 	 *
2561 	 * Let's put a sensible default at runtime_resume so that we
2562 	 * don't end up in this situation.
2563 	 */
2564 	ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2565 	if (ret)
2566 		goto err_put_ddc;
2567 
2568 	/*
2569 	 * We need to have the device powered up at this point to call
2570 	 * our reset hook and for the CEC init.
2571 	 */
2572 	ret = vc4_hdmi_runtime_resume(dev);
2573 	if (ret)
2574 		goto err_put_ddc;
2575 
2576 	pm_runtime_get_noresume(dev);
2577 	pm_runtime_set_active(dev);
2578 	pm_runtime_enable(dev);
2579 
2580 	if (vc4_hdmi->variant->reset)
2581 		vc4_hdmi->variant->reset(vc4_hdmi);
2582 
2583 	if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2584 	     of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2585 	    HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2586 		clk_prepare_enable(vc4_hdmi->pixel_clock);
2587 		clk_prepare_enable(vc4_hdmi->hsm_clock);
2588 		clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2589 	}
2590 
2591 	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2592 	drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2593 
2594 	ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2595 	if (ret)
2596 		goto err_destroy_encoder;
2597 
2598 	ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2599 	if (ret)
2600 		goto err_destroy_conn;
2601 
2602 	ret = vc4_hdmi_cec_init(vc4_hdmi);
2603 	if (ret)
2604 		goto err_free_hotplug;
2605 
2606 	ret = vc4_hdmi_audio_init(vc4_hdmi);
2607 	if (ret)
2608 		goto err_free_cec;
2609 
2610 	vc4_debugfs_add_file(drm, variant->debugfs_name,
2611 			     vc4_hdmi_debugfs_regs,
2612 			     vc4_hdmi);
2613 
2614 	pm_runtime_put_sync(dev);
2615 
2616 	return 0;
2617 
2618 err_free_cec:
2619 	vc4_hdmi_cec_exit(vc4_hdmi);
2620 err_free_hotplug:
2621 	vc4_hdmi_hotplug_exit(vc4_hdmi);
2622 err_destroy_conn:
2623 	vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2624 err_destroy_encoder:
2625 	drm_encoder_cleanup(encoder);
2626 	pm_runtime_put_sync(dev);
2627 	pm_runtime_disable(dev);
2628 err_put_ddc:
2629 	put_device(&vc4_hdmi->ddc->dev);
2630 
2631 	return ret;
2632 }
2633 
2634 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2635 			    void *data)
2636 {
2637 	struct vc4_hdmi *vc4_hdmi;
2638 
2639 	/*
2640 	 * ASoC makes it a bit hard to retrieve a pointer to the
2641 	 * vc4_hdmi structure. Registering the card will overwrite our
2642 	 * device drvdata with a pointer to the snd_soc_card structure,
2643 	 * which can then be used to retrieve whatever drvdata we want
2644 	 * to associate.
2645 	 *
2646 	 * However, that doesn't fly in the case where we wouldn't
2647 	 * register an ASoC card (because of an old DT that is missing
2648 	 * the dmas properties for example), then the card isn't
2649 	 * registered and the device drvdata wouldn't be set.
2650 	 *
2651 	 * We can deal with both cases by making sure a snd_soc_card
2652 	 * pointer and a vc4_hdmi structure are pointing to the same
2653 	 * memory address, so we can treat them indistinctly without any
2654 	 * issue.
2655 	 */
2656 	BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2657 	BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2658 	vc4_hdmi = dev_get_drvdata(dev);
2659 
2660 	kfree(vc4_hdmi->hdmi_regset.regs);
2661 	kfree(vc4_hdmi->hd_regset.regs);
2662 
2663 	vc4_hdmi_cec_exit(vc4_hdmi);
2664 	vc4_hdmi_hotplug_exit(vc4_hdmi);
2665 	vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2666 	drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2667 
2668 	pm_runtime_disable(dev);
2669 
2670 	put_device(&vc4_hdmi->ddc->dev);
2671 }
2672 
2673 static const struct component_ops vc4_hdmi_ops = {
2674 	.bind   = vc4_hdmi_bind,
2675 	.unbind = vc4_hdmi_unbind,
2676 };
2677 
2678 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2679 {
2680 	return component_add(&pdev->dev, &vc4_hdmi_ops);
2681 }
2682 
2683 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2684 {
2685 	component_del(&pdev->dev, &vc4_hdmi_ops);
2686 	return 0;
2687 }
2688 
2689 static const struct vc4_hdmi_variant bcm2835_variant = {
2690 	.encoder_type		= VC4_ENCODER_TYPE_HDMI0,
2691 	.debugfs_name		= "hdmi_regs",
2692 	.card_name		= "vc4-hdmi",
2693 	.max_pixel_clock	= 162000000,
2694 	.registers		= vc4_hdmi_fields,
2695 	.num_registers		= ARRAY_SIZE(vc4_hdmi_fields),
2696 
2697 	.init_resources		= vc4_hdmi_init_resources,
2698 	.csc_setup		= vc4_hdmi_csc_setup,
2699 	.reset			= vc4_hdmi_reset,
2700 	.set_timings		= vc4_hdmi_set_timings,
2701 	.phy_init		= vc4_hdmi_phy_init,
2702 	.phy_disable		= vc4_hdmi_phy_disable,
2703 	.phy_rng_enable		= vc4_hdmi_phy_rng_enable,
2704 	.phy_rng_disable	= vc4_hdmi_phy_rng_disable,
2705 	.channel_map		= vc4_hdmi_channel_map,
2706 	.supports_hdr		= false,
2707 };
2708 
2709 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2710 	.encoder_type		= VC4_ENCODER_TYPE_HDMI0,
2711 	.debugfs_name		= "hdmi0_regs",
2712 	.card_name		= "vc4-hdmi-0",
2713 	.max_pixel_clock	= 600000000,
2714 	.registers		= vc5_hdmi_hdmi0_fields,
2715 	.num_registers		= ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2716 	.phy_lane_mapping	= {
2717 		PHY_LANE_0,
2718 		PHY_LANE_1,
2719 		PHY_LANE_2,
2720 		PHY_LANE_CK,
2721 	},
2722 	.unsupported_odd_h_timings	= true,
2723 	.external_irq_controller	= true,
2724 
2725 	.init_resources		= vc5_hdmi_init_resources,
2726 	.csc_setup		= vc5_hdmi_csc_setup,
2727 	.reset			= vc5_hdmi_reset,
2728 	.set_timings		= vc5_hdmi_set_timings,
2729 	.phy_init		= vc5_hdmi_phy_init,
2730 	.phy_disable		= vc5_hdmi_phy_disable,
2731 	.phy_rng_enable		= vc5_hdmi_phy_rng_enable,
2732 	.phy_rng_disable	= vc5_hdmi_phy_rng_disable,
2733 	.channel_map		= vc5_hdmi_channel_map,
2734 	.supports_hdr		= true,
2735 	.hp_detect		= vc5_hdmi_hp_detect,
2736 };
2737 
2738 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2739 	.encoder_type		= VC4_ENCODER_TYPE_HDMI1,
2740 	.debugfs_name		= "hdmi1_regs",
2741 	.card_name		= "vc4-hdmi-1",
2742 	.max_pixel_clock	= HDMI_14_MAX_TMDS_CLK,
2743 	.registers		= vc5_hdmi_hdmi1_fields,
2744 	.num_registers		= ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2745 	.phy_lane_mapping	= {
2746 		PHY_LANE_1,
2747 		PHY_LANE_0,
2748 		PHY_LANE_CK,
2749 		PHY_LANE_2,
2750 	},
2751 	.unsupported_odd_h_timings	= true,
2752 	.external_irq_controller	= true,
2753 
2754 	.init_resources		= vc5_hdmi_init_resources,
2755 	.csc_setup		= vc5_hdmi_csc_setup,
2756 	.reset			= vc5_hdmi_reset,
2757 	.set_timings		= vc5_hdmi_set_timings,
2758 	.phy_init		= vc5_hdmi_phy_init,
2759 	.phy_disable		= vc5_hdmi_phy_disable,
2760 	.phy_rng_enable		= vc5_hdmi_phy_rng_enable,
2761 	.phy_rng_disable	= vc5_hdmi_phy_rng_disable,
2762 	.channel_map		= vc5_hdmi_channel_map,
2763 	.supports_hdr		= true,
2764 	.hp_detect		= vc5_hdmi_hp_detect,
2765 };
2766 
2767 static const struct of_device_id vc4_hdmi_dt_match[] = {
2768 	{ .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2769 	{ .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2770 	{ .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2771 	{}
2772 };
2773 
2774 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2775 	SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2776 			   vc4_hdmi_runtime_resume,
2777 			   NULL)
2778 };
2779 
2780 struct platform_driver vc4_hdmi_driver = {
2781 	.probe = vc4_hdmi_dev_probe,
2782 	.remove = vc4_hdmi_dev_remove,
2783 	.driver = {
2784 		.name = "vc4_hdmi",
2785 		.of_match_table = vc4_hdmi_dt_match,
2786 		.pm = &vc4_hdmi_pm_ops,
2787 	},
2788 };
2789