1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 #ifndef _VC4_DRV_H_ 6 #define _VC4_DRV_H_ 7 8 #include <linux/delay.h> 9 #include <linux/of.h> 10 #include <linux/refcount.h> 11 #include <linux/uaccess.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_debugfs.h> 15 #include <drm/drm_device.h> 16 #include <drm/drm_encoder.h> 17 #include <drm/drm_gem_cma_helper.h> 18 #include <drm/drm_managed.h> 19 #include <drm/drm_mm.h> 20 #include <drm/drm_modeset_lock.h> 21 22 #include "uapi/drm/vc4_drm.h" 23 24 struct drm_device; 25 struct drm_gem_object; 26 27 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to 28 * this. 29 */ 30 enum vc4_kernel_bo_type { 31 /* Any kernel allocation (gem_create_object hook) before it 32 * gets another type set. 33 */ 34 VC4_BO_TYPE_KERNEL, 35 VC4_BO_TYPE_V3D, 36 VC4_BO_TYPE_V3D_SHADER, 37 VC4_BO_TYPE_DUMB, 38 VC4_BO_TYPE_BIN, 39 VC4_BO_TYPE_RCL, 40 VC4_BO_TYPE_BCL, 41 VC4_BO_TYPE_KERNEL_CACHE, 42 VC4_BO_TYPE_COUNT 43 }; 44 45 /* Performance monitor object. The perform lifetime is controlled by userspace 46 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 47 * request, and when this is the case, HW perf counters will be activated just 48 * before the submit_cl is submitted to the GPU and disabled when the job is 49 * done. This way, only events related to a specific job will be counted. 50 */ 51 struct vc4_perfmon { 52 struct vc4_dev *dev; 53 54 /* Tracks the number of users of the perfmon, when this counter reaches 55 * zero the perfmon is destroyed. 56 */ 57 refcount_t refcnt; 58 59 /* Number of counters activated in this perfmon instance 60 * (should be less than DRM_VC4_MAX_PERF_COUNTERS). 61 */ 62 u8 ncounters; 63 64 /* Events counted by the HW perf counters. */ 65 u8 events[DRM_VC4_MAX_PERF_COUNTERS]; 66 67 /* Storage for counter values. Counters are incremented by the HW 68 * perf counter values every time the perfmon is attached to a GPU job. 69 * This way, perfmon users don't have to retrieve the results after 70 * each job if they want to track events covering several submissions. 71 * Note that counter values can't be reset, but you can fake a reset by 72 * destroying the perfmon and creating a new one. 73 */ 74 u64 counters[]; 75 }; 76 77 struct vc4_dev { 78 struct drm_device base; 79 80 bool is_vc5; 81 82 unsigned int irq; 83 84 struct vc4_hvs *hvs; 85 struct vc4_v3d *v3d; 86 struct vc4_dpi *dpi; 87 struct vc4_vec *vec; 88 struct vc4_txp *txp; 89 90 struct vc4_hang_state *hang_state; 91 92 /* The kernel-space BO cache. Tracks buffers that have been 93 * unreferenced by all other users (refcounts of 0!) but not 94 * yet freed, so we can do cheap allocations. 95 */ 96 struct vc4_bo_cache { 97 /* Array of list heads for entries in the BO cache, 98 * based on number of pages, so we can do O(1) lookups 99 * in the cache when allocating. 100 */ 101 struct list_head *size_list; 102 uint32_t size_list_size; 103 104 /* List of all BOs in the cache, ordered by age, so we 105 * can do O(1) lookups when trying to free old 106 * buffers. 107 */ 108 struct list_head time_list; 109 struct work_struct time_work; 110 struct timer_list time_timer; 111 } bo_cache; 112 113 u32 num_labels; 114 struct vc4_label { 115 const char *name; 116 u32 num_allocated; 117 u32 size_allocated; 118 } *bo_labels; 119 120 /* Protects bo_cache and bo_labels. */ 121 struct mutex bo_lock; 122 123 /* Purgeable BO pool. All BOs in this pool can have their memory 124 * reclaimed if the driver is unable to allocate new BOs. We also 125 * keep stats related to the purge mechanism here. 126 */ 127 struct { 128 struct list_head list; 129 unsigned int num; 130 size_t size; 131 unsigned int purged_num; 132 size_t purged_size; 133 struct mutex lock; 134 } purgeable; 135 136 uint64_t dma_fence_context; 137 138 /* Sequence number for the last job queued in bin_job_list. 139 * Starts at 0 (no jobs emitted). 140 */ 141 uint64_t emit_seqno; 142 143 /* Sequence number for the last completed job on the GPU. 144 * Starts at 0 (no jobs completed). 145 */ 146 uint64_t finished_seqno; 147 148 /* List of all struct vc4_exec_info for jobs to be executed in 149 * the binner. The first job in the list is the one currently 150 * programmed into ct0ca for execution. 151 */ 152 struct list_head bin_job_list; 153 154 /* List of all struct vc4_exec_info for jobs that have 155 * completed binning and are ready for rendering. The first 156 * job in the list is the one currently programmed into ct1ca 157 * for execution. 158 */ 159 struct list_head render_job_list; 160 161 /* List of the finished vc4_exec_infos waiting to be freed by 162 * job_done_work. 163 */ 164 struct list_head job_done_list; 165 /* Spinlock used to synchronize the job_list and seqno 166 * accesses between the IRQ handler and GEM ioctls. 167 */ 168 spinlock_t job_lock; 169 wait_queue_head_t job_wait_queue; 170 struct work_struct job_done_work; 171 172 /* Used to track the active perfmon if any. Access to this field is 173 * protected by job_lock. 174 */ 175 struct vc4_perfmon *active_perfmon; 176 177 /* List of struct vc4_seqno_cb for callbacks to be made from a 178 * workqueue when the given seqno is passed. 179 */ 180 struct list_head seqno_cb_list; 181 182 /* The memory used for storing binner tile alloc, tile state, 183 * and overflow memory allocations. This is freed when V3D 184 * powers down. 185 */ 186 struct vc4_bo *bin_bo; 187 188 /* Size of blocks allocated within bin_bo. */ 189 uint32_t bin_alloc_size; 190 191 /* Bitmask of the bin_alloc_size chunks in bin_bo that are 192 * used. 193 */ 194 uint32_t bin_alloc_used; 195 196 /* Bitmask of the current bin_alloc used for overflow memory. */ 197 uint32_t bin_alloc_overflow; 198 199 /* Incremented when an underrun error happened after an atomic commit. 200 * This is particularly useful to detect when a specific modeset is too 201 * demanding in term of memory or HVS bandwidth which is hard to guess 202 * at atomic check time. 203 */ 204 atomic_t underrun; 205 206 struct work_struct overflow_mem_work; 207 208 int power_refcount; 209 210 /* Set to true when the load tracker is active. */ 211 bool load_tracker_enabled; 212 213 /* Mutex controlling the power refcount. */ 214 struct mutex power_lock; 215 216 struct { 217 struct timer_list timer; 218 struct work_struct reset_work; 219 } hangcheck; 220 221 struct drm_modeset_lock ctm_state_lock; 222 struct drm_private_obj ctm_manager; 223 struct drm_private_obj hvs_channels; 224 struct drm_private_obj load_tracker; 225 226 /* List of vc4_debugfs_info_entry for adding to debugfs once 227 * the minor is available (after drm_dev_register()). 228 */ 229 struct list_head debugfs_list; 230 231 /* Mutex for binner bo allocation. */ 232 struct mutex bin_bo_lock; 233 /* Reference count for our binner bo. */ 234 struct kref bin_bo_kref; 235 }; 236 237 static inline struct vc4_dev * 238 to_vc4_dev(struct drm_device *dev) 239 { 240 return container_of(dev, struct vc4_dev, base); 241 } 242 243 struct vc4_bo { 244 struct drm_gem_cma_object base; 245 246 /* seqno of the last job to render using this BO. */ 247 uint64_t seqno; 248 249 /* seqno of the last job to use the RCL to write to this BO. 250 * 251 * Note that this doesn't include binner overflow memory 252 * writes. 253 */ 254 uint64_t write_seqno; 255 256 bool t_format; 257 258 /* List entry for the BO's position in either 259 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 260 */ 261 struct list_head unref_head; 262 263 /* Time in jiffies when the BO was put in vc4->bo_cache. */ 264 unsigned long free_time; 265 266 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 267 struct list_head size_head; 268 269 /* Struct for shader validation state, if created by 270 * DRM_IOCTL_VC4_CREATE_SHADER_BO. 271 */ 272 struct vc4_validated_shader_info *validated_shader; 273 274 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i 275 * for user-allocated labels. 276 */ 277 int label; 278 279 /* Count the number of active users. This is needed to determine 280 * whether we can move the BO to the purgeable list or not (when the BO 281 * is used by the GPU or the display engine we can't purge it). 282 */ 283 refcount_t usecnt; 284 285 /* Store purgeable/purged state here */ 286 u32 madv; 287 struct mutex madv_lock; 288 }; 289 290 static inline struct vc4_bo * 291 to_vc4_bo(struct drm_gem_object *bo) 292 { 293 return container_of(to_drm_gem_cma_obj(bo), struct vc4_bo, base); 294 } 295 296 struct vc4_fence { 297 struct dma_fence base; 298 struct drm_device *dev; 299 /* vc4 seqno for signaled() test */ 300 uint64_t seqno; 301 }; 302 303 static inline struct vc4_fence * 304 to_vc4_fence(struct dma_fence *fence) 305 { 306 return container_of(fence, struct vc4_fence, base); 307 } 308 309 struct vc4_seqno_cb { 310 struct work_struct work; 311 uint64_t seqno; 312 void (*func)(struct vc4_seqno_cb *cb); 313 }; 314 315 struct vc4_v3d { 316 struct vc4_dev *vc4; 317 struct platform_device *pdev; 318 void __iomem *regs; 319 struct clk *clk; 320 struct debugfs_regset32 regset; 321 }; 322 323 struct vc4_hvs { 324 struct vc4_dev *vc4; 325 struct platform_device *pdev; 326 void __iomem *regs; 327 u32 __iomem *dlist; 328 329 struct clk *core_clk; 330 331 /* Memory manager for CRTCs to allocate space in the display 332 * list. Units are dwords. 333 */ 334 struct drm_mm dlist_mm; 335 /* Memory manager for the LBM memory used by HVS scaling. */ 336 struct drm_mm lbm_mm; 337 spinlock_t mm_lock; 338 339 struct drm_mm_node mitchell_netravali_filter; 340 341 struct debugfs_regset32 regset; 342 }; 343 344 struct vc4_plane { 345 struct drm_plane base; 346 }; 347 348 static inline struct vc4_plane * 349 to_vc4_plane(struct drm_plane *plane) 350 { 351 return container_of(plane, struct vc4_plane, base); 352 } 353 354 enum vc4_scaling_mode { 355 VC4_SCALING_NONE, 356 VC4_SCALING_TPZ, 357 VC4_SCALING_PPF, 358 }; 359 360 struct vc4_plane_state { 361 struct drm_plane_state base; 362 /* System memory copy of the display list for this element, computed 363 * at atomic_check time. 364 */ 365 u32 *dlist; 366 u32 dlist_size; /* Number of dwords allocated for the display list */ 367 u32 dlist_count; /* Number of used dwords in the display list. */ 368 369 /* Offset in the dlist to various words, for pageflip or 370 * cursor updates. 371 */ 372 u32 pos0_offset; 373 u32 pos2_offset; 374 u32 ptr0_offset; 375 u32 lbm_offset; 376 377 /* Offset where the plane's dlist was last stored in the 378 * hardware at vc4_crtc_atomic_flush() time. 379 */ 380 u32 __iomem *hw_dlist; 381 382 /* Clipped coordinates of the plane on the display. */ 383 int crtc_x, crtc_y, crtc_w, crtc_h; 384 /* Clipped area being scanned from in the FB. */ 385 u32 src_x, src_y; 386 387 u32 src_w[2], src_h[2]; 388 389 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */ 390 enum vc4_scaling_mode x_scaling[2], y_scaling[2]; 391 bool is_unity; 392 bool is_yuv; 393 394 /* Offset to start scanning out from the start of the plane's 395 * BO. 396 */ 397 u32 offsets[3]; 398 399 /* Our allocation in LBM for temporary storage during scaling. */ 400 struct drm_mm_node lbm; 401 402 /* Set when the plane has per-pixel alpha content or does not cover 403 * the entire screen. This is a hint to the CRTC that it might need 404 * to enable background color fill. 405 */ 406 bool needs_bg_fill; 407 408 /* Mark the dlist as initialized. Useful to avoid initializing it twice 409 * when async update is not possible. 410 */ 411 bool dlist_initialized; 412 413 /* Load of this plane on the HVS block. The load is expressed in HVS 414 * cycles/sec. 415 */ 416 u64 hvs_load; 417 418 /* Memory bandwidth needed for this plane. This is expressed in 419 * bytes/sec. 420 */ 421 u64 membus_load; 422 }; 423 424 static inline struct vc4_plane_state * 425 to_vc4_plane_state(struct drm_plane_state *state) 426 { 427 return container_of(state, struct vc4_plane_state, base); 428 } 429 430 enum vc4_encoder_type { 431 VC4_ENCODER_TYPE_NONE, 432 VC4_ENCODER_TYPE_HDMI0, 433 VC4_ENCODER_TYPE_HDMI1, 434 VC4_ENCODER_TYPE_VEC, 435 VC4_ENCODER_TYPE_DSI0, 436 VC4_ENCODER_TYPE_DSI1, 437 VC4_ENCODER_TYPE_SMI, 438 VC4_ENCODER_TYPE_DPI, 439 }; 440 441 struct vc4_encoder { 442 struct drm_encoder base; 443 enum vc4_encoder_type type; 444 u32 clock_select; 445 446 void (*pre_crtc_configure)(struct drm_encoder *encoder, struct drm_atomic_state *state); 447 void (*pre_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state); 448 void (*post_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state); 449 450 void (*post_crtc_disable)(struct drm_encoder *encoder, struct drm_atomic_state *state); 451 void (*post_crtc_powerdown)(struct drm_encoder *encoder, struct drm_atomic_state *state); 452 }; 453 454 static inline struct vc4_encoder * 455 to_vc4_encoder(struct drm_encoder *encoder) 456 { 457 return container_of(encoder, struct vc4_encoder, base); 458 } 459 460 struct vc4_crtc_data { 461 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */ 462 unsigned int hvs_available_channels; 463 464 /* Which output of the HVS this pixelvalve sources from. */ 465 int hvs_output; 466 }; 467 468 struct vc4_pv_data { 469 struct vc4_crtc_data base; 470 471 /* Depth of the PixelValve FIFO in bytes */ 472 unsigned int fifo_depth; 473 474 /* Number of pixels output per clock period */ 475 u8 pixels_per_clock; 476 477 enum vc4_encoder_type encoder_types[4]; 478 const char *debugfs_name; 479 480 }; 481 482 struct vc4_crtc { 483 struct drm_crtc base; 484 struct platform_device *pdev; 485 const struct vc4_crtc_data *data; 486 void __iomem *regs; 487 488 /* Timestamp at start of vblank irq - unaffected by lock delays. */ 489 ktime_t t_vblank; 490 491 u8 lut_r[256]; 492 u8 lut_g[256]; 493 u8 lut_b[256]; 494 495 struct drm_pending_vblank_event *event; 496 497 struct debugfs_regset32 regset; 498 499 /** 500 * @feeds_txp: True if the CRTC feeds our writeback controller. 501 */ 502 bool feeds_txp; 503 504 /** 505 * @irq_lock: Spinlock protecting the resources shared between 506 * the atomic code and our vblank handler. 507 */ 508 spinlock_t irq_lock; 509 510 /** 511 * @current_dlist: Start offset of the display list currently 512 * set in the HVS for that CRTC. Protected by @irq_lock, and 513 * copied in vc4_hvs_update_dlist() for the CRTC interrupt 514 * handler to have access to that value. 515 */ 516 unsigned int current_dlist; 517 518 /** 519 * @current_hvs_channel: HVS channel currently assigned to the 520 * CRTC. Protected by @irq_lock, and copied in 521 * vc4_hvs_atomic_begin() for the CRTC interrupt handler to have 522 * access to that value. 523 */ 524 unsigned int current_hvs_channel; 525 }; 526 527 static inline struct vc4_crtc * 528 to_vc4_crtc(struct drm_crtc *crtc) 529 { 530 return container_of(crtc, struct vc4_crtc, base); 531 } 532 533 static inline const struct vc4_crtc_data * 534 vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc) 535 { 536 return crtc->data; 537 } 538 539 static inline const struct vc4_pv_data * 540 vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc) 541 { 542 const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc); 543 544 return container_of(data, struct vc4_pv_data, base); 545 } 546 547 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc, 548 struct drm_crtc_state *state); 549 550 struct vc4_crtc_state { 551 struct drm_crtc_state base; 552 /* Dlist area for this CRTC configuration. */ 553 struct drm_mm_node mm; 554 bool txp_armed; 555 unsigned int assigned_channel; 556 557 struct { 558 unsigned int left; 559 unsigned int right; 560 unsigned int top; 561 unsigned int bottom; 562 } margins; 563 564 unsigned long hvs_load; 565 566 /* Transitional state below, only valid during atomic commits */ 567 bool update_muxing; 568 }; 569 570 #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1) 571 572 static inline struct vc4_crtc_state * 573 to_vc4_crtc_state(struct drm_crtc_state *crtc_state) 574 { 575 return container_of(crtc_state, struct vc4_crtc_state, base); 576 } 577 578 #define V3D_READ(offset) readl(vc4->v3d->regs + offset) 579 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 580 #define HVS_READ(offset) readl(hvs->regs + offset) 581 #define HVS_WRITE(offset, val) writel(val, hvs->regs + offset) 582 583 #define VC4_REG32(reg) { .name = #reg, .offset = reg } 584 585 struct vc4_exec_info { 586 struct vc4_dev *dev; 587 588 /* Sequence number for this bin/render job. */ 589 uint64_t seqno; 590 591 /* Latest write_seqno of any BO that binning depends on. */ 592 uint64_t bin_dep_seqno; 593 594 struct dma_fence *fence; 595 596 /* Last current addresses the hardware was processing when the 597 * hangcheck timer checked on us. 598 */ 599 uint32_t last_ct0ca, last_ct1ca; 600 601 /* Kernel-space copy of the ioctl arguments */ 602 struct drm_vc4_submit_cl *args; 603 604 /* This is the array of BOs that were looked up at the start of exec. 605 * Command validation will use indices into this array. 606 */ 607 struct drm_gem_cma_object **bo; 608 uint32_t bo_count; 609 610 /* List of BOs that are being written by the RCL. Other than 611 * the binner temporary storage, this is all the BOs written 612 * by the job. 613 */ 614 struct drm_gem_cma_object *rcl_write_bo[4]; 615 uint32_t rcl_write_bo_count; 616 617 /* Pointers for our position in vc4->job_list */ 618 struct list_head head; 619 620 /* List of other BOs used in the job that need to be released 621 * once the job is complete. 622 */ 623 struct list_head unref_list; 624 625 /* Current unvalidated indices into @bo loaded by the non-hardware 626 * VC4_PACKET_GEM_HANDLES. 627 */ 628 uint32_t bo_index[2]; 629 630 /* This is the BO where we store the validated command lists, shader 631 * records, and uniforms. 632 */ 633 struct drm_gem_cma_object *exec_bo; 634 635 /** 636 * This tracks the per-shader-record state (packet 64) that 637 * determines the length of the shader record and the offset 638 * it's expected to be found at. It gets read in from the 639 * command lists. 640 */ 641 struct vc4_shader_state { 642 uint32_t addr; 643 /* Maximum vertex index referenced by any primitive using this 644 * shader state. 645 */ 646 uint32_t max_index; 647 } *shader_state; 648 649 /** How many shader states the user declared they were using. */ 650 uint32_t shader_state_size; 651 /** How many shader state records the validator has seen. */ 652 uint32_t shader_state_count; 653 654 bool found_tile_binning_mode_config_packet; 655 bool found_start_tile_binning_packet; 656 bool found_increment_semaphore_packet; 657 bool found_flush; 658 uint8_t bin_tiles_x, bin_tiles_y; 659 /* Physical address of the start of the tile alloc array 660 * (where each tile's binned CL will start) 661 */ 662 uint32_t tile_alloc_offset; 663 /* Bitmask of which binner slots are freed when this job completes. */ 664 uint32_t bin_slots; 665 666 /** 667 * Computed addresses pointing into exec_bo where we start the 668 * bin thread (ct0) and render thread (ct1). 669 */ 670 uint32_t ct0ca, ct0ea; 671 uint32_t ct1ca, ct1ea; 672 673 /* Pointer to the unvalidated bin CL (if present). */ 674 void *bin_u; 675 676 /* Pointers to the shader recs. These paddr gets incremented as CL 677 * packets are relocated in validate_gl_shader_state, and the vaddrs 678 * (u and v) get incremented and size decremented as the shader recs 679 * themselves are validated. 680 */ 681 void *shader_rec_u; 682 void *shader_rec_v; 683 uint32_t shader_rec_p; 684 uint32_t shader_rec_size; 685 686 /* Pointers to the uniform data. These pointers are incremented, and 687 * size decremented, as each batch of uniforms is uploaded. 688 */ 689 void *uniforms_u; 690 void *uniforms_v; 691 uint32_t uniforms_p; 692 uint32_t uniforms_size; 693 694 /* Pointer to a performance monitor object if the user requested it, 695 * NULL otherwise. 696 */ 697 struct vc4_perfmon *perfmon; 698 699 /* Whether the exec has taken a reference to the binner BO, which should 700 * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet. 701 */ 702 bool bin_bo_used; 703 }; 704 705 /* Per-open file private data. Any driver-specific resource that has to be 706 * released when the DRM file is closed should be placed here. 707 */ 708 struct vc4_file { 709 struct vc4_dev *dev; 710 711 struct { 712 struct idr idr; 713 struct mutex lock; 714 } perfmon; 715 716 bool bin_bo_used; 717 }; 718 719 static inline struct vc4_exec_info * 720 vc4_first_bin_job(struct vc4_dev *vc4) 721 { 722 return list_first_entry_or_null(&vc4->bin_job_list, 723 struct vc4_exec_info, head); 724 } 725 726 static inline struct vc4_exec_info * 727 vc4_first_render_job(struct vc4_dev *vc4) 728 { 729 return list_first_entry_or_null(&vc4->render_job_list, 730 struct vc4_exec_info, head); 731 } 732 733 static inline struct vc4_exec_info * 734 vc4_last_render_job(struct vc4_dev *vc4) 735 { 736 if (list_empty(&vc4->render_job_list)) 737 return NULL; 738 return list_last_entry(&vc4->render_job_list, 739 struct vc4_exec_info, head); 740 } 741 742 /** 743 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 744 * setup parameters. 745 * 746 * This will be used at draw time to relocate the reference to the texture 747 * contents in p0, and validate that the offset combined with 748 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 749 * Note that the hardware treats unprovided config parameters as 0, so not all 750 * of them need to be set up for every texure sample, and we'll store ~0 as 751 * the offset to mark the unused ones. 752 * 753 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 754 * Setup") for definitions of the texture parameters. 755 */ 756 struct vc4_texture_sample_info { 757 bool is_direct; 758 uint32_t p_offset[4]; 759 }; 760 761 /** 762 * struct vc4_validated_shader_info - information about validated shaders that 763 * needs to be used from command list validation. 764 * 765 * For a given shader, each time a shader state record references it, we need 766 * to verify that the shader doesn't read more uniforms than the shader state 767 * record's uniform BO pointer can provide, and we need to apply relocations 768 * and validate the shader state record's uniforms that define the texture 769 * samples. 770 */ 771 struct vc4_validated_shader_info { 772 uint32_t uniforms_size; 773 uint32_t uniforms_src_size; 774 uint32_t num_texture_samples; 775 struct vc4_texture_sample_info *texture_samples; 776 777 uint32_t num_uniform_addr_offsets; 778 uint32_t *uniform_addr_offsets; 779 780 bool is_threaded; 781 }; 782 783 /** 784 * __wait_for - magic wait macro 785 * 786 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 787 * important that we check the condition again after having timed out, since the 788 * timeout could be due to preemption or similar and we've never had a chance to 789 * check the condition before the timeout. 790 */ 791 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 792 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 793 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 794 int ret__; \ 795 might_sleep(); \ 796 for (;;) { \ 797 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 798 OP; \ 799 /* Guarantee COND check prior to timeout */ \ 800 barrier(); \ 801 if (COND) { \ 802 ret__ = 0; \ 803 break; \ 804 } \ 805 if (expired__) { \ 806 ret__ = -ETIMEDOUT; \ 807 break; \ 808 } \ 809 usleep_range(wait__, wait__ * 2); \ 810 if (wait__ < (Wmax)) \ 811 wait__ <<= 1; \ 812 } \ 813 ret__; \ 814 }) 815 816 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 817 (Wmax)) 818 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 819 820 /* vc4_bo.c */ 821 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 822 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 823 bool from_cache, enum vc4_kernel_bo_type type); 824 int vc4_bo_dumb_create(struct drm_file *file_priv, 825 struct drm_device *dev, 826 struct drm_mode_create_dumb *args); 827 int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 828 struct drm_file *file_priv); 829 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 830 struct drm_file *file_priv); 831 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 832 struct drm_file *file_priv); 833 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data, 834 struct drm_file *file_priv); 835 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data, 836 struct drm_file *file_priv); 837 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, 838 struct drm_file *file_priv); 839 int vc4_label_bo_ioctl(struct drm_device *dev, void *data, 840 struct drm_file *file_priv); 841 int vc4_bo_cache_init(struct drm_device *dev); 842 int vc4_bo_inc_usecnt(struct vc4_bo *bo); 843 void vc4_bo_dec_usecnt(struct vc4_bo *bo); 844 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo); 845 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo); 846 847 /* vc4_crtc.c */ 848 extern struct platform_driver vc4_crtc_driver; 849 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc); 850 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, 851 const struct drm_crtc_funcs *crtc_funcs, 852 const struct drm_crtc_helper_funcs *crtc_helper_funcs); 853 void vc4_crtc_destroy(struct drm_crtc *crtc); 854 int vc4_page_flip(struct drm_crtc *crtc, 855 struct drm_framebuffer *fb, 856 struct drm_pending_vblank_event *event, 857 uint32_t flags, 858 struct drm_modeset_acquire_ctx *ctx); 859 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc); 860 void vc4_crtc_destroy_state(struct drm_crtc *crtc, 861 struct drm_crtc_state *state); 862 void vc4_crtc_reset(struct drm_crtc *crtc); 863 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc); 864 void vc4_crtc_get_margins(struct drm_crtc_state *state, 865 unsigned int *left, unsigned int *right, 866 unsigned int *top, unsigned int *bottom); 867 868 /* vc4_debugfs.c */ 869 void vc4_debugfs_init(struct drm_minor *minor); 870 #ifdef CONFIG_DEBUG_FS 871 void vc4_debugfs_add_file(struct drm_device *drm, 872 const char *filename, 873 int (*show)(struct seq_file*, void*), 874 void *data); 875 void vc4_debugfs_add_regset32(struct drm_device *drm, 876 const char *filename, 877 struct debugfs_regset32 *regset); 878 #else 879 static inline void vc4_debugfs_add_file(struct drm_device *drm, 880 const char *filename, 881 int (*show)(struct seq_file*, void*), 882 void *data) 883 { 884 } 885 886 static inline void vc4_debugfs_add_regset32(struct drm_device *drm, 887 const char *filename, 888 struct debugfs_regset32 *regset) 889 { 890 } 891 #endif 892 893 /* vc4_drv.c */ 894 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 895 int vc4_dumb_fixup_args(struct drm_mode_create_dumb *args); 896 897 /* vc4_dpi.c */ 898 extern struct platform_driver vc4_dpi_driver; 899 900 /* vc4_dsi.c */ 901 extern struct platform_driver vc4_dsi_driver; 902 903 /* vc4_fence.c */ 904 extern const struct dma_fence_ops vc4_fence_ops; 905 906 /* vc4_gem.c */ 907 int vc4_gem_init(struct drm_device *dev); 908 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 909 struct drm_file *file_priv); 910 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 911 struct drm_file *file_priv); 912 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 913 struct drm_file *file_priv); 914 void vc4_submit_next_bin_job(struct drm_device *dev); 915 void vc4_submit_next_render_job(struct drm_device *dev); 916 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec); 917 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 918 uint64_t timeout_ns, bool interruptible); 919 void vc4_job_handle_completed(struct vc4_dev *vc4); 920 int vc4_queue_seqno_cb(struct drm_device *dev, 921 struct vc4_seqno_cb *cb, uint64_t seqno, 922 void (*func)(struct vc4_seqno_cb *cb)); 923 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data, 924 struct drm_file *file_priv); 925 926 /* vc4_hdmi.c */ 927 extern struct platform_driver vc4_hdmi_driver; 928 929 /* vc4_vec.c */ 930 extern struct platform_driver vc4_vec_driver; 931 932 /* vc4_txp.c */ 933 extern struct platform_driver vc4_txp_driver; 934 935 /* vc4_irq.c */ 936 void vc4_irq_enable(struct drm_device *dev); 937 void vc4_irq_disable(struct drm_device *dev); 938 int vc4_irq_install(struct drm_device *dev, int irq); 939 void vc4_irq_uninstall(struct drm_device *dev); 940 void vc4_irq_reset(struct drm_device *dev); 941 942 /* vc4_hvs.c */ 943 extern struct platform_driver vc4_hvs_driver; 944 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int output); 945 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output); 946 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo); 947 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state); 948 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state); 949 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state); 950 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state); 951 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state); 952 void vc4_hvs_dump_state(struct vc4_hvs *hvs); 953 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel); 954 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel); 955 956 /* vc4_kms.c */ 957 int vc4_kms_load(struct drm_device *dev); 958 959 /* vc4_plane.c */ 960 struct drm_plane *vc4_plane_init(struct drm_device *dev, 961 enum drm_plane_type type); 962 int vc4_plane_create_additional_planes(struct drm_device *dev); 963 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 964 u32 vc4_plane_dlist_size(const struct drm_plane_state *state); 965 void vc4_plane_async_set_fb(struct drm_plane *plane, 966 struct drm_framebuffer *fb); 967 968 /* vc4_v3d.c */ 969 extern struct platform_driver vc4_v3d_driver; 970 extern const struct of_device_id vc4_v3d_dt_match[]; 971 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4); 972 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used); 973 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4); 974 int vc4_v3d_pm_get(struct vc4_dev *vc4); 975 void vc4_v3d_pm_put(struct vc4_dev *vc4); 976 977 /* vc4_validate.c */ 978 int 979 vc4_validate_bin_cl(struct drm_device *dev, 980 void *validated, 981 void *unvalidated, 982 struct vc4_exec_info *exec); 983 984 int 985 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 986 987 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 988 uint32_t hindex); 989 990 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 991 992 bool vc4_check_tex_size(struct vc4_exec_info *exec, 993 struct drm_gem_cma_object *fbo, 994 uint32_t offset, uint8_t tiling_format, 995 uint32_t width, uint32_t height, uint8_t cpp); 996 997 /* vc4_validate_shader.c */ 998 struct vc4_validated_shader_info * 999 vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 1000 1001 /* vc4_perfmon.c */ 1002 void vc4_perfmon_get(struct vc4_perfmon *perfmon); 1003 void vc4_perfmon_put(struct vc4_perfmon *perfmon); 1004 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon); 1005 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon, 1006 bool capture); 1007 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id); 1008 void vc4_perfmon_open_file(struct vc4_file *vc4file); 1009 void vc4_perfmon_close_file(struct vc4_file *vc4file); 1010 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data, 1011 struct drm_file *file_priv); 1012 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 1013 struct drm_file *file_priv); 1014 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 1015 struct drm_file *file_priv); 1016 1017 #endif /* _VC4_DRV_H_ */ 1018