1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 CRTC module 8 * 9 * In VC4, the Pixel Valve is what most closely corresponds to the 10 * DRM's concept of a CRTC. The PV generates video timings from the 11 * encoder's clock plus its configuration. It pulls scaled pixels from 12 * the HVS at that timing, and feeds it to the encoder. 13 * 14 * However, the DRM CRTC also collects the configuration of all the 15 * DRM planes attached to it. As a result, the CRTC is also 16 * responsible for writing the display list for the HVS channel that 17 * the CRTC will use. 18 * 19 * The 2835 has 3 different pixel valves. pv0 in the audio power 20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the 21 * image domain can feed either HDMI or the SDTV controller. The 22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for 23 * SDTV, etc.) according to which output type is chosen in the mux. 24 * 25 * For power management, the pixel valve's registers are all clocked 26 * by the AXI clock, while the timings and FIFOs make use of the 27 * output-specific clock. Since the encoders also directly consume 28 * the CPRMAN clocks, and know what timings they need, they are the 29 * ones that set the clock. 30 */ 31 32 #include <linux/clk.h> 33 #include <linux/component.h> 34 #include <linux/of_device.h> 35 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_atomic_uapi.h> 39 #include <drm/drm_fb_cma_helper.h> 40 #include <drm/drm_print.h> 41 #include <drm/drm_probe_helper.h> 42 #include <drm/drm_vblank.h> 43 44 #include "vc4_drv.h" 45 #include "vc4_regs.h" 46 47 #define HVS_FIFO_LATENCY_PIX 6 48 49 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) 50 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) 51 52 static const struct debugfs_reg32 crtc_regs[] = { 53 VC4_REG32(PV_CONTROL), 54 VC4_REG32(PV_V_CONTROL), 55 VC4_REG32(PV_VSYNCD_EVEN), 56 VC4_REG32(PV_HORZA), 57 VC4_REG32(PV_HORZB), 58 VC4_REG32(PV_VERTA), 59 VC4_REG32(PV_VERTB), 60 VC4_REG32(PV_VERTA_EVEN), 61 VC4_REG32(PV_VERTB_EVEN), 62 VC4_REG32(PV_INTEN), 63 VC4_REG32(PV_INTSTAT), 64 VC4_REG32(PV_STAT), 65 VC4_REG32(PV_HACT_ACT), 66 }; 67 68 static unsigned int 69 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel) 70 { 71 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel)); 72 /* Top/base are supposed to be 4-pixel aligned, but the 73 * Raspberry Pi firmware fills the low bits (which are 74 * presumably ignored). 75 */ 76 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3; 77 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; 78 79 return top - base + 4; 80 } 81 82 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc, 83 bool in_vblank_irq, 84 int *vpos, int *hpos, 85 ktime_t *stime, ktime_t *etime, 86 const struct drm_display_mode *mode) 87 { 88 struct drm_device *dev = crtc->dev; 89 struct vc4_dev *vc4 = to_vc4_dev(dev); 90 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 91 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 92 unsigned int cob_size; 93 u32 val; 94 int fifo_lines; 95 int vblank_lines; 96 bool ret = false; 97 98 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 99 100 /* Get optional system timestamp before query. */ 101 if (stime) 102 *stime = ktime_get(); 103 104 /* 105 * Read vertical scanline which is currently composed for our 106 * pixelvalve by the HVS, and also the scaler status. 107 */ 108 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel)); 109 110 /* Get optional system timestamp after query. */ 111 if (etime) 112 *etime = ktime_get(); 113 114 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 115 116 /* Vertical position of hvs composed scanline. */ 117 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE); 118 *hpos = 0; 119 120 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 121 *vpos /= 2; 122 123 /* Use hpos to correct for field offset in interlaced mode. */ 124 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2) 125 *hpos += mode->crtc_htotal / 2; 126 } 127 128 cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel); 129 /* This is the offset we need for translating hvs -> pv scanout pos. */ 130 fifo_lines = cob_size / mode->crtc_hdisplay; 131 132 if (fifo_lines > 0) 133 ret = true; 134 135 /* HVS more than fifo_lines into frame for compositing? */ 136 if (*vpos > fifo_lines) { 137 /* 138 * We are in active scanout and can get some meaningful results 139 * from HVS. The actual PV scanout can not trail behind more 140 * than fifo_lines as that is the fifo's capacity. Assume that 141 * in active scanout the HVS and PV work in lockstep wrt. HVS 142 * refilling the fifo and PV consuming from the fifo, ie. 143 * whenever the PV consumes and frees up a scanline in the 144 * fifo, the HVS will immediately refill it, therefore 145 * incrementing vpos. Therefore we choose HVS read position - 146 * fifo size in scanlines as a estimate of the real scanout 147 * position of the PV. 148 */ 149 *vpos -= fifo_lines + 1; 150 151 return ret; 152 } 153 154 /* 155 * Less: This happens when we are in vblank and the HVS, after getting 156 * the VSTART restart signal from the PV, just started refilling its 157 * fifo with new lines from the top-most lines of the new framebuffers. 158 * The PV does not scan out in vblank, so does not remove lines from 159 * the fifo, so the fifo will be full quickly and the HVS has to pause. 160 * We can't get meaningful readings wrt. scanline position of the PV 161 * and need to make things up in a approximative but consistent way. 162 */ 163 vblank_lines = mode->vtotal - mode->vdisplay; 164 165 if (in_vblank_irq) { 166 /* 167 * Assume the irq handler got called close to first 168 * line of vblank, so PV has about a full vblank 169 * scanlines to go, and as a base timestamp use the 170 * one taken at entry into vblank irq handler, so it 171 * is not affected by random delays due to lock 172 * contention on event_lock or vblank_time lock in 173 * the core. 174 */ 175 *vpos = -vblank_lines; 176 177 if (stime) 178 *stime = vc4_crtc->t_vblank; 179 if (etime) 180 *etime = vc4_crtc->t_vblank; 181 182 /* 183 * If the HVS fifo is not yet full then we know for certain 184 * we are at the very beginning of vblank, as the hvs just 185 * started refilling, and the stime and etime timestamps 186 * truly correspond to start of vblank. 187 * 188 * Unfortunately there's no way to report this to upper levels 189 * and make it more useful. 190 */ 191 } else { 192 /* 193 * No clue where we are inside vblank. Return a vpos of zero, 194 * which will cause calling code to just return the etime 195 * timestamp uncorrected. At least this is no worse than the 196 * standard fallback. 197 */ 198 *vpos = 0; 199 } 200 201 return ret; 202 } 203 204 void vc4_crtc_destroy(struct drm_crtc *crtc) 205 { 206 drm_crtc_cleanup(crtc); 207 } 208 209 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format) 210 { 211 const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc); 212 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 213 u32 fifo_len_bytes = pv_data->fifo_depth; 214 215 /* 216 * Pixels are pulled from the HVS if the number of bytes is 217 * lower than the FIFO full level. 218 * 219 * The latency of the pixel fetch mechanism is 6 pixels, so we 220 * need to convert those 6 pixels in bytes, depending on the 221 * format, and then subtract that from the length of the FIFO 222 * to make sure we never end up in a situation where the FIFO 223 * is full. 224 */ 225 switch (format) { 226 case PV_CONTROL_FORMAT_DSIV_16: 227 case PV_CONTROL_FORMAT_DSIC_16: 228 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX; 229 case PV_CONTROL_FORMAT_DSIV_18: 230 return fifo_len_bytes - 14; 231 case PV_CONTROL_FORMAT_24: 232 case PV_CONTROL_FORMAT_DSIV_24: 233 default: 234 /* 235 * For some reason, the pixelvalve4 doesn't work with 236 * the usual formula and will only work with 32. 237 */ 238 if (crtc_data->hvs_output == 5) 239 return 32; 240 241 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX; 242 } 243 } 244 245 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc, 246 u32 format) 247 { 248 u32 level = vc4_get_fifo_full_level(vc4_crtc, format); 249 u32 ret = 0; 250 251 ret |= VC4_SET_FIELD((level >> 6), 252 PV5_CONTROL_FIFO_LEVEL_HIGH); 253 254 return ret | VC4_SET_FIELD(level & 0x3f, 255 PV_CONTROL_FIFO_LEVEL); 256 } 257 258 /* 259 * Returns the encoder attached to the CRTC. 260 * 261 * VC4 can only scan out to one encoder at a time, while the DRM core 262 * allows drivers to push pixels to more than one encoder from the 263 * same CRTC. 264 */ 265 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) 266 { 267 struct drm_connector *connector; 268 struct drm_connector_list_iter conn_iter; 269 270 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 271 drm_for_each_connector_iter(connector, &conn_iter) { 272 if (connector->state->crtc == crtc) { 273 drm_connector_list_iter_end(&conn_iter); 274 return connector->encoder; 275 } 276 } 277 drm_connector_list_iter_end(&conn_iter); 278 279 return NULL; 280 } 281 282 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc) 283 { 284 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 285 286 /* The PV needs to be disabled before it can be flushed */ 287 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); 288 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR); 289 } 290 291 static void vc4_crtc_config_pv(struct drm_crtc *crtc) 292 { 293 struct drm_device *dev = crtc->dev; 294 struct vc4_dev *vc4 = to_vc4_dev(dev); 295 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); 296 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 297 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 298 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 299 struct drm_crtc_state *state = crtc->state; 300 struct drm_display_mode *mode = &state->adjusted_mode; 301 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 302 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 303 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || 304 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); 305 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; 306 u8 ppc = pv_data->pixels_per_clock; 307 bool debug_dump_regs = false; 308 309 if (debug_dump_regs) { 310 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); 311 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n", 312 drm_crtc_index(crtc)); 313 drm_print_regset32(&p, &vc4_crtc->regset); 314 } 315 316 vc4_crtc_pixelvalve_reset(crtc); 317 318 CRTC_WRITE(PV_HORZA, 319 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, 320 PV_HORZA_HBP) | 321 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, 322 PV_HORZA_HSYNC)); 323 324 CRTC_WRITE(PV_HORZB, 325 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, 326 PV_HORZB_HFP) | 327 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, 328 PV_HORZB_HACTIVE)); 329 330 CRTC_WRITE(PV_VERTA, 331 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 332 PV_VERTA_VBP) | 333 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 334 PV_VERTA_VSYNC)); 335 CRTC_WRITE(PV_VERTB, 336 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 337 PV_VERTB_VFP) | 338 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); 339 340 if (interlace) { 341 CRTC_WRITE(PV_VERTA_EVEN, 342 VC4_SET_FIELD(mode->crtc_vtotal - 343 mode->crtc_vsync_end - 1, 344 PV_VERTA_VBP) | 345 VC4_SET_FIELD(mode->crtc_vsync_end - 346 mode->crtc_vsync_start, 347 PV_VERTA_VSYNC)); 348 CRTC_WRITE(PV_VERTB_EVEN, 349 VC4_SET_FIELD(mode->crtc_vsync_start - 350 mode->crtc_vdisplay, 351 PV_VERTB_VFP) | 352 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); 353 354 /* We set up first field even mode for HDMI. VEC's 355 * NTSC mode would want first field odd instead, once 356 * we support it (to do so, set ODD_FIRST and put the 357 * delay in VSYNCD_EVEN instead). 358 */ 359 CRTC_WRITE(PV_V_CONTROL, 360 PV_VCONTROL_CONTINUOUS | 361 (is_dsi ? PV_VCONTROL_DSI : 0) | 362 PV_VCONTROL_INTERLACE | 363 VC4_SET_FIELD(mode->htotal * pixel_rep / 2, 364 PV_VCONTROL_ODD_DELAY)); 365 CRTC_WRITE(PV_VSYNCD_EVEN, 0); 366 } else { 367 CRTC_WRITE(PV_V_CONTROL, 368 PV_VCONTROL_CONTINUOUS | 369 (is_dsi ? PV_VCONTROL_DSI : 0)); 370 } 371 372 if (is_dsi) 373 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); 374 375 if (vc4->hvs->hvs5) 376 CRTC_WRITE(PV_MUX_CFG, 377 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP, 378 PV_MUX_CFG_RGB_PIXEL_MUX_MODE)); 379 380 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | 381 vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) | 382 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | 383 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | 384 PV_CONTROL_CLR_AT_START | 385 PV_CONTROL_TRIGGER_UNDERFLOW | 386 PV_CONTROL_WAIT_HSTART | 387 VC4_SET_FIELD(vc4_encoder->clock_select, 388 PV_CONTROL_CLK_SELECT)); 389 390 if (debug_dump_regs) { 391 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); 392 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n", 393 drm_crtc_index(crtc)); 394 drm_print_regset32(&p, &vc4_crtc->regset); 395 } 396 } 397 398 static void require_hvs_enabled(struct drm_device *dev) 399 { 400 struct vc4_dev *vc4 = to_vc4_dev(dev); 401 402 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != 403 SCALER_DISPCTRL_ENABLE); 404 } 405 406 static int vc4_crtc_disable(struct drm_crtc *crtc, 407 struct drm_atomic_state *state, 408 unsigned int channel) 409 { 410 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); 411 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 412 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 413 struct drm_device *dev = crtc->dev; 414 int ret; 415 416 CRTC_WRITE(PV_V_CONTROL, 417 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); 418 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); 419 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); 420 421 /* 422 * This delay is needed to avoid to get a pixel stuck in an 423 * unflushable FIFO between the pixelvalve and the HDMI 424 * controllers on the BCM2711. 425 * 426 * Timing is fairly sensitive here, so mdelay is the safest 427 * approach. 428 * 429 * If it was to be reworked, the stuck pixel happens on a 430 * BCM2711 when changing mode with a good probability, so a 431 * script that changes mode on a regular basis should trigger 432 * the bug after less than 10 attempts. It manifests itself with 433 * every pixels being shifted by one to the right, and thus the 434 * last pixel of a line actually being displayed as the first 435 * pixel on the next line. 436 */ 437 mdelay(20); 438 439 if (vc4_encoder && vc4_encoder->post_crtc_disable) 440 vc4_encoder->post_crtc_disable(encoder, state); 441 442 vc4_crtc_pixelvalve_reset(crtc); 443 vc4_hvs_stop_channel(dev, channel); 444 445 if (vc4_encoder && vc4_encoder->post_crtc_powerdown) 446 vc4_encoder->post_crtc_powerdown(encoder, state); 447 448 return 0; 449 } 450 451 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc) 452 { 453 struct drm_device *drm = crtc->dev; 454 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 455 int channel; 456 457 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node, 458 "brcm,bcm2711-pixelvalve2") || 459 of_device_is_compatible(vc4_crtc->pdev->dev.of_node, 460 "brcm,bcm2711-pixelvalve4"))) 461 return 0; 462 463 if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN)) 464 return 0; 465 466 if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN)) 467 return 0; 468 469 channel = vc4_hvs_get_fifo_from_output(drm, vc4_crtc->data->hvs_output); 470 if (channel < 0) 471 return 0; 472 473 return vc4_crtc_disable(crtc, NULL, channel); 474 } 475 476 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, 477 struct drm_atomic_state *state) 478 { 479 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 480 crtc); 481 struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state); 482 struct drm_device *dev = crtc->dev; 483 484 require_hvs_enabled(dev); 485 486 /* Disable vblank irq handling before crtc is disabled. */ 487 drm_crtc_vblank_off(crtc); 488 489 vc4_crtc_disable(crtc, state, old_vc4_state->assigned_channel); 490 491 /* 492 * Make sure we issue a vblank event after disabling the CRTC if 493 * someone was waiting it. 494 */ 495 if (crtc->state->event) { 496 unsigned long flags; 497 498 spin_lock_irqsave(&dev->event_lock, flags); 499 drm_crtc_send_vblank_event(crtc, crtc->state->event); 500 crtc->state->event = NULL; 501 spin_unlock_irqrestore(&dev->event_lock, flags); 502 } 503 } 504 505 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, 506 struct drm_atomic_state *state) 507 { 508 struct drm_device *dev = crtc->dev; 509 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 510 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); 511 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 512 513 require_hvs_enabled(dev); 514 515 /* Enable vblank irq handling before crtc is started otherwise 516 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist(). 517 */ 518 drm_crtc_vblank_on(crtc); 519 520 vc4_hvs_atomic_enable(crtc, state); 521 522 if (vc4_encoder->pre_crtc_configure) 523 vc4_encoder->pre_crtc_configure(encoder, state); 524 525 vc4_crtc_config_pv(crtc); 526 527 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN); 528 529 if (vc4_encoder->pre_crtc_enable) 530 vc4_encoder->pre_crtc_enable(encoder, state); 531 532 /* When feeding the transposer block the pixelvalve is unneeded and 533 * should not be enabled. 534 */ 535 CRTC_WRITE(PV_V_CONTROL, 536 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); 537 538 if (vc4_encoder->post_crtc_enable) 539 vc4_encoder->post_crtc_enable(encoder, state); 540 } 541 542 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc, 543 const struct drm_display_mode *mode) 544 { 545 /* Do not allow doublescan modes from user space */ 546 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 547 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n", 548 crtc->base.id); 549 return MODE_NO_DBLESCAN; 550 } 551 552 return MODE_OK; 553 } 554 555 void vc4_crtc_get_margins(struct drm_crtc_state *state, 556 unsigned int *left, unsigned int *right, 557 unsigned int *top, unsigned int *bottom) 558 { 559 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 560 struct drm_connector_state *conn_state; 561 struct drm_connector *conn; 562 int i; 563 564 *left = vc4_state->margins.left; 565 *right = vc4_state->margins.right; 566 *top = vc4_state->margins.top; 567 *bottom = vc4_state->margins.bottom; 568 569 /* We have to interate over all new connector states because 570 * vc4_crtc_get_margins() might be called before 571 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state 572 * might be outdated. 573 */ 574 for_each_new_connector_in_state(state->state, conn, conn_state, i) { 575 if (conn_state->crtc != state->crtc) 576 continue; 577 578 *left = conn_state->tv.margins.left; 579 *right = conn_state->tv.margins.right; 580 *top = conn_state->tv.margins.top; 581 *bottom = conn_state->tv.margins.bottom; 582 break; 583 } 584 } 585 586 static int vc4_crtc_atomic_check(struct drm_crtc *crtc, 587 struct drm_atomic_state *state) 588 { 589 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 590 crtc); 591 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 592 struct drm_connector *conn; 593 struct drm_connector_state *conn_state; 594 int ret, i; 595 596 ret = vc4_hvs_atomic_check(crtc, state); 597 if (ret) 598 return ret; 599 600 for_each_new_connector_in_state(state, conn, conn_state, 601 i) { 602 if (conn_state->crtc != crtc) 603 continue; 604 605 vc4_state->margins.left = conn_state->tv.margins.left; 606 vc4_state->margins.right = conn_state->tv.margins.right; 607 vc4_state->margins.top = conn_state->tv.margins.top; 608 vc4_state->margins.bottom = conn_state->tv.margins.bottom; 609 break; 610 } 611 612 return 0; 613 } 614 615 static int vc4_enable_vblank(struct drm_crtc *crtc) 616 { 617 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 618 619 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); 620 621 return 0; 622 } 623 624 static void vc4_disable_vblank(struct drm_crtc *crtc) 625 { 626 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 627 628 CRTC_WRITE(PV_INTEN, 0); 629 } 630 631 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) 632 { 633 struct drm_crtc *crtc = &vc4_crtc->base; 634 struct drm_device *dev = crtc->dev; 635 struct vc4_dev *vc4 = to_vc4_dev(dev); 636 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 637 u32 chan = vc4_state->assigned_channel; 638 unsigned long flags; 639 640 spin_lock_irqsave(&dev->event_lock, flags); 641 if (vc4_crtc->event && 642 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) || 643 vc4_state->feed_txp)) { 644 drm_crtc_send_vblank_event(crtc, vc4_crtc->event); 645 vc4_crtc->event = NULL; 646 drm_crtc_vblank_put(crtc); 647 648 /* Wait for the page flip to unmask the underrun to ensure that 649 * the display list was updated by the hardware. Before that 650 * happens, the HVS will be using the previous display list with 651 * the CRTC and encoder already reconfigured, leading to 652 * underruns. This can be seen when reconfiguring the CRTC. 653 */ 654 vc4_hvs_unmask_underrun(dev, chan); 655 } 656 spin_unlock_irqrestore(&dev->event_lock, flags); 657 } 658 659 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc) 660 { 661 crtc->t_vblank = ktime_get(); 662 drm_crtc_handle_vblank(&crtc->base); 663 vc4_crtc_handle_page_flip(crtc); 664 } 665 666 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data) 667 { 668 struct vc4_crtc *vc4_crtc = data; 669 u32 stat = CRTC_READ(PV_INTSTAT); 670 irqreturn_t ret = IRQ_NONE; 671 672 if (stat & PV_INT_VFP_START) { 673 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); 674 vc4_crtc_handle_vblank(vc4_crtc); 675 ret = IRQ_HANDLED; 676 } 677 678 return ret; 679 } 680 681 struct vc4_async_flip_state { 682 struct drm_crtc *crtc; 683 struct drm_framebuffer *fb; 684 struct drm_framebuffer *old_fb; 685 struct drm_pending_vblank_event *event; 686 687 struct vc4_seqno_cb cb; 688 }; 689 690 /* Called when the V3D execution for the BO being flipped to is done, so that 691 * we can actually update the plane's address to point to it. 692 */ 693 static void 694 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) 695 { 696 struct vc4_async_flip_state *flip_state = 697 container_of(cb, struct vc4_async_flip_state, cb); 698 struct drm_crtc *crtc = flip_state->crtc; 699 struct drm_device *dev = crtc->dev; 700 struct drm_plane *plane = crtc->primary; 701 702 vc4_plane_async_set_fb(plane, flip_state->fb); 703 if (flip_state->event) { 704 unsigned long flags; 705 706 spin_lock_irqsave(&dev->event_lock, flags); 707 drm_crtc_send_vblank_event(crtc, flip_state->event); 708 spin_unlock_irqrestore(&dev->event_lock, flags); 709 } 710 711 drm_crtc_vblank_put(crtc); 712 drm_framebuffer_put(flip_state->fb); 713 714 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced 715 * when the planes are updated through the async update path. 716 * FIXME: we should move to generic async-page-flip when it's 717 * available, so that we can get rid of this hand-made cleanup_fb() 718 * logic. 719 */ 720 if (flip_state->old_fb) { 721 struct drm_gem_cma_object *cma_bo; 722 struct vc4_bo *bo; 723 724 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0); 725 bo = to_vc4_bo(&cma_bo->base); 726 vc4_bo_dec_usecnt(bo); 727 drm_framebuffer_put(flip_state->old_fb); 728 } 729 730 kfree(flip_state); 731 } 732 733 /* Implements async (non-vblank-synced) page flips. 734 * 735 * The page flip ioctl needs to return immediately, so we grab the 736 * modeset semaphore on the pipe, and queue the address update for 737 * when V3D is done with the BO being flipped to. 738 */ 739 static int vc4_async_page_flip(struct drm_crtc *crtc, 740 struct drm_framebuffer *fb, 741 struct drm_pending_vblank_event *event, 742 uint32_t flags) 743 { 744 struct drm_device *dev = crtc->dev; 745 struct drm_plane *plane = crtc->primary; 746 int ret = 0; 747 struct vc4_async_flip_state *flip_state; 748 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0); 749 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); 750 751 /* Increment the BO usecnt here, so that we never end up with an 752 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the 753 * plane is later updated through the non-async path. 754 * FIXME: we should move to generic async-page-flip when it's 755 * available, so that we can get rid of this hand-made prepare_fb() 756 * logic. 757 */ 758 ret = vc4_bo_inc_usecnt(bo); 759 if (ret) 760 return ret; 761 762 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL); 763 if (!flip_state) { 764 vc4_bo_dec_usecnt(bo); 765 return -ENOMEM; 766 } 767 768 drm_framebuffer_get(fb); 769 flip_state->fb = fb; 770 flip_state->crtc = crtc; 771 flip_state->event = event; 772 773 /* Save the current FB before it's replaced by the new one in 774 * drm_atomic_set_fb_for_plane(). We'll need the old FB in 775 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep 776 * it consistent. 777 * FIXME: we should move to generic async-page-flip when it's 778 * available, so that we can get rid of this hand-made cleanup_fb() 779 * logic. 780 */ 781 flip_state->old_fb = plane->state->fb; 782 if (flip_state->old_fb) 783 drm_framebuffer_get(flip_state->old_fb); 784 785 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 786 787 /* Immediately update the plane's legacy fb pointer, so that later 788 * modeset prep sees the state that will be present when the semaphore 789 * is released. 790 */ 791 drm_atomic_set_fb_for_plane(plane->state, fb); 792 793 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno, 794 vc4_async_page_flip_complete); 795 796 /* Driver takes ownership of state on successful async commit. */ 797 return 0; 798 } 799 800 int vc4_page_flip(struct drm_crtc *crtc, 801 struct drm_framebuffer *fb, 802 struct drm_pending_vblank_event *event, 803 uint32_t flags, 804 struct drm_modeset_acquire_ctx *ctx) 805 { 806 if (flags & DRM_MODE_PAGE_FLIP_ASYNC) 807 return vc4_async_page_flip(crtc, fb, event, flags); 808 else 809 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx); 810 } 811 812 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc) 813 { 814 struct vc4_crtc_state *vc4_state, *old_vc4_state; 815 816 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); 817 if (!vc4_state) 818 return NULL; 819 820 old_vc4_state = to_vc4_crtc_state(crtc->state); 821 vc4_state->feed_txp = old_vc4_state->feed_txp; 822 vc4_state->margins = old_vc4_state->margins; 823 vc4_state->assigned_channel = old_vc4_state->assigned_channel; 824 825 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); 826 return &vc4_state->base; 827 } 828 829 void vc4_crtc_destroy_state(struct drm_crtc *crtc, 830 struct drm_crtc_state *state) 831 { 832 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); 833 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 834 835 if (drm_mm_node_allocated(&vc4_state->mm)) { 836 unsigned long flags; 837 838 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 839 drm_mm_remove_node(&vc4_state->mm); 840 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 841 842 } 843 844 drm_atomic_helper_crtc_destroy_state(crtc, state); 845 } 846 847 void vc4_crtc_reset(struct drm_crtc *crtc) 848 { 849 struct vc4_crtc_state *vc4_crtc_state; 850 851 if (crtc->state) 852 vc4_crtc_destroy_state(crtc, crtc->state); 853 854 vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL); 855 if (!vc4_crtc_state) { 856 crtc->state = NULL; 857 return; 858 } 859 860 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; 861 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base); 862 } 863 864 static const struct drm_crtc_funcs vc4_crtc_funcs = { 865 .set_config = drm_atomic_helper_set_config, 866 .destroy = vc4_crtc_destroy, 867 .page_flip = vc4_page_flip, 868 .set_property = NULL, 869 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */ 870 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */ 871 .reset = vc4_crtc_reset, 872 .atomic_duplicate_state = vc4_crtc_duplicate_state, 873 .atomic_destroy_state = vc4_crtc_destroy_state, 874 .enable_vblank = vc4_enable_vblank, 875 .disable_vblank = vc4_disable_vblank, 876 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 877 }; 878 879 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { 880 .mode_valid = vc4_crtc_mode_valid, 881 .atomic_check = vc4_crtc_atomic_check, 882 .atomic_flush = vc4_hvs_atomic_flush, 883 .atomic_enable = vc4_crtc_atomic_enable, 884 .atomic_disable = vc4_crtc_atomic_disable, 885 .get_scanout_position = vc4_crtc_get_scanout_position, 886 }; 887 888 static const struct vc4_pv_data bcm2835_pv0_data = { 889 .base = { 890 .hvs_available_channels = BIT(0), 891 .hvs_output = 0, 892 }, 893 .debugfs_name = "crtc0_regs", 894 .fifo_depth = 64, 895 .pixels_per_clock = 1, 896 .encoder_types = { 897 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, 898 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI, 899 }, 900 }; 901 902 static const struct vc4_pv_data bcm2835_pv1_data = { 903 .base = { 904 .hvs_available_channels = BIT(2), 905 .hvs_output = 2, 906 }, 907 .debugfs_name = "crtc1_regs", 908 .fifo_depth = 64, 909 .pixels_per_clock = 1, 910 .encoder_types = { 911 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, 912 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI, 913 }, 914 }; 915 916 static const struct vc4_pv_data bcm2835_pv2_data = { 917 .base = { 918 .hvs_available_channels = BIT(1), 919 .hvs_output = 1, 920 }, 921 .debugfs_name = "crtc2_regs", 922 .fifo_depth = 64, 923 .pixels_per_clock = 1, 924 .encoder_types = { 925 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0, 926 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, 927 }, 928 }; 929 930 static const struct vc4_pv_data bcm2711_pv0_data = { 931 .base = { 932 .hvs_available_channels = BIT(0), 933 .hvs_output = 0, 934 }, 935 .debugfs_name = "crtc0_regs", 936 .fifo_depth = 64, 937 .pixels_per_clock = 1, 938 .encoder_types = { 939 [0] = VC4_ENCODER_TYPE_DSI0, 940 [1] = VC4_ENCODER_TYPE_DPI, 941 }, 942 }; 943 944 static const struct vc4_pv_data bcm2711_pv1_data = { 945 .base = { 946 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 947 .hvs_output = 3, 948 }, 949 .debugfs_name = "crtc1_regs", 950 .fifo_depth = 64, 951 .pixels_per_clock = 1, 952 .encoder_types = { 953 [0] = VC4_ENCODER_TYPE_DSI1, 954 [1] = VC4_ENCODER_TYPE_SMI, 955 }, 956 }; 957 958 static const struct vc4_pv_data bcm2711_pv2_data = { 959 .base = { 960 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 961 .hvs_output = 4, 962 }, 963 .debugfs_name = "crtc2_regs", 964 .fifo_depth = 256, 965 .pixels_per_clock = 2, 966 .encoder_types = { 967 [0] = VC4_ENCODER_TYPE_HDMI0, 968 }, 969 }; 970 971 static const struct vc4_pv_data bcm2711_pv3_data = { 972 .base = { 973 .hvs_available_channels = BIT(1), 974 .hvs_output = 1, 975 }, 976 .debugfs_name = "crtc3_regs", 977 .fifo_depth = 64, 978 .pixels_per_clock = 1, 979 .encoder_types = { 980 [0] = VC4_ENCODER_TYPE_VEC, 981 }, 982 }; 983 984 static const struct vc4_pv_data bcm2711_pv4_data = { 985 .base = { 986 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 987 .hvs_output = 5, 988 }, 989 .debugfs_name = "crtc4_regs", 990 .fifo_depth = 64, 991 .pixels_per_clock = 2, 992 .encoder_types = { 993 [0] = VC4_ENCODER_TYPE_HDMI1, 994 }, 995 }; 996 997 static const struct of_device_id vc4_crtc_dt_match[] = { 998 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data }, 999 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data }, 1000 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data }, 1001 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data }, 1002 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data }, 1003 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data }, 1004 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data }, 1005 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data }, 1006 {} 1007 }; 1008 1009 static void vc4_set_crtc_possible_masks(struct drm_device *drm, 1010 struct drm_crtc *crtc) 1011 { 1012 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 1013 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 1014 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types; 1015 struct drm_encoder *encoder; 1016 1017 drm_for_each_encoder(encoder, drm) { 1018 struct vc4_encoder *vc4_encoder; 1019 int i; 1020 1021 vc4_encoder = to_vc4_encoder(encoder); 1022 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) { 1023 if (vc4_encoder->type == encoder_types[i]) { 1024 vc4_encoder->clock_select = i; 1025 encoder->possible_crtcs |= drm_crtc_mask(crtc); 1026 break; 1027 } 1028 } 1029 } 1030 } 1031 1032 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, 1033 const struct drm_crtc_funcs *crtc_funcs, 1034 const struct drm_crtc_helper_funcs *crtc_helper_funcs) 1035 { 1036 struct vc4_dev *vc4 = to_vc4_dev(drm); 1037 struct drm_crtc *crtc = &vc4_crtc->base; 1038 struct drm_plane *primary_plane; 1039 unsigned int i; 1040 1041 /* For now, we create just the primary and the legacy cursor 1042 * planes. We should be able to stack more planes on easily, 1043 * but to do that we would need to compute the bandwidth 1044 * requirement of the plane configuration, and reject ones 1045 * that will take too much. 1046 */ 1047 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); 1048 if (IS_ERR(primary_plane)) { 1049 dev_err(drm->dev, "failed to construct primary plane\n"); 1050 return PTR_ERR(primary_plane); 1051 } 1052 1053 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, 1054 crtc_funcs, NULL); 1055 drm_crtc_helper_add(crtc, crtc_helper_funcs); 1056 1057 if (!vc4->hvs->hvs5) { 1058 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); 1059 1060 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); 1061 1062 /* We support CTM, but only for one CRTC at a time. It's therefore 1063 * implemented as private driver state in vc4_kms, not here. 1064 */ 1065 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); 1066 } 1067 1068 for (i = 0; i < crtc->gamma_size; i++) { 1069 vc4_crtc->lut_r[i] = i; 1070 vc4_crtc->lut_g[i] = i; 1071 vc4_crtc->lut_b[i] = i; 1072 } 1073 1074 return 0; 1075 } 1076 1077 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) 1078 { 1079 struct platform_device *pdev = to_platform_device(dev); 1080 struct drm_device *drm = dev_get_drvdata(master); 1081 const struct vc4_pv_data *pv_data; 1082 struct vc4_crtc *vc4_crtc; 1083 struct drm_crtc *crtc; 1084 struct drm_plane *destroy_plane, *temp; 1085 int ret; 1086 1087 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL); 1088 if (!vc4_crtc) 1089 return -ENOMEM; 1090 crtc = &vc4_crtc->base; 1091 1092 pv_data = of_device_get_match_data(dev); 1093 if (!pv_data) 1094 return -ENODEV; 1095 vc4_crtc->data = &pv_data->base; 1096 vc4_crtc->pdev = pdev; 1097 1098 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); 1099 if (IS_ERR(vc4_crtc->regs)) 1100 return PTR_ERR(vc4_crtc->regs); 1101 1102 vc4_crtc->regset.base = vc4_crtc->regs; 1103 vc4_crtc->regset.regs = crtc_regs; 1104 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs); 1105 1106 ret = vc4_crtc_init(drm, vc4_crtc, 1107 &vc4_crtc_funcs, &vc4_crtc_helper_funcs); 1108 if (ret) 1109 return ret; 1110 vc4_set_crtc_possible_masks(drm, crtc); 1111 1112 CRTC_WRITE(PV_INTEN, 0); 1113 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); 1114 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 1115 vc4_crtc_irq_handler, 1116 IRQF_SHARED, 1117 "vc4 crtc", vc4_crtc); 1118 if (ret) 1119 goto err_destroy_planes; 1120 1121 platform_set_drvdata(pdev, vc4_crtc); 1122 1123 vc4_debugfs_add_regset32(drm, pv_data->debugfs_name, 1124 &vc4_crtc->regset); 1125 1126 return 0; 1127 1128 err_destroy_planes: 1129 list_for_each_entry_safe(destroy_plane, temp, 1130 &drm->mode_config.plane_list, head) { 1131 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc)) 1132 destroy_plane->funcs->destroy(destroy_plane); 1133 } 1134 1135 return ret; 1136 } 1137 1138 static void vc4_crtc_unbind(struct device *dev, struct device *master, 1139 void *data) 1140 { 1141 struct platform_device *pdev = to_platform_device(dev); 1142 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev); 1143 1144 vc4_crtc_destroy(&vc4_crtc->base); 1145 1146 CRTC_WRITE(PV_INTEN, 0); 1147 1148 platform_set_drvdata(pdev, NULL); 1149 } 1150 1151 static const struct component_ops vc4_crtc_ops = { 1152 .bind = vc4_crtc_bind, 1153 .unbind = vc4_crtc_unbind, 1154 }; 1155 1156 static int vc4_crtc_dev_probe(struct platform_device *pdev) 1157 { 1158 return component_add(&pdev->dev, &vc4_crtc_ops); 1159 } 1160 1161 static int vc4_crtc_dev_remove(struct platform_device *pdev) 1162 { 1163 component_del(&pdev->dev, &vc4_crtc_ops); 1164 return 0; 1165 } 1166 1167 struct platform_driver vc4_crtc_driver = { 1168 .probe = vc4_crtc_dev_probe, 1169 .remove = vc4_crtc_dev_remove, 1170 .driver = { 1171 .name = "vc4_crtc", 1172 .of_match_table = vc4_crtc_dt_match, 1173 }, 1174 }; 1175