1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D scheduling 6 * 7 * The shared DRM GPU scheduler is used to coordinate submitting jobs 8 * to the hardware. Each DRM fd (roughly a client process) gets its 9 * own scheduler entity, which will process jobs in order. The GPU 10 * scheduler will schedule the clients with a FIFO scheduling algorithm. 11 * 12 * For simplicity, and in order to keep latency low for interactive 13 * jobs when bulk background jobs are queued up, we submit a new job 14 * to the HW only when it has completed the last one, instead of 15 * filling up the CT[01]Q FIFOs with jobs. Similarly, we use 16 * `drm_sched_job_add_dependency()` to manage the dependency between bin 17 * and render, instead of having the clients submit jobs using the HW's 18 * semaphores to interlock between them. 19 */ 20 21 #include <linux/sched/clock.h> 22 #include <linux/kthread.h> 23 24 #include <drm/drm_print.h> 25 #include <drm/drm_syncobj.h> 26 27 #include "v3d_drv.h" 28 #include "v3d_regs.h" 29 #include "v3d_trace.h" 30 31 #define V3D_CSD_CFG012_WG_COUNT_SHIFT 16 32 33 static struct v3d_job * 34 to_v3d_job(struct drm_sched_job *sched_job) 35 { 36 return container_of(sched_job, struct v3d_job, base); 37 } 38 39 static struct v3d_bin_job * 40 to_bin_job(struct drm_sched_job *sched_job) 41 { 42 return container_of(sched_job, struct v3d_bin_job, base.base); 43 } 44 45 static struct v3d_render_job * 46 to_render_job(struct drm_sched_job *sched_job) 47 { 48 return container_of(sched_job, struct v3d_render_job, base.base); 49 } 50 51 static struct v3d_tfu_job * 52 to_tfu_job(struct drm_sched_job *sched_job) 53 { 54 return container_of(sched_job, struct v3d_tfu_job, base.base); 55 } 56 57 static struct v3d_csd_job * 58 to_csd_job(struct drm_sched_job *sched_job) 59 { 60 return container_of(sched_job, struct v3d_csd_job, base.base); 61 } 62 63 static struct v3d_cpu_job * 64 to_cpu_job(struct drm_sched_job *sched_job) 65 { 66 return container_of(sched_job, struct v3d_cpu_job, base.base); 67 } 68 69 void v3d_stats_release(struct kref *refcount) 70 { 71 struct v3d_stats *stats = container_of(refcount, typeof(*stats), refcount); 72 73 kfree(stats); 74 } 75 76 struct v3d_stats *v3d_stats_alloc(void) 77 { 78 struct v3d_stats *stats; 79 80 stats = kzalloc_obj(*stats); 81 if (!stats) 82 return NULL; 83 84 kref_init(&stats->refcount); 85 seqcount_init(&stats->lock); 86 87 return stats; 88 } 89 90 static void 91 v3d_sched_job_free(struct drm_sched_job *sched_job) 92 { 93 struct v3d_job *job = to_v3d_job(sched_job); 94 95 v3d_job_cleanup(job); 96 } 97 98 void 99 v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info, 100 unsigned int count) 101 { 102 if (query_info->queries) { 103 unsigned int i; 104 105 for (i = 0; i < count; i++) 106 drm_syncobj_put(query_info->queries[i].syncobj); 107 108 kvfree(query_info->queries); 109 } 110 } 111 112 void 113 v3d_performance_query_info_free(struct v3d_performance_query_info *query_info, 114 unsigned int count) 115 { 116 if (query_info->queries) { 117 unsigned int i; 118 119 for (i = 0; i < count; i++) { 120 drm_syncobj_put(query_info->queries[i].syncobj); 121 kvfree(query_info->queries[i].kperfmon_ids); 122 } 123 124 kvfree(query_info->queries); 125 } 126 } 127 128 static void 129 v3d_switch_perfmon(struct v3d_dev *v3d, struct v3d_job *job) 130 { 131 struct v3d_perfmon *perfmon = v3d->global_perfmon; 132 133 if (!perfmon) 134 perfmon = job->perfmon; 135 136 if (perfmon == v3d->active_perfmon) 137 return; 138 139 if (perfmon != v3d->active_perfmon) 140 v3d_perfmon_stop(v3d, v3d->active_perfmon, true); 141 142 if (perfmon && v3d->active_perfmon != perfmon) 143 v3d_perfmon_start(v3d, perfmon); 144 } 145 146 static void 147 v3d_stats_start(struct v3d_stats *stats, u64 now) 148 { 149 raw_write_seqcount_begin(&stats->lock); 150 stats->start_ns = now; 151 raw_write_seqcount_end(&stats->lock); 152 } 153 154 static void 155 v3d_job_start_stats(struct v3d_job *job) 156 { 157 u64 now = local_clock(); 158 159 preempt_disable(); 160 v3d_stats_start(job->client_stats, now); 161 v3d_stats_start(job->global_stats, now); 162 preempt_enable(); 163 } 164 165 static void 166 v3d_stats_update(struct v3d_stats *stats, u64 now) 167 { 168 raw_write_seqcount_begin(&stats->lock); 169 stats->enabled_ns += now - stats->start_ns; 170 stats->jobs_completed++; 171 stats->start_ns = 0; 172 raw_write_seqcount_end(&stats->lock); 173 } 174 175 void 176 v3d_job_update_stats(struct v3d_job *job) 177 { 178 u64 now = local_clock(); 179 180 preempt_disable(); 181 v3d_stats_update(job->client_stats, now); 182 v3d_stats_update(job->global_stats, now); 183 preempt_enable(); 184 } 185 186 static struct dma_fence *v3d_bin_job_run(struct drm_sched_job *sched_job) 187 { 188 struct v3d_bin_job *job = to_bin_job(sched_job); 189 struct v3d_dev *v3d = job->base.v3d; 190 struct v3d_queue_state *queue = &v3d->queue[V3D_BIN]; 191 struct drm_device *dev = &v3d->drm; 192 struct dma_fence *fence; 193 unsigned long irqflags; 194 195 if (unlikely(job->base.base.s_fence->finished.error)) { 196 spin_lock_irqsave(&queue->queue_lock, irqflags); 197 queue->active_job = NULL; 198 spin_unlock_irqrestore(&queue->queue_lock, irqflags); 199 return NULL; 200 } 201 202 /* Lock required around bin_job update vs 203 * v3d_overflow_mem_work(). 204 */ 205 spin_lock_irqsave(&queue->queue_lock, irqflags); 206 queue->active_job = &job->base; 207 /* Clear out the overflow allocation, so we don't 208 * reuse the overflow attached to a previous job. 209 */ 210 V3D_CORE_WRITE(0, V3D_PTB_BPOS, 0); 211 spin_unlock_irqrestore(&queue->queue_lock, irqflags); 212 213 v3d_invalidate_caches(v3d); 214 215 fence = v3d_fence_create(v3d, V3D_BIN); 216 if (IS_ERR(fence)) 217 return NULL; 218 219 if (job->base.irq_fence) 220 dma_fence_put(job->base.irq_fence); 221 job->base.irq_fence = dma_fence_get(fence); 222 223 trace_v3d_submit_cl(dev, false, to_v3d_fence(fence)->seqno, 224 job->start, job->end); 225 226 v3d_job_start_stats(&job->base); 227 v3d_switch_perfmon(v3d, &job->base); 228 229 /* Set the current and end address of the control list. 230 * Writing the end register is what starts the job. 231 */ 232 if (job->qma) { 233 V3D_CORE_WRITE(0, V3D_CLE_CT0QMA, job->qma); 234 V3D_CORE_WRITE(0, V3D_CLE_CT0QMS, job->qms); 235 } 236 if (job->qts) { 237 V3D_CORE_WRITE(0, V3D_CLE_CT0QTS, 238 V3D_CLE_CT0QTS_ENABLE | 239 job->qts); 240 } 241 V3D_CORE_WRITE(0, V3D_CLE_CT0QBA, job->start); 242 V3D_CORE_WRITE(0, V3D_CLE_CT0QEA, job->end); 243 244 return fence; 245 } 246 247 static struct dma_fence *v3d_render_job_run(struct drm_sched_job *sched_job) 248 { 249 struct v3d_render_job *job = to_render_job(sched_job); 250 struct v3d_dev *v3d = job->base.v3d; 251 struct drm_device *dev = &v3d->drm; 252 struct dma_fence *fence; 253 254 if (unlikely(job->base.base.s_fence->finished.error)) { 255 v3d->queue[V3D_RENDER].active_job = NULL; 256 return NULL; 257 } 258 259 v3d->queue[V3D_RENDER].active_job = &job->base; 260 261 /* Can we avoid this flush? We need to be careful of 262 * scheduling, though -- imagine job0 rendering to texture and 263 * job1 reading, and them being executed as bin0, bin1, 264 * render0, render1, so that render1's flush at bin time 265 * wasn't enough. 266 */ 267 v3d_invalidate_caches(v3d); 268 269 fence = v3d_fence_create(v3d, V3D_RENDER); 270 if (IS_ERR(fence)) 271 return NULL; 272 273 if (job->base.irq_fence) 274 dma_fence_put(job->base.irq_fence); 275 job->base.irq_fence = dma_fence_get(fence); 276 277 trace_v3d_submit_cl(dev, true, to_v3d_fence(fence)->seqno, 278 job->start, job->end); 279 280 v3d_job_start_stats(&job->base); 281 v3d_switch_perfmon(v3d, &job->base); 282 283 /* XXX: Set the QCFG */ 284 285 /* Set the current and end address of the control list. 286 * Writing the end register is what starts the job. 287 */ 288 V3D_CORE_WRITE(0, V3D_CLE_CT1QBA, job->start); 289 V3D_CORE_WRITE(0, V3D_CLE_CT1QEA, job->end); 290 291 return fence; 292 } 293 294 static struct dma_fence * 295 v3d_tfu_job_run(struct drm_sched_job *sched_job) 296 { 297 struct v3d_tfu_job *job = to_tfu_job(sched_job); 298 struct v3d_dev *v3d = job->base.v3d; 299 struct drm_device *dev = &v3d->drm; 300 struct dma_fence *fence; 301 302 if (unlikely(job->base.base.s_fence->finished.error)) { 303 v3d->queue[V3D_TFU].active_job = NULL; 304 return NULL; 305 } 306 307 v3d->queue[V3D_TFU].active_job = &job->base; 308 309 fence = v3d_fence_create(v3d, V3D_TFU); 310 if (IS_ERR(fence)) 311 return NULL; 312 313 if (job->base.irq_fence) 314 dma_fence_put(job->base.irq_fence); 315 job->base.irq_fence = dma_fence_get(fence); 316 317 trace_v3d_submit_tfu(dev, to_v3d_fence(fence)->seqno); 318 319 v3d_job_start_stats(&job->base); 320 321 V3D_WRITE(V3D_TFU_IIA(v3d->ver), job->args.iia); 322 V3D_WRITE(V3D_TFU_IIS(v3d->ver), job->args.iis); 323 V3D_WRITE(V3D_TFU_ICA(v3d->ver), job->args.ica); 324 V3D_WRITE(V3D_TFU_IUA(v3d->ver), job->args.iua); 325 V3D_WRITE(V3D_TFU_IOA(v3d->ver), job->args.ioa); 326 if (v3d->ver >= V3D_GEN_71) 327 V3D_WRITE(V3D_V7_TFU_IOC, job->args.v71.ioc); 328 V3D_WRITE(V3D_TFU_IOS(v3d->ver), job->args.ios); 329 V3D_WRITE(V3D_TFU_COEF0(v3d->ver), job->args.coef[0]); 330 if (v3d->ver >= V3D_GEN_71 || (job->args.coef[0] & V3D_TFU_COEF0_USECOEF)) { 331 V3D_WRITE(V3D_TFU_COEF1(v3d->ver), job->args.coef[1]); 332 V3D_WRITE(V3D_TFU_COEF2(v3d->ver), job->args.coef[2]); 333 V3D_WRITE(V3D_TFU_COEF3(v3d->ver), job->args.coef[3]); 334 } 335 /* ICFG kicks off the job. */ 336 V3D_WRITE(V3D_TFU_ICFG(v3d->ver), job->args.icfg | V3D_TFU_ICFG_IOC); 337 338 return fence; 339 } 340 341 static struct dma_fence * 342 v3d_csd_job_run(struct drm_sched_job *sched_job) 343 { 344 struct v3d_csd_job *job = to_csd_job(sched_job); 345 struct v3d_dev *v3d = job->base.v3d; 346 struct drm_device *dev = &v3d->drm; 347 struct dma_fence *fence; 348 int i, csd_cfg0_reg; 349 350 if (unlikely(job->base.base.s_fence->finished.error)) { 351 v3d->queue[V3D_CSD].active_job = NULL; 352 return NULL; 353 } 354 355 v3d->queue[V3D_CSD].active_job = &job->base; 356 357 v3d_invalidate_caches(v3d); 358 359 fence = v3d_fence_create(v3d, V3D_CSD); 360 if (IS_ERR(fence)) 361 return NULL; 362 363 if (job->base.irq_fence) 364 dma_fence_put(job->base.irq_fence); 365 job->base.irq_fence = dma_fence_get(fence); 366 367 trace_v3d_submit_csd(dev, to_v3d_fence(fence)->seqno); 368 369 v3d_job_start_stats(&job->base); 370 v3d_switch_perfmon(v3d, &job->base); 371 372 csd_cfg0_reg = V3D_CSD_QUEUED_CFG0(v3d->ver); 373 for (i = 1; i <= 6; i++) 374 V3D_CORE_WRITE(0, csd_cfg0_reg + 4 * i, job->args.cfg[i]); 375 376 /* Although V3D 7.1 has an eighth configuration register, we are not 377 * using it. Therefore, make sure it remains unused. 378 * 379 * XXX: Set the CFG7 register 380 */ 381 if (v3d->ver >= V3D_GEN_71) 382 V3D_CORE_WRITE(0, V3D_V7_CSD_QUEUED_CFG7, 0); 383 384 /* CFG0 write kicks off the job. */ 385 V3D_CORE_WRITE(0, csd_cfg0_reg, job->args.cfg[0]); 386 387 return fence; 388 } 389 390 static void 391 v3d_rewrite_csd_job_wg_counts_from_indirect(struct v3d_cpu_job *job) 392 { 393 struct v3d_indirect_csd_info *indirect_csd = &job->indirect_csd; 394 struct v3d_bo *bo = to_v3d_bo(job->base.bo[0]); 395 struct v3d_bo *indirect = to_v3d_bo(indirect_csd->indirect); 396 struct drm_v3d_submit_csd *args = &indirect_csd->job->args; 397 struct v3d_dev *v3d = job->base.v3d; 398 u32 num_batches, *wg_counts; 399 400 v3d_get_bo_vaddr(bo); 401 v3d_get_bo_vaddr(indirect); 402 403 wg_counts = (uint32_t *)(bo->vaddr + indirect_csd->offset); 404 405 if (wg_counts[0] == 0 || wg_counts[1] == 0 || wg_counts[2] == 0) 406 return; 407 408 args->cfg[0] = wg_counts[0] << V3D_CSD_CFG012_WG_COUNT_SHIFT; 409 args->cfg[1] = wg_counts[1] << V3D_CSD_CFG012_WG_COUNT_SHIFT; 410 args->cfg[2] = wg_counts[2] << V3D_CSD_CFG012_WG_COUNT_SHIFT; 411 412 num_batches = DIV_ROUND_UP(indirect_csd->wg_size, 16) * 413 (wg_counts[0] * wg_counts[1] * wg_counts[2]); 414 415 /* V3D 7.1.6 and later don't subtract 1 from the number of batches */ 416 if (v3d->ver < 71 || (v3d->ver == 71 && v3d->rev < 6)) 417 args->cfg[4] = num_batches - 1; 418 else 419 args->cfg[4] = num_batches; 420 421 WARN_ON(args->cfg[4] == ~0); 422 423 for (int i = 0; i < 3; i++) { 424 /* 0xffffffff indicates that the uniform rewrite is not needed */ 425 if (indirect_csd->wg_uniform_offsets[i] != 0xffffffff) { 426 u32 uniform_idx = indirect_csd->wg_uniform_offsets[i]; 427 ((uint32_t *)indirect->vaddr)[uniform_idx] = wg_counts[i]; 428 } 429 } 430 431 v3d_put_bo_vaddr(indirect); 432 v3d_put_bo_vaddr(bo); 433 } 434 435 static void 436 v3d_timestamp_query(struct v3d_cpu_job *job) 437 { 438 struct v3d_timestamp_query_info *timestamp_query = &job->timestamp_query; 439 struct v3d_bo *bo = to_v3d_bo(job->base.bo[0]); 440 u8 *value_addr; 441 442 v3d_get_bo_vaddr(bo); 443 444 for (int i = 0; i < timestamp_query->count; i++) { 445 value_addr = ((u8 *)bo->vaddr) + timestamp_query->queries[i].offset; 446 *((u64 *)value_addr) = i == 0 ? ktime_get_ns() : 0ull; 447 448 drm_syncobj_replace_fence(timestamp_query->queries[i].syncobj, 449 job->base.done_fence); 450 } 451 452 v3d_put_bo_vaddr(bo); 453 } 454 455 static void 456 v3d_reset_timestamp_queries(struct v3d_cpu_job *job) 457 { 458 struct v3d_timestamp_query_info *timestamp_query = &job->timestamp_query; 459 struct v3d_timestamp_query *queries = timestamp_query->queries; 460 struct v3d_bo *bo = to_v3d_bo(job->base.bo[0]); 461 u8 *value_addr; 462 463 v3d_get_bo_vaddr(bo); 464 465 for (int i = 0; i < timestamp_query->count; i++) { 466 value_addr = ((u8 *)bo->vaddr) + queries[i].offset; 467 *((u64 *)value_addr) = 0; 468 469 drm_syncobj_replace_fence(queries[i].syncobj, NULL); 470 } 471 472 v3d_put_bo_vaddr(bo); 473 } 474 475 static void write_to_buffer_32(u32 *dst, unsigned int idx, u32 value) 476 { 477 dst[idx] = value; 478 } 479 480 static void write_to_buffer_64(u64 *dst, unsigned int idx, u64 value) 481 { 482 dst[idx] = value; 483 } 484 485 static void 486 write_to_buffer(void *dst, unsigned int idx, bool do_64bit, u64 value) 487 { 488 if (do_64bit) 489 write_to_buffer_64(dst, idx, value); 490 else 491 write_to_buffer_32(dst, idx, value); 492 } 493 494 static void 495 v3d_copy_query_results(struct v3d_cpu_job *job) 496 { 497 struct v3d_timestamp_query_info *timestamp_query = &job->timestamp_query; 498 struct v3d_timestamp_query *queries = timestamp_query->queries; 499 struct v3d_bo *bo = to_v3d_bo(job->base.bo[0]); 500 struct v3d_bo *timestamp = to_v3d_bo(job->base.bo[1]); 501 struct v3d_copy_query_results_info *copy = &job->copy; 502 struct dma_fence *fence; 503 u8 *query_addr; 504 bool available, write_result; 505 u8 *data; 506 int i; 507 508 v3d_get_bo_vaddr(bo); 509 v3d_get_bo_vaddr(timestamp); 510 511 data = ((u8 *)bo->vaddr) + copy->offset; 512 513 for (i = 0; i < timestamp_query->count; i++) { 514 fence = drm_syncobj_fence_get(queries[i].syncobj); 515 available = fence ? dma_fence_is_signaled(fence) : false; 516 517 write_result = available || copy->do_partial; 518 if (write_result) { 519 query_addr = ((u8 *)timestamp->vaddr) + queries[i].offset; 520 write_to_buffer(data, 0, copy->do_64bit, *((u64 *)query_addr)); 521 } 522 523 if (copy->availability_bit) 524 write_to_buffer(data, 1, copy->do_64bit, available ? 1u : 0u); 525 526 data += copy->stride; 527 528 dma_fence_put(fence); 529 } 530 531 v3d_put_bo_vaddr(timestamp); 532 v3d_put_bo_vaddr(bo); 533 } 534 535 static void 536 v3d_reset_performance_queries(struct v3d_cpu_job *job) 537 { 538 struct v3d_performance_query_info *performance_query = &job->performance_query; 539 struct v3d_file_priv *v3d_priv = job->base.file_priv; 540 struct v3d_dev *v3d = job->base.v3d; 541 struct v3d_perfmon *perfmon; 542 543 for (int i = 0; i < performance_query->count; i++) { 544 for (int j = 0; j < performance_query->nperfmons; j++) { 545 perfmon = v3d_perfmon_find(v3d_priv, 546 performance_query->queries[i].kperfmon_ids[j]); 547 if (!perfmon) { 548 drm_dbg(&v3d->drm, "Failed to find perfmon."); 549 continue; 550 } 551 552 v3d_perfmon_stop(v3d, perfmon, false); 553 554 memset(perfmon->values, 0, perfmon->ncounters * sizeof(u64)); 555 556 v3d_perfmon_put(perfmon); 557 } 558 559 drm_syncobj_replace_fence(performance_query->queries[i].syncobj, NULL); 560 } 561 } 562 563 static void 564 v3d_write_performance_query_result(struct v3d_cpu_job *job, void *data, 565 unsigned int query) 566 { 567 struct v3d_performance_query_info *performance_query = 568 &job->performance_query; 569 struct v3d_file_priv *v3d_priv = job->base.file_priv; 570 struct v3d_performance_query *perf_query = 571 &performance_query->queries[query]; 572 struct v3d_dev *v3d = job->base.v3d; 573 unsigned int i, j, offset; 574 575 for (i = 0, offset = 0; 576 i < performance_query->nperfmons; 577 i++, offset += DRM_V3D_MAX_PERF_COUNTERS) { 578 struct v3d_perfmon *perfmon; 579 580 perfmon = v3d_perfmon_find(v3d_priv, 581 perf_query->kperfmon_ids[i]); 582 if (!perfmon) { 583 drm_dbg(&v3d->drm, "Failed to find perfmon."); 584 continue; 585 } 586 587 v3d_perfmon_stop(v3d, perfmon, true); 588 589 if (job->copy.do_64bit) { 590 for (j = 0; j < perfmon->ncounters; j++) 591 write_to_buffer_64(data, offset + j, 592 perfmon->values[j]); 593 } else { 594 for (j = 0; j < perfmon->ncounters; j++) 595 write_to_buffer_32(data, offset + j, 596 perfmon->values[j]); 597 } 598 599 v3d_perfmon_put(perfmon); 600 } 601 } 602 603 static void 604 v3d_copy_performance_query(struct v3d_cpu_job *job) 605 { 606 struct v3d_performance_query_info *performance_query = &job->performance_query; 607 struct v3d_copy_query_results_info *copy = &job->copy; 608 struct v3d_bo *bo = to_v3d_bo(job->base.bo[0]); 609 struct dma_fence *fence; 610 bool available, write_result; 611 u8 *data; 612 613 v3d_get_bo_vaddr(bo); 614 615 data = ((u8 *)bo->vaddr) + copy->offset; 616 617 for (int i = 0; i < performance_query->count; i++) { 618 fence = drm_syncobj_fence_get(performance_query->queries[i].syncobj); 619 available = fence ? dma_fence_is_signaled(fence) : false; 620 621 write_result = available || copy->do_partial; 622 if (write_result) 623 v3d_write_performance_query_result(job, data, i); 624 625 if (copy->availability_bit) 626 write_to_buffer(data, performance_query->ncounters, 627 copy->do_64bit, available ? 1u : 0u); 628 629 data += copy->stride; 630 631 dma_fence_put(fence); 632 } 633 634 v3d_put_bo_vaddr(bo); 635 } 636 637 static const v3d_cpu_job_fn cpu_job_function[] = { 638 [V3D_CPU_JOB_TYPE_INDIRECT_CSD] = v3d_rewrite_csd_job_wg_counts_from_indirect, 639 [V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY] = v3d_timestamp_query, 640 [V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY] = v3d_reset_timestamp_queries, 641 [V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY] = v3d_copy_query_results, 642 [V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY] = v3d_reset_performance_queries, 643 [V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY] = v3d_copy_performance_query, 644 }; 645 646 static struct dma_fence * 647 v3d_cpu_job_run(struct drm_sched_job *sched_job) 648 { 649 struct v3d_cpu_job *job = to_cpu_job(sched_job); 650 struct v3d_dev *v3d = job->base.v3d; 651 652 if (job->job_type >= ARRAY_SIZE(cpu_job_function)) { 653 drm_dbg(&v3d->drm, "Unknown CPU job: %d\n", job->job_type); 654 return NULL; 655 } 656 657 v3d_job_start_stats(&job->base); 658 trace_v3d_cpu_job_begin(&v3d->drm, job->job_type); 659 660 cpu_job_function[job->job_type](job); 661 662 trace_v3d_cpu_job_end(&v3d->drm, job->job_type); 663 v3d_job_update_stats(&job->base); 664 665 /* Synchronous operation, so no fence to wait on. */ 666 return NULL; 667 } 668 669 static struct dma_fence * 670 v3d_cache_clean_job_run(struct drm_sched_job *sched_job) 671 { 672 struct v3d_job *job = to_v3d_job(sched_job); 673 struct v3d_dev *v3d = job->v3d; 674 675 v3d_job_start_stats(job); 676 677 v3d_clean_caches(v3d); 678 679 v3d_job_update_stats(job); 680 681 /* Synchronous operation, so no fence to wait on. */ 682 return NULL; 683 } 684 685 static enum drm_gpu_sched_stat 686 v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job, 687 enum v3d_queue q) 688 { 689 struct v3d_job *job = to_v3d_job(sched_job); 690 enum v3d_queue i; 691 692 mutex_lock(&v3d->reset_lock); 693 694 /* block scheduler */ 695 for (i = 0; i < V3D_MAX_QUEUES; i++) 696 drm_sched_stop(&v3d->queue[i].sched, sched_job); 697 698 if (sched_job) 699 drm_sched_increase_karma(sched_job); 700 701 /* get the GPU back into the init state */ 702 v3d_reset(v3d); 703 704 atomic_inc(&v3d->reset_counter); 705 atomic_inc(&job->client_stats->reset_counter); 706 707 for (i = 0; i < V3D_MAX_QUEUES; i++) 708 drm_sched_resubmit_jobs(&v3d->queue[i].sched); 709 710 /* Unblock schedulers and restart their jobs. */ 711 for (i = 0; i < V3D_MAX_QUEUES; i++) 712 drm_sched_start(&v3d->queue[i].sched, 0); 713 714 mutex_unlock(&v3d->reset_lock); 715 716 return DRM_GPU_SCHED_STAT_RESET; 717 } 718 719 static enum drm_gpu_sched_stat 720 v3d_cl_job_timedout(struct drm_sched_job *sched_job, enum v3d_queue q, 721 u32 *timedout_ctca, u32 *timedout_ctra) 722 { 723 struct v3d_job *job = to_v3d_job(sched_job); 724 struct v3d_dev *v3d = job->v3d; 725 u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(q)); 726 u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(q)); 727 728 /* If the current address or return address have changed, then the GPU 729 * has probably made progress and we should delay the reset. This 730 * could fail if the GPU got in an infinite loop in the CL, but that 731 * is pretty unlikely outside of an i-g-t testcase. 732 */ 733 if (*timedout_ctca != ctca || *timedout_ctra != ctra) { 734 *timedout_ctca = ctca; 735 *timedout_ctra = ctra; 736 737 return DRM_GPU_SCHED_STAT_NO_HANG; 738 } 739 740 return v3d_gpu_reset_for_timeout(v3d, sched_job, q); 741 } 742 743 static enum drm_gpu_sched_stat 744 v3d_bin_job_timedout(struct drm_sched_job *sched_job) 745 { 746 struct v3d_bin_job *job = to_bin_job(sched_job); 747 748 return v3d_cl_job_timedout(sched_job, V3D_BIN, 749 &job->timedout_ctca, &job->timedout_ctra); 750 } 751 752 static enum drm_gpu_sched_stat 753 v3d_render_job_timedout(struct drm_sched_job *sched_job) 754 { 755 struct v3d_render_job *job = to_render_job(sched_job); 756 757 return v3d_cl_job_timedout(sched_job, V3D_RENDER, 758 &job->timedout_ctca, &job->timedout_ctra); 759 } 760 761 static enum drm_gpu_sched_stat 762 v3d_tfu_job_timedout(struct drm_sched_job *sched_job) 763 { 764 struct v3d_job *job = to_v3d_job(sched_job); 765 766 return v3d_gpu_reset_for_timeout(job->v3d, sched_job, V3D_TFU); 767 } 768 769 static enum drm_gpu_sched_stat 770 v3d_csd_job_timedout(struct drm_sched_job *sched_job) 771 { 772 struct v3d_csd_job *job = to_csd_job(sched_job); 773 struct v3d_dev *v3d = job->base.v3d; 774 u32 batches = V3D_CORE_READ(0, V3D_CSD_CURRENT_CFG4(v3d->ver)); 775 776 /* If we've made progress, skip reset, add the job to the pending 777 * list, and let the timer get rearmed. 778 */ 779 if (job->timedout_batches != batches) { 780 job->timedout_batches = batches; 781 782 return DRM_GPU_SCHED_STAT_NO_HANG; 783 } 784 785 return v3d_gpu_reset_for_timeout(v3d, sched_job, V3D_CSD); 786 } 787 788 static const struct drm_sched_backend_ops v3d_bin_sched_ops = { 789 .run_job = v3d_bin_job_run, 790 .timedout_job = v3d_bin_job_timedout, 791 .free_job = v3d_sched_job_free, 792 }; 793 794 static const struct drm_sched_backend_ops v3d_render_sched_ops = { 795 .run_job = v3d_render_job_run, 796 .timedout_job = v3d_render_job_timedout, 797 .free_job = v3d_sched_job_free, 798 }; 799 800 static const struct drm_sched_backend_ops v3d_tfu_sched_ops = { 801 .run_job = v3d_tfu_job_run, 802 .timedout_job = v3d_tfu_job_timedout, 803 .free_job = v3d_sched_job_free, 804 }; 805 806 static const struct drm_sched_backend_ops v3d_csd_sched_ops = { 807 .run_job = v3d_csd_job_run, 808 .timedout_job = v3d_csd_job_timedout, 809 .free_job = v3d_sched_job_free 810 }; 811 812 static const struct drm_sched_backend_ops v3d_cache_clean_sched_ops = { 813 .run_job = v3d_cache_clean_job_run, 814 .free_job = v3d_sched_job_free 815 }; 816 817 static const struct drm_sched_backend_ops v3d_cpu_sched_ops = { 818 .run_job = v3d_cpu_job_run, 819 .free_job = v3d_sched_job_free 820 }; 821 822 static int 823 v3d_queue_sched_init(struct v3d_dev *v3d, const struct drm_sched_backend_ops *ops, 824 enum v3d_queue queue, const char *name) 825 { 826 struct drm_sched_init_args args = { 827 .num_rqs = DRM_SCHED_PRIORITY_COUNT, 828 .credit_limit = 1, 829 .timeout = msecs_to_jiffies(500), 830 .dev = v3d->drm.dev, 831 }; 832 833 args.ops = ops; 834 args.name = name; 835 836 return drm_sched_init(&v3d->queue[queue].sched, &args); 837 } 838 839 int 840 v3d_sched_init(struct v3d_dev *v3d) 841 { 842 int ret; 843 844 ret = v3d_queue_sched_init(v3d, &v3d_bin_sched_ops, V3D_BIN, "v3d_bin"); 845 if (ret) 846 return ret; 847 848 ret = v3d_queue_sched_init(v3d, &v3d_render_sched_ops, V3D_RENDER, 849 "v3d_render"); 850 if (ret) 851 goto fail; 852 853 ret = v3d_queue_sched_init(v3d, &v3d_tfu_sched_ops, V3D_TFU, "v3d_tfu"); 854 if (ret) 855 goto fail; 856 857 if (v3d_has_csd(v3d)) { 858 ret = v3d_queue_sched_init(v3d, &v3d_csd_sched_ops, V3D_CSD, 859 "v3d_csd"); 860 if (ret) 861 goto fail; 862 863 ret = v3d_queue_sched_init(v3d, &v3d_cache_clean_sched_ops, 864 V3D_CACHE_CLEAN, "v3d_cache_clean"); 865 if (ret) 866 goto fail; 867 } 868 869 ret = v3d_queue_sched_init(v3d, &v3d_cpu_sched_ops, V3D_CPU, "v3d_cpu"); 870 if (ret) 871 goto fail; 872 873 return 0; 874 875 fail: 876 v3d_sched_fini(v3d); 877 return ret; 878 } 879 880 void 881 v3d_sched_fini(struct v3d_dev *v3d) 882 { 883 enum v3d_queue q; 884 885 for (q = 0; q < V3D_MAX_QUEUES; q++) { 886 if (v3d->queue[q].sched.ready) 887 drm_sched_fini(&v3d->queue[q].sched); 888 } 889 } 890