1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2021 Raspberry Pi 4 */ 5 6 #include "v3d_drv.h" 7 #include "v3d_regs.h" 8 9 static const struct v3d_perf_counter_desc v3d_v42_performance_counters[] = { 10 {"FEP", "FEP-valid-primitives-no-rendered-pixels", "[FEP] Valid primitives that result in no rendered pixels, for all rendered tiles"}, 11 {"FEP", "FEP-valid-primitives-rendered-pixels", "[FEP] Valid primitives for all rendered tiles (primitives may be counted in more than one tile)"}, 12 {"FEP", "FEP-clipped-quads", "[FEP] Early-Z/Near/Far clipped quads"}, 13 {"FEP", "FEP-valid-quads", "[FEP] Valid quads"}, 14 {"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test"}, 15 {"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and stencil tests"}, 16 {"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and stencil tests"}, 17 {"TLB", "TLB-quads-with-zero-coverage", "[TLB] Quads with all pixels having zero coverage"}, 18 {"TLB", "TLB-quads-with-non-zero-coverage", "[TLB] Quads with any pixels having non-zero coverage"}, 19 {"TLB", "TLB-quads-written-to-color-buffer", "[TLB] Quads with valid pixels written to colour buffer"}, 20 {"PTB", "PTB-primitives-discarded-outside-viewport", "[PTB] Primitives discarded by being outside the viewport"}, 21 {"PTB", "PTB-primitives-need-clipping", "[PTB] Primitives that need clipping"}, 22 {"PTB", "PTB-primitives-discarded-reversed", "[PTB] Primitives that are discarded because they are reversed"}, 23 {"QPU", "QPU-total-idle-clk-cycles", "[QPU] Total idle clock cycles for all QPUs"}, 24 {"QPU", "QPU-total-active-clk-cycles-vertex-coord-shading", "[QPU] Total active clock cycles for all QPUs doing vertex/coordinate/user shading (counts only when QPU is not stalled)"}, 25 {"QPU", "QPU-total-active-clk-cycles-fragment-shading", "[QPU] Total active clock cycles for all QPUs doing fragment shading (counts only when QPU is not stalled)"}, 26 {"QPU", "QPU-total-clk-cycles-executing-valid-instr", "[QPU] Total clock cycles for all QPUs executing valid instructions"}, 27 {"QPU", "QPU-total-clk-cycles-waiting-TMU", "[QPU] Total clock cycles for all QPUs stalled waiting for TMUs only (counter won't increment if QPU also stalling for another reason)"}, 28 {"QPU", "QPU-total-clk-cycles-waiting-scoreboard", "[QPU] Total clock cycles for all QPUs stalled waiting for Scoreboard only (counter won't increment if QPU also stalling for another reason)"}, 29 {"QPU", "QPU-total-clk-cycles-waiting-varyings", "[QPU] Total clock cycles for all QPUs stalled waiting for Varyings only (counter won't increment if QPU also stalling for another reason)"}, 30 {"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"}, 31 {"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"}, 32 {"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"}, 33 {"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"}, 34 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"}, 35 {"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from memory/L2cache)"}, 36 {"VPM", "VPM-total-clk-cycles-VDW-stalled", "[VPM] Total clock cycles VDW is stalled waiting for VPM access"}, 37 {"VPM", "VPM-total-clk-cycles-VCD-stalled", "[VPM] Total clock cycles VCD is stalled waiting for VPM access"}, 38 {"CLE", "CLE-bin-thread-active-cycles", "[CLE] Bin thread active cycles"}, 39 {"CLE", "CLE-render-thread-active-cycles", "[CLE] Render thread active cycles"}, 40 {"L2T", "L2T-total-cache-hit", "[L2T] Total Level 2 cache hits"}, 41 {"L2T", "L2T-total-cache-miss", "[L2T] Total Level 2 cache misses"}, 42 {"CORE", "cycle-count", "[CORE] Cycle counter"}, 43 {"QPU", "QPU-total-clk-cycles-waiting-vertex-coord-shading", "[QPU] Total stalled clock cycles for all QPUs doing vertex/coordinate/user shading"}, 44 {"QPU", "QPU-total-clk-cycles-waiting-fragment-shading", "[QPU] Total stalled clock cycles for all QPUs doing fragment shading"}, 45 {"PTB", "PTB-primitives-binned", "[PTB] Total primitives binned"}, 46 {"AXI", "AXI-writes-seen-watch-0", "[AXI] Writes seen by watch 0"}, 47 {"AXI", "AXI-reads-seen-watch-0", "[AXI] Reads seen by watch 0"}, 48 {"AXI", "AXI-writes-stalled-seen-watch-0", "[AXI] Write stalls seen by watch 0"}, 49 {"AXI", "AXI-reads-stalled-seen-watch-0", "[AXI] Read stalls seen by watch 0"}, 50 {"AXI", "AXI-write-bytes-seen-watch-0", "[AXI] Total bytes written seen by watch 0"}, 51 {"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"}, 52 {"AXI", "AXI-writes-seen-watch-1", "[AXI] Writes seen by watch 1"}, 53 {"AXI", "AXI-reads-seen-watch-1", "[AXI] Reads seen by watch 1"}, 54 {"AXI", "AXI-writes-stalled-seen-watch-1", "[AXI] Write stalls seen by watch 1"}, 55 {"AXI", "AXI-reads-stalled-seen-watch-1", "[AXI] Read stalls seen by watch 1"}, 56 {"AXI", "AXI-write-bytes-seen-watch-1", "[AXI] Total bytes written seen by watch 1"}, 57 {"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"}, 58 {"TLB", "TLB-partial-quads-written-to-color-buffer", "[TLB] Partial quads written to the colour buffer"}, 59 {"TMU", "TMU-total-config-access", "[TMU] Total config accesses"}, 60 {"L2T", "L2T-no-id-stalled", "[L2T] No ID stall"}, 61 {"L2T", "L2T-command-queue-stalled", "[L2T] Command queue full stall"}, 62 {"L2T", "L2T-TMU-writes", "[L2T] TMU write accesses"}, 63 {"TMU", "TMU-active-cycles", "[TMU] Active cycles"}, 64 {"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"}, 65 {"CLE", "CLE-thread-active-cycles", "[CLE] Bin or render thread active cycles"}, 66 {"L2T", "L2T-TMU-reads", "[L2T] TMU read accesses"}, 67 {"L2T", "L2T-CLE-reads", "[L2T] CLE read accesses"}, 68 {"L2T", "L2T-VCD-reads", "[L2T] VCD read accesses"}, 69 {"L2T", "L2T-TMU-config-reads", "[L2T] TMU CFG read accesses"}, 70 {"L2T", "L2T-SLC0-reads", "[L2T] SLC0 read accesses"}, 71 {"L2T", "L2T-SLC1-reads", "[L2T] SLC1 read accesses"}, 72 {"L2T", "L2T-SLC2-reads", "[L2T] SLC2 read accesses"}, 73 {"L2T", "L2T-TMU-write-miss", "[L2T] TMU write misses"}, 74 {"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"}, 75 {"L2T", "L2T-CLE-read-miss", "[L2T] CLE read misses"}, 76 {"L2T", "L2T-VCD-read-miss", "[L2T] VCD read misses"}, 77 {"L2T", "L2T-TMU-config-read-miss", "[L2T] TMU CFG read misses"}, 78 {"L2T", "L2T-SLC0-read-miss", "[L2T] SLC0 read misses"}, 79 {"L2T", "L2T-SLC1-read-miss", "[L2T] SLC1 read misses"}, 80 {"L2T", "L2T-SLC2-read-miss", "[L2T] SLC2 read misses"}, 81 {"CORE", "core-memory-writes", "[CORE] Total memory writes"}, 82 {"L2T", "L2T-memory-writes", "[L2T] Total memory writes"}, 83 {"PTB", "PTB-memory-writes", "[PTB] Total memory writes"}, 84 {"TLB", "TLB-memory-writes", "[TLB] Total memory writes"}, 85 {"CORE", "core-memory-reads", "[CORE] Total memory reads"}, 86 {"L2T", "L2T-memory-reads", "[L2T] Total memory reads"}, 87 {"PTB", "PTB-memory-reads", "[PTB] Total memory reads"}, 88 {"PSE", "PSE-memory-reads", "[PSE] Total memory reads"}, 89 {"TLB", "TLB-memory-reads", "[TLB] Total memory reads"}, 90 {"GMP", "GMP-memory-reads", "[GMP] Total memory reads"}, 91 {"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"}, 92 {"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"}, 93 {"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"}, 94 {"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"}, 95 {"TMU", "TMU-MRU-hits", "[TMU] Total MRU hits"}, 96 {"CORE", "compute-active-cycles", "[CORE] Compute active cycles"}, 97 }; 98 99 static const struct v3d_perf_counter_desc v3d_v71_performance_counters[] = { 100 {"CORE", "cycle-count", "[CORE] Cycle counter"}, 101 {"CORE", "core-active", "[CORE] Bin/Render/Compute active cycles"}, 102 {"CLE", "CLE-bin-thread-active-cycles", "[CLE] Bin thread active cycles"}, 103 {"CLE", "CLE-render-thread-active-cycles", "[CLE] Render thread active cycles"}, 104 {"CORE", "compute-active-cycles", "[CORE] Compute active cycles"}, 105 {"FEP", "FEP-valid-primitives-no-rendered-pixels", "[FEP] Valid primitives that result in no rendered pixels, for all rendered tiles"}, 106 {"FEP", "FEP-valid-primitives-rendered-pixels", "[FEP] Valid primitives for all rendered tiles (primitives may be counted in more than one tile)"}, 107 {"FEP", "FEP-clipped-quads", "[FEP] Early-Z/Near/Far clipped quads"}, 108 {"FEP", "FEP-valid-quads", "[FEP] Valid quads"}, 109 {"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test"}, 110 {"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and stencil tests"}, 111 {"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and stencil tests"}, 112 {"TLB", "TLB-quads-written-to-color-buffer", "[TLB] Quads with valid pixels written to colour buffer"}, 113 {"TLB", "TLB-partial-quads-written-to-color-buffer", "[TLB] Partial quads written to the colour buffer"}, 114 {"PTB", "PTB-primitives-need-clipping", "[PTB] Primitives that need clipping"}, 115 {"PTB", "PTB-primitives-discarded-outside-viewport", "[PTB] Primitives discarded by being outside the viewport"}, 116 {"PTB", "PTB-primitives-binned", "[PTB] Total primitives binned"}, 117 {"PTB", "PTB-primitives-discarded-reversed", "[PTB] Primitives that are discarded because they are reversed"}, 118 {"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"}, 119 {"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"}, 120 {"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"}, 121 {"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"}, 122 {"TMU", "TMU-active-cycles", "[TMU] Active cycles"}, 123 {"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"}, 124 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"}, 125 {"TMU", "TMU-cache-x4-active-cycles", "[TMU] Cache active cycles for x4 access"}, 126 {"TMU", "TMU-cache-x4-stalled-cycles", "[TMU] Cache stalled cycles for x4 access"}, 127 {"TMU", "TMU-total-text-quads-x4-access", "[TMU] Total texture cache x4 access"}, 128 {"L2T", "L2T-total-cache-hit", "[L2T] Total Level 2 cache hits"}, 129 {"L2T", "L2T-total-cache-miss", "[L2T] Total Level 2 cache misses"}, 130 {"L2T", "L2T-local", "[L2T] Local mode access"}, 131 {"L2T", "L2T-writeback", "[L2T] Writeback"}, 132 {"L2T", "L2T-zero", "[L2T] Zero"}, 133 {"L2T", "L2T-merge", "[L2T] Merge"}, 134 {"L2T", "L2T-fill", "[L2T] Fill"}, 135 {"L2T", "L2T-stalls-no-wid", "[L2T] Stalls because no WID available"}, 136 {"L2T", "L2T-stalls-no-rid", "[L2T] Stalls because no RID available"}, 137 {"L2T", "L2T-stalls-queue-full", "[L2T] Stalls because internal queue full"}, 138 {"L2T", "L2T-stalls-wrightback", "[L2T] Stalls because writeback in flight"}, 139 {"L2T", "L2T-stalls-mem", "[L2T] Stalls because AXI blocks read"}, 140 {"L2T", "L2T-stalls-fill", "[L2T] Stalls because fill pending for victim cache-line"}, 141 {"L2T", "L2T-hitq", "[L2T] Sent request via hit queue"}, 142 {"L2T", "L2T-hitq-full", "[L2T] Sent request via main queue because hit queue is full"}, 143 {"L2T", "L2T-stalls-read-data", "[L2T] Stalls because waiting for data from SDRAM"}, 144 {"L2T", "L2T-TMU-read-hits", "[L2T] TMU read hits"}, 145 {"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"}, 146 {"L2T", "L2T-VCD-read-hits", "[L2T] VCD read hits"}, 147 {"L2T", "L2T-VCD-read-miss", "[L2T] VCD read misses"}, 148 {"L2T", "L2T-SLC-read-hits", "[L2T] SLC read hits (all slices)"}, 149 {"L2T", "L2T-SLC-read-miss", "[L2T] SLC read misses (all slices)"}, 150 {"AXI", "AXI-writes-seen-watch-0", "[AXI] Writes seen by watch 0"}, 151 {"AXI", "AXI-reads-seen-watch-0", "[AXI] Reads seen by watch 0"}, 152 {"AXI", "AXI-writes-stalled-seen-watch-0", "[AXI] Write stalls seen by watch 0"}, 153 {"AXI", "AXI-reads-stalled-seen-watch-0", "[AXI] Read stalls seen by watch 0"}, 154 {"AXI", "AXI-write-bytes-seen-watch-0", "[AXI] Total bytes written seen by watch 0"}, 155 {"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"}, 156 {"AXI", "AXI-writes-seen-watch-1", "[AXI] Writes seen by watch 1"}, 157 {"AXI", "AXI-reads-seen-watch-1", "[AXI] Reads seen by watch 1"}, 158 {"AXI", "AXI-writes-stalled-seen-watch-1", "[AXI] Write stalls seen by watch 1"}, 159 {"AXI", "AXI-reads-stalled-seen-watch-1", "[AXI] Read stalls seen by watch 1"}, 160 {"AXI", "AXI-write-bytes-seen-watch-1", "[AXI] Total bytes written seen by watch 1"}, 161 {"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"}, 162 {"CORE", "core-memory-writes", "[CORE] Total memory writes"}, 163 {"L2T", "L2T-memory-writes", "[L2T] Total memory writes"}, 164 {"PTB", "PTB-memory-writes", "[PTB] Total memory writes"}, 165 {"TLB", "TLB-memory-writes", "[TLB] Total memory writes"}, 166 {"CORE", "core-memory-reads", "[CORE] Total memory reads"}, 167 {"L2T", "L2T-memory-reads", "[L2T] Total memory reads"}, 168 {"PTB", "PTB-memory-reads", "[PTB] Total memory reads"}, 169 {"PSE", "PSE-memory-reads", "[PSE] Total memory reads"}, 170 {"TLB", "TLB-memory-reads", "[TLB] Total memory reads"}, 171 {"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"}, 172 {"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"}, 173 {"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"}, 174 {"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"}, 175 {"AXI", "AXI-read-trans", "[AXI] Read transaction count"}, 176 {"AXI", "AXI-write-trans", "[AXI] Write transaction count"}, 177 {"AXI", "AXI-read-wait-cycles", "[AXI] Read total wait cycles"}, 178 {"AXI", "AXI-write-wait-cycles", "[AXI] Write total wait cycles"}, 179 {"AXI", "AXI-max-outstanding-reads", "[AXI] Maximum outstanding read transactions"}, 180 {"AXI", "AXI-max-outstanding-writes", "[AXI] Maximum outstanding write transactions"}, 181 {"QPU", "QPU-wait-bubble", "[QPU] Pipeline bubble in qcycles due all threads waiting"}, 182 {"QPU", "QPU-ic-miss-bubble", "[QPU] Pipeline bubble in qcycles due instruction-cache miss"}, 183 {"QPU", "QPU-active", "[QPU] Executed shader instruction"}, 184 {"QPU", "QPU-total-active-clk-cycles-fragment-shading", "[QPU] Total active clock cycles for all QPUs doing fragment shading (counts only when QPU is not stalled)"}, 185 {"QPU", "QPU-stalls", "[QPU] Stalled qcycles executing shader instruction"}, 186 {"QPU", "QPU-total-clk-cycles-waiting-fragment-shading", "[QPU] Total stalled clock cycles for all QPUs doing fragment shading"}, 187 {"QPU", "QPU-stalls-TMU", "[QPU] Stalled qcycles waiting for TMU"}, 188 {"QPU", "QPU-stalls-TLB", "[QPU] Stalled qcycles waiting for TLB"}, 189 {"QPU", "QPU-stalls-VPM", "[QPU] Stalled qcycles waiting for VPM"}, 190 {"QPU", "QPU-stalls-uniforms", "[QPU] Stalled qcycles waiting for uniforms"}, 191 {"QPU", "QPU-stalls-SFU", "[QPU] Stalled qcycles waiting for SFU"}, 192 {"QPU", "QPU-stalls-other", "[QPU] Stalled qcycles waiting for any other reason (vary/W/Z)"}, 193 }; 194 195 void v3d_perfmon_init(struct v3d_dev *v3d) 196 { 197 const struct v3d_perf_counter_desc *counters = NULL; 198 unsigned int max = 0; 199 200 if (v3d->ver >= V3D_GEN_71) { 201 counters = v3d_v71_performance_counters; 202 max = ARRAY_SIZE(v3d_v71_performance_counters); 203 } else if (v3d->ver >= V3D_GEN_42) { 204 counters = v3d_v42_performance_counters; 205 max = ARRAY_SIZE(v3d_v42_performance_counters); 206 } 207 208 v3d->perfmon_info.max_counters = max; 209 v3d->perfmon_info.counters = counters; 210 } 211 212 void v3d_perfmon_get(struct v3d_perfmon *perfmon) 213 { 214 if (perfmon) 215 refcount_inc(&perfmon->refcnt); 216 } 217 218 void v3d_perfmon_put(struct v3d_perfmon *perfmon) 219 { 220 if (perfmon && refcount_dec_and_test(&perfmon->refcnt)) { 221 mutex_destroy(&perfmon->lock); 222 kfree(perfmon); 223 } 224 } 225 226 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon) 227 { 228 unsigned int i; 229 u32 mask; 230 u8 ncounters; 231 232 if (WARN_ON_ONCE(!perfmon || v3d->active_perfmon)) 233 return; 234 235 ncounters = perfmon->ncounters; 236 mask = GENMASK(ncounters - 1, 0); 237 238 for (i = 0; i < ncounters; i++) { 239 u32 source = i / 4; 240 u32 channel = V3D_SET_FIELD_VER(perfmon->counters[i], V3D_PCTR_S0, 241 v3d->ver); 242 243 i++; 244 channel |= V3D_SET_FIELD_VER(i < ncounters ? perfmon->counters[i] : 0, 245 V3D_PCTR_S1, v3d->ver); 246 i++; 247 channel |= V3D_SET_FIELD_VER(i < ncounters ? perfmon->counters[i] : 0, 248 V3D_PCTR_S2, v3d->ver); 249 i++; 250 channel |= V3D_SET_FIELD_VER(i < ncounters ? perfmon->counters[i] : 0, 251 V3D_PCTR_S3, v3d->ver); 252 V3D_CORE_WRITE(0, V3D_V4_PCTR_0_SRC_X(source), channel); 253 } 254 255 V3D_CORE_WRITE(0, V3D_V4_PCTR_0_EN, mask); 256 V3D_CORE_WRITE(0, V3D_V4_PCTR_0_CLR, mask); 257 V3D_CORE_WRITE(0, V3D_PCTR_0_OVERFLOW, mask); 258 259 v3d->active_perfmon = perfmon; 260 } 261 262 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 263 bool capture) 264 { 265 unsigned int i; 266 267 if (!perfmon || !v3d->active_perfmon) 268 return; 269 270 mutex_lock(&perfmon->lock); 271 if (perfmon != v3d->active_perfmon) { 272 mutex_unlock(&perfmon->lock); 273 return; 274 } 275 276 if (capture) 277 for (i = 0; i < perfmon->ncounters; i++) 278 perfmon->values[i] += V3D_CORE_READ(0, V3D_PCTR_0_PCTRX(i)); 279 280 V3D_CORE_WRITE(0, V3D_V4_PCTR_0_EN, 0); 281 282 v3d->active_perfmon = NULL; 283 mutex_unlock(&perfmon->lock); 284 } 285 286 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id) 287 { 288 struct v3d_perfmon *perfmon; 289 290 xa_lock(&v3d_priv->perfmons); 291 perfmon = xa_load(&v3d_priv->perfmons, id); 292 v3d_perfmon_get(perfmon); 293 xa_unlock(&v3d_priv->perfmons); 294 295 return perfmon; 296 } 297 298 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv) 299 { 300 xa_init_flags(&v3d_priv->perfmons, XA_FLAGS_ALLOC1); 301 } 302 303 static void v3d_perfmon_delete(struct v3d_file_priv *v3d_priv, 304 struct v3d_perfmon *perfmon) 305 { 306 struct v3d_dev *v3d = v3d_priv->v3d; 307 308 /* If the active perfmon is being destroyed, stop it first */ 309 if (perfmon == v3d->active_perfmon) 310 v3d_perfmon_stop(v3d, perfmon, false); 311 312 /* If the global perfmon is being destroyed, set it to NULL */ 313 cmpxchg(&v3d->global_perfmon, perfmon, NULL); 314 315 v3d_perfmon_put(perfmon); 316 } 317 318 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv) 319 { 320 struct v3d_perfmon *perfmon; 321 unsigned long id; 322 323 xa_for_each(&v3d_priv->perfmons, id, perfmon) 324 v3d_perfmon_delete(v3d_priv, perfmon); 325 326 xa_destroy(&v3d_priv->perfmons); 327 } 328 329 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 330 struct drm_file *file_priv) 331 { 332 struct v3d_file_priv *v3d_priv = file_priv->driver_priv; 333 struct drm_v3d_perfmon_create *req = data; 334 struct v3d_dev *v3d = v3d_priv->v3d; 335 struct v3d_perfmon *perfmon; 336 unsigned int i; 337 int ret; 338 u32 id; 339 340 /* Number of monitored counters cannot exceed HW limits. */ 341 if (req->ncounters > DRM_V3D_MAX_PERF_COUNTERS || 342 !req->ncounters) 343 return -EINVAL; 344 345 /* Make sure all counters are valid. */ 346 for (i = 0; i < req->ncounters; i++) { 347 if (req->counters[i] >= v3d->perfmon_info.max_counters) 348 return -EINVAL; 349 } 350 351 perfmon = kzalloc_flex(*perfmon, values, req->ncounters); 352 if (!perfmon) 353 return -ENOMEM; 354 355 for (i = 0; i < req->ncounters; i++) 356 perfmon->counters[i] = req->counters[i]; 357 358 perfmon->ncounters = req->ncounters; 359 360 refcount_set(&perfmon->refcnt, 1); 361 mutex_init(&perfmon->lock); 362 363 ret = xa_alloc(&v3d_priv->perfmons, &id, perfmon, xa_limit_32b, 364 GFP_KERNEL); 365 if (ret < 0) { 366 mutex_destroy(&perfmon->lock); 367 kfree(perfmon); 368 return ret; 369 } 370 371 req->id = id; 372 373 return 0; 374 } 375 376 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 377 struct drm_file *file_priv) 378 { 379 struct v3d_file_priv *v3d_priv = file_priv->driver_priv; 380 struct drm_v3d_perfmon_destroy *req = data; 381 struct v3d_perfmon *perfmon; 382 383 perfmon = xa_erase(&v3d_priv->perfmons, req->id); 384 if (!perfmon) 385 return -EINVAL; 386 387 v3d_perfmon_delete(v3d_priv, perfmon); 388 389 return 0; 390 } 391 392 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 393 struct drm_file *file_priv) 394 { 395 struct v3d_dev *v3d = to_v3d_dev(dev); 396 struct v3d_file_priv *v3d_priv = file_priv->driver_priv; 397 struct drm_v3d_perfmon_get_values *req = data; 398 struct v3d_perfmon *perfmon; 399 int ret = 0; 400 401 if (req->pad != 0) 402 return -EINVAL; 403 404 perfmon = v3d_perfmon_find(v3d_priv, req->id); 405 if (!perfmon) 406 return -EINVAL; 407 408 v3d_perfmon_stop(v3d, perfmon, true); 409 410 if (copy_to_user(u64_to_user_ptr(req->values_ptr), perfmon->values, 411 perfmon->ncounters * sizeof(u64))) 412 ret = -EFAULT; 413 414 v3d_perfmon_put(perfmon); 415 416 return ret; 417 } 418 419 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data, 420 struct drm_file *file_priv) 421 { 422 struct drm_v3d_perfmon_get_counter *req = data; 423 struct v3d_dev *v3d = to_v3d_dev(dev); 424 const struct v3d_perf_counter_desc *counter; 425 426 for (int i = 0; i < ARRAY_SIZE(req->reserved); i++) { 427 if (req->reserved[i] != 0) 428 return -EINVAL; 429 } 430 431 if (!v3d->perfmon_info.max_counters) 432 return -EOPNOTSUPP; 433 434 /* Make sure that the counter ID is valid */ 435 if (req->counter >= v3d->perfmon_info.max_counters) 436 return -EINVAL; 437 438 counter = &v3d->perfmon_info.counters[req->counter]; 439 440 strscpy(req->name, counter->name, sizeof(req->name)); 441 strscpy(req->category, counter->category, sizeof(req->category)); 442 strscpy(req->description, counter->description, sizeof(req->description)); 443 444 return 0; 445 } 446 447 int v3d_perfmon_set_global_ioctl(struct drm_device *dev, void *data, 448 struct drm_file *file_priv) 449 { 450 struct v3d_file_priv *v3d_priv = file_priv->driver_priv; 451 struct drm_v3d_perfmon_set_global *req = data; 452 struct v3d_dev *v3d = to_v3d_dev(dev); 453 struct v3d_perfmon *perfmon; 454 455 if (req->flags & ~DRM_V3D_PERFMON_CLEAR_GLOBAL) 456 return -EINVAL; 457 458 perfmon = v3d_perfmon_find(v3d_priv, req->id); 459 if (!perfmon) 460 return -EINVAL; 461 462 /* If the request is to clear the global performance monitor */ 463 if (req->flags & DRM_V3D_PERFMON_CLEAR_GLOBAL) { 464 if (!v3d->global_perfmon) 465 return -EINVAL; 466 467 xchg(&v3d->global_perfmon, NULL); 468 469 return 0; 470 } 471 472 if (cmpxchg(&v3d->global_perfmon, NULL, perfmon)) 473 return -EBUSY; 474 475 return 0; 476 } 477