1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2017-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D MMU 6 * 7 * The V3D 3.x hardware (compared to VC4) now includes an MMU. It has 8 * a single level of page tables for the V3D's 4GB address space to 9 * map to AXI bus addresses, thus it could need up to 4MB of 10 * physically contiguous memory to store the PTEs. 11 * 12 * Because the 4MB of contiguous memory for page tables is precious, 13 * and switching between them is expensive, we load all BOs into the 14 * same 4GB address space. 15 * 16 * To protect clients from each other, we should use the GMP to 17 * quickly mask out (at 128kb granularity) what pages are available to 18 * each client. This is not yet implemented. 19 */ 20 21 #include <drm/drm_print.h> 22 23 #include "v3d_drv.h" 24 #include "v3d_regs.h" 25 26 /* Note: All PTEs for the 64KB bigpage or 1MB superpage must be filled 27 * with the bigpage/superpage bit set. 28 */ 29 #define V3D_PTE_SUPERPAGE BIT(31) 30 #define V3D_PTE_BIGPAGE BIT(30) 31 #define V3D_PTE_WRITEABLE BIT(29) 32 #define V3D_PTE_VALID BIT(28) 33 34 static bool v3d_mmu_is_aligned(u32 page, u32 page_address, size_t alignment) 35 { 36 return IS_ALIGNED(page, alignment >> V3D_MMU_PAGE_SHIFT) && 37 IS_ALIGNED(page_address, alignment >> V3D_MMU_PAGE_SHIFT); 38 } 39 40 int v3d_mmu_flush_all(struct v3d_dev *v3d) 41 { 42 int ret; 43 44 V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_FLUSH | 45 V3D_MMUC_CONTROL_ENABLE); 46 47 ret = wait_for(!(V3D_READ(V3D_MMUC_CONTROL) & 48 V3D_MMUC_CONTROL_FLUSHING), 100); 49 if (ret) { 50 dev_err(v3d->drm.dev, "MMUC flush wait idle failed\n"); 51 return ret; 52 } 53 54 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL) | 55 V3D_MMU_CTL_TLB_CLEAR); 56 57 ret = wait_for(!(V3D_READ(V3D_MMU_CTL) & 58 V3D_MMU_CTL_TLB_CLEARING), 100); 59 if (ret) 60 dev_err(v3d->drm.dev, "MMU TLB clear wait idle failed\n"); 61 62 return ret; 63 } 64 65 int v3d_mmu_set_page_table(struct v3d_dev *v3d) 66 { 67 V3D_WRITE(V3D_MMU_PT_PA_BASE, v3d->pt_paddr >> V3D_MMU_PAGE_SHIFT); 68 V3D_WRITE(V3D_MMU_CTL, 69 V3D_MMU_CTL_ENABLE | 70 V3D_MMU_CTL_PT_INVALID_ENABLE | 71 V3D_MMU_CTL_PT_INVALID_ABORT | 72 V3D_MMU_CTL_PT_INVALID_INT | 73 V3D_MMU_CTL_WRITE_VIOLATION_ABORT | 74 V3D_MMU_CTL_WRITE_VIOLATION_INT | 75 V3D_MMU_CTL_CAP_EXCEEDED_ABORT | 76 V3D_MMU_CTL_CAP_EXCEEDED_INT); 77 V3D_WRITE(V3D_MMU_ILLEGAL_ADDR, 78 (v3d->mmu_scratch_paddr >> V3D_MMU_PAGE_SHIFT) | 79 V3D_MMU_ILLEGAL_ADDR_ENABLE); 80 V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_ENABLE); 81 82 return v3d_mmu_flush_all(v3d); 83 } 84 85 void v3d_mmu_insert_ptes(struct v3d_bo *bo) 86 { 87 struct drm_gem_shmem_object *shmem_obj = &bo->base; 88 struct v3d_dev *v3d = to_v3d_dev(shmem_obj->base.dev); 89 u32 page = bo->node.start; 90 struct scatterlist *sgl; 91 unsigned int count; 92 93 for_each_sgtable_dma_sg(shmem_obj->sgt, sgl, count) { 94 dma_addr_t dma_addr = sg_dma_address(sgl); 95 u32 pfn = dma_addr >> V3D_MMU_PAGE_SHIFT; 96 unsigned int len = sg_dma_len(sgl); 97 98 while (len > 0) { 99 u32 page_prot = V3D_PTE_WRITEABLE | V3D_PTE_VALID; 100 u32 page_address = page_prot | pfn; 101 unsigned int i, page_size; 102 103 BUG_ON(pfn + V3D_PAGE_FACTOR >= BIT(24)); 104 105 if (len >= SZ_1M && 106 v3d_mmu_is_aligned(page, page_address, SZ_1M)) { 107 page_size = SZ_1M; 108 page_address |= V3D_PTE_SUPERPAGE; 109 } else if (len >= SZ_64K && 110 v3d_mmu_is_aligned(page, page_address, SZ_64K)) { 111 page_size = SZ_64K; 112 page_address |= V3D_PTE_BIGPAGE; 113 } else { 114 page_size = SZ_4K; 115 } 116 117 for (i = 0; i < page_size >> V3D_MMU_PAGE_SHIFT; i++) { 118 v3d->pt[page++] = page_address + i; 119 pfn++; 120 } 121 122 len -= page_size; 123 } 124 } 125 126 WARN_ON_ONCE(page - bo->node.start != 127 shmem_obj->base.size >> V3D_MMU_PAGE_SHIFT); 128 129 if (v3d_mmu_flush_all(v3d)) 130 drm_err(&v3d->drm, "MMU flush timeout\n"); 131 } 132 133 void v3d_mmu_remove_ptes(struct v3d_bo *bo) 134 { 135 struct v3d_dev *v3d = to_v3d_dev(bo->base.base.dev); 136 u32 npages = bo->base.base.size >> V3D_MMU_PAGE_SHIFT; 137 u32 page; 138 139 for (page = bo->node.start; page < bo->node.start + npages; page++) 140 v3d->pt[page] = 0; 141 142 if (v3d_mmu_flush_all(v3d)) 143 drm_err(&v3d->drm, "MMU flush timeout\n"); 144 } 145