1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2017-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D MMU 6 * 7 * The V3D 3.x hardware (compared to VC4) now includes an MMU. It has 8 * a single level of page tables for the V3D's 4GB address space to 9 * map to AXI bus addresses, thus it could need up to 4MB of 10 * physically contiguous memory to store the PTEs. 11 * 12 * Because the 4MB of contiguous memory for page tables is precious, 13 * and switching between them is expensive, we load all BOs into the 14 * same 4GB address space. 15 * 16 * To protect clients from each other, we should use the GMP to 17 * quickly mask out (at 128kb granularity) what pages are available to 18 * each client. This is not yet implemented. 19 */ 20 21 #include <drm/drm_print.h> 22 23 #include "v3d_drv.h" 24 #include "v3d_regs.h" 25 26 /* Note: All PTEs for the 64KB bigpage or 1MB superpage must be filled 27 * with the bigpage/superpage bit set. 28 */ 29 #define V3D_PTE_SUPERPAGE BIT(31) 30 #define V3D_PTE_BIGPAGE BIT(30) 31 #define V3D_PTE_WRITEABLE BIT(29) 32 #define V3D_PTE_VALID BIT(28) 33 34 static bool v3d_mmu_is_aligned(u32 page, u32 page_address, size_t alignment) 35 { 36 return IS_ALIGNED(page, alignment >> V3D_MMU_PAGE_SHIFT) && 37 IS_ALIGNED(page_address, alignment >> V3D_MMU_PAGE_SHIFT); 38 } 39 40 int v3d_mmu_flush_all(struct v3d_dev *v3d) 41 { 42 int ret = 0; 43 44 /* Flush the PTs only if we're already awake */ 45 if (!pm_runtime_get_if_active(v3d->drm.dev)) 46 return 0; 47 48 V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_FLUSH | 49 V3D_MMUC_CONTROL_ENABLE); 50 51 ret = wait_for(!(V3D_READ(V3D_MMUC_CONTROL) & 52 V3D_MMUC_CONTROL_FLUSHING), 100); 53 if (ret) { 54 dev_err(v3d->drm.dev, "MMUC flush wait idle failed\n"); 55 goto pm_put; 56 } 57 58 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL) | 59 V3D_MMU_CTL_TLB_CLEAR); 60 61 ret = wait_for(!(V3D_READ(V3D_MMU_CTL) & 62 V3D_MMU_CTL_TLB_CLEARING), 100); 63 if (ret) 64 dev_err(v3d->drm.dev, "MMU TLB clear wait idle failed\n"); 65 66 pm_put: 67 v3d_pm_runtime_put(v3d); 68 return ret; 69 } 70 71 int v3d_mmu_set_page_table(struct v3d_dev *v3d) 72 { 73 V3D_WRITE(V3D_MMU_PT_PA_BASE, v3d->pt_paddr >> V3D_MMU_PAGE_SHIFT); 74 V3D_WRITE(V3D_MMU_CTL, 75 V3D_MMU_CTL_ENABLE | 76 V3D_MMU_CTL_PT_INVALID_ENABLE | 77 V3D_MMU_CTL_PT_INVALID_ABORT | 78 V3D_MMU_CTL_PT_INVALID_INT | 79 V3D_MMU_CTL_WRITE_VIOLATION_ABORT | 80 V3D_MMU_CTL_WRITE_VIOLATION_INT | 81 V3D_MMU_CTL_CAP_EXCEEDED_ABORT | 82 V3D_MMU_CTL_CAP_EXCEEDED_INT); 83 V3D_WRITE(V3D_MMU_ILLEGAL_ADDR, 84 (v3d->mmu_scratch_paddr >> V3D_MMU_PAGE_SHIFT) | 85 V3D_MMU_ILLEGAL_ADDR_ENABLE); 86 V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_ENABLE); 87 88 return v3d_mmu_flush_all(v3d); 89 } 90 91 void v3d_mmu_insert_ptes(struct v3d_bo *bo) 92 { 93 struct drm_gem_shmem_object *shmem_obj = &bo->base; 94 struct v3d_dev *v3d = to_v3d_dev(shmem_obj->base.dev); 95 u32 page = bo->node.start; 96 struct scatterlist *sgl; 97 unsigned int count; 98 99 for_each_sgtable_dma_sg(shmem_obj->sgt, sgl, count) { 100 dma_addr_t dma_addr = sg_dma_address(sgl); 101 u32 pfn = dma_addr >> V3D_MMU_PAGE_SHIFT; 102 unsigned int len = sg_dma_len(sgl); 103 104 while (len > 0) { 105 u32 page_prot = V3D_PTE_WRITEABLE | V3D_PTE_VALID; 106 u32 page_address = page_prot | pfn; 107 unsigned int i, page_size; 108 109 BUG_ON(pfn + V3D_PAGE_FACTOR >= BIT(24)); 110 111 if (len >= SZ_1M && 112 v3d_mmu_is_aligned(page, page_address, SZ_1M)) { 113 page_size = SZ_1M; 114 page_address |= V3D_PTE_SUPERPAGE; 115 } else if (len >= SZ_64K && 116 v3d_mmu_is_aligned(page, page_address, SZ_64K)) { 117 page_size = SZ_64K; 118 page_address |= V3D_PTE_BIGPAGE; 119 } else { 120 page_size = SZ_4K; 121 } 122 123 for (i = 0; i < page_size >> V3D_MMU_PAGE_SHIFT; i++) { 124 v3d->pt[page++] = page_address + i; 125 pfn++; 126 } 127 128 len -= page_size; 129 } 130 } 131 132 WARN_ON_ONCE(page - bo->node.start != 133 shmem_obj->base.size >> V3D_MMU_PAGE_SHIFT); 134 135 if (v3d_mmu_flush_all(v3d)) 136 drm_err(&v3d->drm, "MMU flush timeout\n"); 137 } 138 139 void v3d_mmu_remove_ptes(struct v3d_bo *bo) 140 { 141 struct v3d_dev *v3d = to_v3d_dev(bo->base.base.dev); 142 u32 npages = bo->base.base.size >> V3D_MMU_PAGE_SHIFT; 143 u32 page; 144 145 for (page = bo->node.start; page < bo->node.start + npages; page++) 146 v3d->pt[page] = 0; 147 148 if (v3d_mmu_flush_all(v3d)) 149 drm_err(&v3d->drm, "MMU flush timeout\n"); 150 } 151