1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Interrupt management for the V3D engine 6 * 7 * When we take a bin, render, TFU done, or CSD done interrupt, we 8 * need to signal the fence for that job so that the scheduler can 9 * queue up the next one and unblock any waiters. 10 * 11 * When we take the binner out of memory interrupt, we need to 12 * allocate some new memory and pass it to the binner so that the 13 * current job can make progress. 14 */ 15 16 #include "v3d_drv.h" 17 #include "v3d_regs.h" 18 #include "v3d_trace.h" 19 20 #define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM | \ 21 V3D_INT_FLDONE | \ 22 V3D_INT_FRDONE | \ 23 V3D_INT_CSDDONE | \ 24 V3D_INT_GMPV)) 25 26 #define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \ 27 V3D_HUB_INT_MMU_PTI | \ 28 V3D_HUB_INT_MMU_CAP | \ 29 V3D_HUB_INT_TFUC)) 30 31 static irqreturn_t 32 v3d_hub_irq(int irq, void *arg); 33 34 static void 35 v3d_overflow_mem_work(struct work_struct *work) 36 { 37 struct v3d_dev *v3d = 38 container_of(work, struct v3d_dev, overflow_mem_work); 39 struct drm_device *dev = &v3d->drm; 40 struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024); 41 struct drm_gem_object *obj; 42 unsigned long irqflags; 43 44 if (IS_ERR(bo)) { 45 DRM_ERROR("Couldn't allocate binner overflow mem\n"); 46 return; 47 } 48 obj = &bo->base.base; 49 50 /* We lost a race, and our work task came in after the bin job 51 * completed and exited. This can happen because the HW 52 * signals OOM before it's fully OOM, so the binner might just 53 * barely complete. 54 * 55 * If we lose the race and our work task comes in after a new 56 * bin job got scheduled, that's fine. We'll just give them 57 * some binner pool anyway. 58 */ 59 spin_lock_irqsave(&v3d->job_lock, irqflags); 60 if (!v3d->bin_job) { 61 spin_unlock_irqrestore(&v3d->job_lock, irqflags); 62 goto out; 63 } 64 65 drm_gem_object_get(obj); 66 list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list); 67 spin_unlock_irqrestore(&v3d->job_lock, irqflags); 68 69 V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT); 70 V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size); 71 72 out: 73 drm_gem_object_put_unlocked(obj); 74 } 75 76 static irqreturn_t 77 v3d_irq(int irq, void *arg) 78 { 79 struct v3d_dev *v3d = arg; 80 u32 intsts; 81 irqreturn_t status = IRQ_NONE; 82 83 intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS); 84 85 /* Acknowledge the interrupts we're handling here. */ 86 V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts); 87 88 if (intsts & V3D_INT_OUTOMEM) { 89 /* Note that the OOM status is edge signaled, so the 90 * interrupt won't happen again until the we actually 91 * add more memory. Also, as of V3D 4.1, FLDONE won't 92 * be reported until any OOM state has been cleared. 93 */ 94 schedule_work(&v3d->overflow_mem_work); 95 status = IRQ_HANDLED; 96 } 97 98 if (intsts & V3D_INT_FLDONE) { 99 struct v3d_fence *fence = 100 to_v3d_fence(v3d->bin_job->base.irq_fence); 101 102 trace_v3d_bcl_irq(&v3d->drm, fence->seqno); 103 dma_fence_signal(&fence->base); 104 status = IRQ_HANDLED; 105 } 106 107 if (intsts & V3D_INT_FRDONE) { 108 struct v3d_fence *fence = 109 to_v3d_fence(v3d->render_job->base.irq_fence); 110 111 trace_v3d_rcl_irq(&v3d->drm, fence->seqno); 112 dma_fence_signal(&fence->base); 113 status = IRQ_HANDLED; 114 } 115 116 if (intsts & V3D_INT_CSDDONE) { 117 struct v3d_fence *fence = 118 to_v3d_fence(v3d->csd_job->base.irq_fence); 119 120 trace_v3d_csd_irq(&v3d->drm, fence->seqno); 121 dma_fence_signal(&fence->base); 122 status = IRQ_HANDLED; 123 } 124 125 /* We shouldn't be triggering these if we have GMP in 126 * always-allowed mode. 127 */ 128 if (intsts & V3D_INT_GMPV) 129 dev_err(v3d->dev, "GMP violation\n"); 130 131 /* V3D 4.2 wires the hub and core IRQs together, so if we & 132 * didn't see the common one then check hub for MMU IRQs. 133 */ 134 if (v3d->single_irq_line && status == IRQ_NONE) 135 return v3d_hub_irq(irq, arg); 136 137 return status; 138 } 139 140 static irqreturn_t 141 v3d_hub_irq(int irq, void *arg) 142 { 143 struct v3d_dev *v3d = arg; 144 u32 intsts; 145 irqreturn_t status = IRQ_NONE; 146 147 intsts = V3D_READ(V3D_HUB_INT_STS); 148 149 /* Acknowledge the interrupts we're handling here. */ 150 V3D_WRITE(V3D_HUB_INT_CLR, intsts); 151 152 if (intsts & V3D_HUB_INT_TFUC) { 153 struct v3d_fence *fence = 154 to_v3d_fence(v3d->tfu_job->base.irq_fence); 155 156 trace_v3d_tfu_irq(&v3d->drm, fence->seqno); 157 dma_fence_signal(&fence->base); 158 status = IRQ_HANDLED; 159 } 160 161 if (intsts & (V3D_HUB_INT_MMU_WRV | 162 V3D_HUB_INT_MMU_PTI | 163 V3D_HUB_INT_MMU_CAP)) { 164 u32 axi_id = V3D_READ(V3D_MMU_VIO_ID); 165 u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) << 166 (v3d->va_width - 32)); 167 static const char *const v3d41_axi_ids[] = { 168 "L2T", 169 "PTB", 170 "PSE", 171 "TLB", 172 "CLE", 173 "TFU", 174 "MMU", 175 "GMP", 176 }; 177 const char *client = "?"; 178 179 V3D_WRITE(V3D_MMU_CTL, 180 V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED | 181 V3D_MMU_CTL_PT_INVALID | 182 V3D_MMU_CTL_WRITE_VIOLATION)); 183 184 if (v3d->ver >= 41) { 185 axi_id = axi_id >> 5; 186 if (axi_id < ARRAY_SIZE(v3d41_axi_ids)) 187 client = v3d41_axi_ids[axi_id]; 188 } 189 190 dev_err(v3d->dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n", 191 client, axi_id, (long long)vio_addr, 192 ((intsts & V3D_HUB_INT_MMU_WRV) ? 193 ", write violation" : ""), 194 ((intsts & V3D_HUB_INT_MMU_PTI) ? 195 ", pte invalid" : ""), 196 ((intsts & V3D_HUB_INT_MMU_CAP) ? 197 ", cap exceeded" : "")); 198 status = IRQ_HANDLED; 199 } 200 201 return status; 202 } 203 204 int 205 v3d_irq_init(struct v3d_dev *v3d) 206 { 207 int irq1, ret, core; 208 209 INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work); 210 211 /* Clear any pending interrupts someone might have left around 212 * for us. 213 */ 214 for (core = 0; core < v3d->cores; core++) 215 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS); 216 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); 217 218 irq1 = platform_get_irq(v3d->pdev, 1); 219 if (irq1 == -EPROBE_DEFER) 220 return irq1; 221 if (irq1 > 0) { 222 ret = devm_request_irq(v3d->dev, irq1, 223 v3d_irq, IRQF_SHARED, 224 "v3d_core0", v3d); 225 if (ret) 226 goto fail; 227 ret = devm_request_irq(v3d->dev, platform_get_irq(v3d->pdev, 0), 228 v3d_hub_irq, IRQF_SHARED, 229 "v3d_hub", v3d); 230 if (ret) 231 goto fail; 232 } else { 233 v3d->single_irq_line = true; 234 235 ret = devm_request_irq(v3d->dev, platform_get_irq(v3d->pdev, 0), 236 v3d_irq, IRQF_SHARED, 237 "v3d", v3d); 238 if (ret) 239 goto fail; 240 } 241 242 v3d_irq_enable(v3d); 243 return 0; 244 245 fail: 246 if (ret != -EPROBE_DEFER) 247 dev_err(v3d->dev, "IRQ setup failed: %d\n", ret); 248 return ret; 249 } 250 251 void 252 v3d_irq_enable(struct v3d_dev *v3d) 253 { 254 int core; 255 256 /* Enable our set of interrupts, masking out any others. */ 257 for (core = 0; core < v3d->cores; core++) { 258 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS); 259 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS); 260 } 261 262 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS); 263 V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS); 264 } 265 266 void 267 v3d_irq_disable(struct v3d_dev *v3d) 268 { 269 int core; 270 271 /* Disable all interrupts. */ 272 for (core = 0; core < v3d->cores; core++) 273 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0); 274 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); 275 276 /* Clear any pending interrupts we might have left. */ 277 for (core = 0; core < v3d->cores; core++) 278 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS); 279 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); 280 281 cancel_work_sync(&v3d->overflow_mem_work); 282 } 283 284 /** Reinitializes interrupt registers when a GPU reset is performed. */ 285 void v3d_irq_reset(struct v3d_dev *v3d) 286 { 287 v3d_irq_enable(v3d); 288 } 289