1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Interrupt management for the V3D engine 6 * 7 * When we take a bin, render, TFU done, or CSD done interrupt, we 8 * need to signal the fence for that job so that the scheduler can 9 * queue up the next one and unblock any waiters. 10 * 11 * When we take the binner out of memory interrupt, we need to 12 * allocate some new memory and pass it to the binner so that the 13 * current job can make progress. 14 */ 15 16 #include <linux/platform_device.h> 17 #include <linux/sched/clock.h> 18 19 #include "v3d_drv.h" 20 #include "v3d_regs.h" 21 #include "v3d_trace.h" 22 23 #define V3D_CORE_IRQS(ver) ((u32)(V3D_INT_OUTOMEM | \ 24 V3D_INT_FLDONE | \ 25 V3D_INT_FRDONE | \ 26 V3D_INT_CSDDONE(ver) | \ 27 (ver < 71 ? V3D_INT_GMPV : 0))) 28 29 #define V3D_HUB_IRQS(ver) ((u32)(V3D_HUB_INT_MMU_WRV | \ 30 V3D_HUB_INT_MMU_PTI | \ 31 V3D_HUB_INT_MMU_CAP | \ 32 V3D_HUB_INT_TFUC | \ 33 (ver >= 71 ? V3D_V7_HUB_INT_GMPV : 0))) 34 35 static irqreturn_t 36 v3d_hub_irq(int irq, void *arg); 37 38 static void 39 v3d_overflow_mem_work(struct work_struct *work) 40 { 41 struct v3d_dev *v3d = 42 container_of(work, struct v3d_dev, overflow_mem_work); 43 struct drm_device *dev = &v3d->drm; 44 struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024); 45 struct drm_gem_object *obj; 46 unsigned long irqflags; 47 48 if (IS_ERR(bo)) { 49 DRM_ERROR("Couldn't allocate binner overflow mem\n"); 50 return; 51 } 52 obj = &bo->base.base; 53 54 /* We lost a race, and our work task came in after the bin job 55 * completed and exited. This can happen because the HW 56 * signals OOM before it's fully OOM, so the binner might just 57 * barely complete. 58 * 59 * If we lose the race and our work task comes in after a new 60 * bin job got scheduled, that's fine. We'll just give them 61 * some binner pool anyway. 62 */ 63 spin_lock_irqsave(&v3d->job_lock, irqflags); 64 if (!v3d->bin_job) { 65 spin_unlock_irqrestore(&v3d->job_lock, irqflags); 66 goto out; 67 } 68 69 drm_gem_object_get(obj); 70 list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list); 71 spin_unlock_irqrestore(&v3d->job_lock, irqflags); 72 73 V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << V3D_MMU_PAGE_SHIFT); 74 V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size); 75 76 out: 77 drm_gem_object_put(obj); 78 } 79 80 static irqreturn_t 81 v3d_irq(int irq, void *arg) 82 { 83 struct v3d_dev *v3d = arg; 84 u32 intsts; 85 irqreturn_t status = IRQ_NONE; 86 87 intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS); 88 89 /* Acknowledge the interrupts we're handling here. */ 90 V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts); 91 92 if (intsts & V3D_INT_OUTOMEM) { 93 /* Note that the OOM status is edge signaled, so the 94 * interrupt won't happen again until the we actually 95 * add more memory. Also, as of V3D 4.1, FLDONE won't 96 * be reported until any OOM state has been cleared. 97 */ 98 schedule_work(&v3d->overflow_mem_work); 99 status = IRQ_HANDLED; 100 } 101 102 if (intsts & V3D_INT_FLDONE) { 103 struct v3d_fence *fence = 104 to_v3d_fence(v3d->bin_job->base.irq_fence); 105 struct v3d_file_priv *file = v3d->bin_job->base.file->driver_priv; 106 u64 runtime = local_clock() - file->start_ns[V3D_BIN]; 107 108 file->jobs_sent[V3D_BIN]++; 109 v3d->queue[V3D_BIN].jobs_sent++; 110 111 file->start_ns[V3D_BIN] = 0; 112 v3d->queue[V3D_BIN].start_ns = 0; 113 114 file->enabled_ns[V3D_BIN] += runtime; 115 v3d->queue[V3D_BIN].enabled_ns += runtime; 116 117 trace_v3d_bcl_irq(&v3d->drm, fence->seqno); 118 dma_fence_signal(&fence->base); 119 status = IRQ_HANDLED; 120 } 121 122 if (intsts & V3D_INT_FRDONE) { 123 struct v3d_fence *fence = 124 to_v3d_fence(v3d->render_job->base.irq_fence); 125 struct v3d_file_priv *file = v3d->render_job->base.file->driver_priv; 126 u64 runtime = local_clock() - file->start_ns[V3D_RENDER]; 127 128 file->jobs_sent[V3D_RENDER]++; 129 v3d->queue[V3D_RENDER].jobs_sent++; 130 131 file->start_ns[V3D_RENDER] = 0; 132 v3d->queue[V3D_RENDER].start_ns = 0; 133 134 file->enabled_ns[V3D_RENDER] += runtime; 135 v3d->queue[V3D_RENDER].enabled_ns += runtime; 136 137 trace_v3d_rcl_irq(&v3d->drm, fence->seqno); 138 dma_fence_signal(&fence->base); 139 status = IRQ_HANDLED; 140 } 141 142 if (intsts & V3D_INT_CSDDONE(v3d->ver)) { 143 struct v3d_fence *fence = 144 to_v3d_fence(v3d->csd_job->base.irq_fence); 145 struct v3d_file_priv *file = v3d->csd_job->base.file->driver_priv; 146 u64 runtime = local_clock() - file->start_ns[V3D_CSD]; 147 148 file->jobs_sent[V3D_CSD]++; 149 v3d->queue[V3D_CSD].jobs_sent++; 150 151 file->start_ns[V3D_CSD] = 0; 152 v3d->queue[V3D_CSD].start_ns = 0; 153 154 file->enabled_ns[V3D_CSD] += runtime; 155 v3d->queue[V3D_CSD].enabled_ns += runtime; 156 157 trace_v3d_csd_irq(&v3d->drm, fence->seqno); 158 dma_fence_signal(&fence->base); 159 status = IRQ_HANDLED; 160 } 161 162 /* We shouldn't be triggering these if we have GMP in 163 * always-allowed mode. 164 */ 165 if (v3d->ver < 71 && (intsts & V3D_INT_GMPV)) 166 dev_err(v3d->drm.dev, "GMP violation\n"); 167 168 /* V3D 4.2 wires the hub and core IRQs together, so if we & 169 * didn't see the common one then check hub for MMU IRQs. 170 */ 171 if (v3d->single_irq_line && status == IRQ_NONE) 172 return v3d_hub_irq(irq, arg); 173 174 return status; 175 } 176 177 static irqreturn_t 178 v3d_hub_irq(int irq, void *arg) 179 { 180 struct v3d_dev *v3d = arg; 181 u32 intsts; 182 irqreturn_t status = IRQ_NONE; 183 184 intsts = V3D_READ(V3D_HUB_INT_STS); 185 186 /* Acknowledge the interrupts we're handling here. */ 187 V3D_WRITE(V3D_HUB_INT_CLR, intsts); 188 189 if (intsts & V3D_HUB_INT_TFUC) { 190 struct v3d_fence *fence = 191 to_v3d_fence(v3d->tfu_job->base.irq_fence); 192 struct v3d_file_priv *file = v3d->tfu_job->base.file->driver_priv; 193 u64 runtime = local_clock() - file->start_ns[V3D_TFU]; 194 195 file->jobs_sent[V3D_TFU]++; 196 v3d->queue[V3D_TFU].jobs_sent++; 197 198 file->start_ns[V3D_TFU] = 0; 199 v3d->queue[V3D_TFU].start_ns = 0; 200 201 file->enabled_ns[V3D_TFU] += runtime; 202 v3d->queue[V3D_TFU].enabled_ns += runtime; 203 204 trace_v3d_tfu_irq(&v3d->drm, fence->seqno); 205 dma_fence_signal(&fence->base); 206 status = IRQ_HANDLED; 207 } 208 209 if (intsts & (V3D_HUB_INT_MMU_WRV | 210 V3D_HUB_INT_MMU_PTI | 211 V3D_HUB_INT_MMU_CAP)) { 212 u32 axi_id = V3D_READ(V3D_MMU_VIO_ID); 213 u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) << 214 (v3d->va_width - 32)); 215 static const char *const v3d41_axi_ids[] = { 216 "L2T", 217 "PTB", 218 "PSE", 219 "TLB", 220 "CLE", 221 "TFU", 222 "MMU", 223 "GMP", 224 }; 225 const char *client = "?"; 226 227 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL)); 228 229 if (v3d->ver >= 41) { 230 axi_id = axi_id >> 5; 231 if (axi_id < ARRAY_SIZE(v3d41_axi_ids)) 232 client = v3d41_axi_ids[axi_id]; 233 } 234 235 dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n", 236 client, axi_id, (long long)vio_addr, 237 ((intsts & V3D_HUB_INT_MMU_WRV) ? 238 ", write violation" : ""), 239 ((intsts & V3D_HUB_INT_MMU_PTI) ? 240 ", pte invalid" : ""), 241 ((intsts & V3D_HUB_INT_MMU_CAP) ? 242 ", cap exceeded" : "")); 243 status = IRQ_HANDLED; 244 } 245 246 if (v3d->ver >= 71 && (intsts & V3D_V7_HUB_INT_GMPV)) { 247 dev_err(v3d->drm.dev, "GMP Violation\n"); 248 status = IRQ_HANDLED; 249 } 250 251 return status; 252 } 253 254 int 255 v3d_irq_init(struct v3d_dev *v3d) 256 { 257 int irq1, ret, core; 258 259 INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work); 260 261 /* Clear any pending interrupts someone might have left around 262 * for us. 263 */ 264 for (core = 0; core < v3d->cores; core++) 265 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver)); 266 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver)); 267 268 irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1); 269 if (irq1 == -EPROBE_DEFER) 270 return irq1; 271 if (irq1 > 0) { 272 ret = devm_request_irq(v3d->drm.dev, irq1, 273 v3d_irq, IRQF_SHARED, 274 "v3d_core0", v3d); 275 if (ret) 276 goto fail; 277 ret = devm_request_irq(v3d->drm.dev, 278 platform_get_irq(v3d_to_pdev(v3d), 0), 279 v3d_hub_irq, IRQF_SHARED, 280 "v3d_hub", v3d); 281 if (ret) 282 goto fail; 283 } else { 284 v3d->single_irq_line = true; 285 286 ret = devm_request_irq(v3d->drm.dev, 287 platform_get_irq(v3d_to_pdev(v3d), 0), 288 v3d_irq, IRQF_SHARED, 289 "v3d", v3d); 290 if (ret) 291 goto fail; 292 } 293 294 v3d_irq_enable(v3d); 295 return 0; 296 297 fail: 298 if (ret != -EPROBE_DEFER) 299 dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret); 300 return ret; 301 } 302 303 void 304 v3d_irq_enable(struct v3d_dev *v3d) 305 { 306 int core; 307 308 /* Enable our set of interrupts, masking out any others. */ 309 for (core = 0; core < v3d->cores; core++) { 310 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS(v3d->ver)); 311 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS(v3d->ver)); 312 } 313 314 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS(v3d->ver)); 315 V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS(v3d->ver)); 316 } 317 318 void 319 v3d_irq_disable(struct v3d_dev *v3d) 320 { 321 int core; 322 323 /* Disable all interrupts. */ 324 for (core = 0; core < v3d->cores; core++) 325 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0); 326 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); 327 328 /* Clear any pending interrupts we might have left. */ 329 for (core = 0; core < v3d->cores; core++) 330 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver)); 331 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver)); 332 333 cancel_work_sync(&v3d->overflow_mem_work); 334 } 335 336 /** Reinitializes interrupt registers when a GPU reset is performed. */ 337 void v3d_irq_reset(struct v3d_dev *v3d) 338 { 339 v3d_irq_enable(v3d); 340 } 341