157692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+
257692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */
357692c94SEric Anholt
457692c94SEric Anholt /**
557692c94SEric Anholt * DOC: Interrupt management for the V3D engine
657692c94SEric Anholt *
7d223f98fSEric Anholt * When we take a bin, render, TFU done, or CSD done interrupt, we
8d223f98fSEric Anholt * need to signal the fence for that job so that the scheduler can
9d223f98fSEric Anholt * queue up the next one and unblock any waiters.
1057692c94SEric Anholt *
1157692c94SEric Anholt * When we take the binner out of memory interrupt, we need to
1257692c94SEric Anholt * allocate some new memory and pass it to the binner so that the
1357692c94SEric Anholt * current job can make progress.
1457692c94SEric Anholt */
1557692c94SEric Anholt
16220989e7SSam Ravnborg #include <linux/platform_device.h>
1709a93cc4SMaíra Canal #include <linux/sched/clock.h>
18220989e7SSam Ravnborg
1957692c94SEric Anholt #include "v3d_drv.h"
2057692c94SEric Anholt #include "v3d_regs.h"
2155a9b748SEric Anholt #include "v3d_trace.h"
2257692c94SEric Anholt
230ad5bc1cSIago Toral Quiroga #define V3D_CORE_IRQS(ver) ((u32)(V3D_INT_OUTOMEM | \
2457692c94SEric Anholt V3D_INT_FLDONE | \
2557692c94SEric Anholt V3D_INT_FRDONE | \
260ad5bc1cSIago Toral Quiroga V3D_INT_CSDDONE(ver) | \
270ad5bc1cSIago Toral Quiroga (ver < 71 ? V3D_INT_GMPV : 0)))
2857692c94SEric Anholt
290ad5bc1cSIago Toral Quiroga #define V3D_HUB_IRQS(ver) ((u32)(V3D_HUB_INT_MMU_WRV | \
3057692c94SEric Anholt V3D_HUB_INT_MMU_PTI | \
311584f16cSEric Anholt V3D_HUB_INT_MMU_CAP | \
320ad5bc1cSIago Toral Quiroga V3D_HUB_INT_TFUC | \
330ad5bc1cSIago Toral Quiroga (ver >= 71 ? V3D_V7_HUB_INT_GMPV : 0)))
3457692c94SEric Anholt
35eea9b97bSEric Anholt static irqreturn_t
36eea9b97bSEric Anholt v3d_hub_irq(int irq, void *arg);
37eea9b97bSEric Anholt
3857692c94SEric Anholt static void
v3d_overflow_mem_work(struct work_struct * work)3957692c94SEric Anholt v3d_overflow_mem_work(struct work_struct *work)
4057692c94SEric Anholt {
4157692c94SEric Anholt struct v3d_dev *v3d =
4257692c94SEric Anholt container_of(work, struct v3d_dev, overflow_mem_work);
4357692c94SEric Anholt struct drm_device *dev = &v3d->drm;
4457692c94SEric Anholt struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024);
4540609d48SEric Anholt struct drm_gem_object *obj;
4657692c94SEric Anholt unsigned long irqflags;
4757692c94SEric Anholt
4857692c94SEric Anholt if (IS_ERR(bo)) {
4957692c94SEric Anholt DRM_ERROR("Couldn't allocate binner overflow mem\n");
5057692c94SEric Anholt return;
5157692c94SEric Anholt }
5240609d48SEric Anholt obj = &bo->base.base;
5357692c94SEric Anholt
5457692c94SEric Anholt /* We lost a race, and our work task came in after the bin job
5557692c94SEric Anholt * completed and exited. This can happen because the HW
5657692c94SEric Anholt * signals OOM before it's fully OOM, so the binner might just
5757692c94SEric Anholt * barely complete.
5857692c94SEric Anholt *
5957692c94SEric Anholt * If we lose the race and our work task comes in after a new
6057692c94SEric Anholt * bin job got scheduled, that's fine. We'll just give them
6157692c94SEric Anholt * some binner pool anyway.
6257692c94SEric Anholt */
6357692c94SEric Anholt spin_lock_irqsave(&v3d->job_lock, irqflags);
6457692c94SEric Anholt if (!v3d->bin_job) {
6557692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags);
6657692c94SEric Anholt goto out;
6757692c94SEric Anholt }
6857692c94SEric Anholt
6940609d48SEric Anholt drm_gem_object_get(obj);
70a783a09eSEric Anholt list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list);
7157692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags);
7257692c94SEric Anholt
7351b76c1fSMaíra Canal V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << V3D_MMU_PAGE_SHIFT);
7440609d48SEric Anholt V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size);
7557692c94SEric Anholt
7657692c94SEric Anholt out:
772b86189eSEmil Velikov drm_gem_object_put(obj);
7857692c94SEric Anholt }
7957692c94SEric Anholt
8057692c94SEric Anholt static irqreturn_t
v3d_irq(int irq,void * arg)8157692c94SEric Anholt v3d_irq(int irq, void *arg)
8257692c94SEric Anholt {
8357692c94SEric Anholt struct v3d_dev *v3d = arg;
8457692c94SEric Anholt u32 intsts;
8557692c94SEric Anholt irqreturn_t status = IRQ_NONE;
8657692c94SEric Anholt
8757692c94SEric Anholt intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS);
8857692c94SEric Anholt
8957692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */
9057692c94SEric Anholt V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts);
9157692c94SEric Anholt
9257692c94SEric Anholt if (intsts & V3D_INT_OUTOMEM) {
9357692c94SEric Anholt /* Note that the OOM status is edge signaled, so the
9457692c94SEric Anholt * interrupt won't happen again until the we actually
95ad8d68b2SEric Anholt * add more memory. Also, as of V3D 4.1, FLDONE won't
96ad8d68b2SEric Anholt * be reported until any OOM state has been cleared.
9757692c94SEric Anholt */
9857692c94SEric Anholt schedule_work(&v3d->overflow_mem_work);
9957692c94SEric Anholt status = IRQ_HANDLED;
10057692c94SEric Anholt }
10157692c94SEric Anholt
10257692c94SEric Anholt if (intsts & V3D_INT_FLDONE) {
10355a9b748SEric Anholt struct v3d_fence *fence =
104a783a09eSEric Anholt to_v3d_fence(v3d->bin_job->base.irq_fence);
10509a93cc4SMaíra Canal
106*52ce9776SMaíra Canal v3d_job_update_stats(&v3d->bin_job->base, V3D_BIN);
10755a9b748SEric Anholt trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
10855a9b748SEric Anholt dma_fence_signal(&fence->base);
10957692c94SEric Anholt status = IRQ_HANDLED;
11057692c94SEric Anholt }
11157692c94SEric Anholt
11257692c94SEric Anholt if (intsts & V3D_INT_FRDONE) {
11355a9b748SEric Anholt struct v3d_fence *fence =
114a783a09eSEric Anholt to_v3d_fence(v3d->render_job->base.irq_fence);
11509a93cc4SMaíra Canal
116*52ce9776SMaíra Canal v3d_job_update_stats(&v3d->render_job->base, V3D_RENDER);
11755a9b748SEric Anholt trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
11855a9b748SEric Anholt dma_fence_signal(&fence->base);
11957692c94SEric Anholt status = IRQ_HANDLED;
12057692c94SEric Anholt }
12157692c94SEric Anholt
1220ad5bc1cSIago Toral Quiroga if (intsts & V3D_INT_CSDDONE(v3d->ver)) {
123d223f98fSEric Anholt struct v3d_fence *fence =
124d223f98fSEric Anholt to_v3d_fence(v3d->csd_job->base.irq_fence);
12509a93cc4SMaíra Canal
126*52ce9776SMaíra Canal v3d_job_update_stats(&v3d->csd_job->base, V3D_CSD);
127d223f98fSEric Anholt trace_v3d_csd_irq(&v3d->drm, fence->seqno);
128d223f98fSEric Anholt dma_fence_signal(&fence->base);
129d223f98fSEric Anholt status = IRQ_HANDLED;
130d223f98fSEric Anholt }
131d223f98fSEric Anholt
13257692c94SEric Anholt /* We shouldn't be triggering these if we have GMP in
13357692c94SEric Anholt * always-allowed mode.
13457692c94SEric Anholt */
1350ad5bc1cSIago Toral Quiroga if (v3d->ver < 71 && (intsts & V3D_INT_GMPV))
136bc662528SDaniel Vetter dev_err(v3d->drm.dev, "GMP violation\n");
13757692c94SEric Anholt
138eea9b97bSEric Anholt /* V3D 4.2 wires the hub and core IRQs together, so if we &
139eea9b97bSEric Anholt * didn't see the common one then check hub for MMU IRQs.
140eea9b97bSEric Anholt */
141eea9b97bSEric Anholt if (v3d->single_irq_line && status == IRQ_NONE)
142eea9b97bSEric Anholt return v3d_hub_irq(irq, arg);
143eea9b97bSEric Anholt
14457692c94SEric Anholt return status;
14557692c94SEric Anholt }
14657692c94SEric Anholt
14757692c94SEric Anholt static irqreturn_t
v3d_hub_irq(int irq,void * arg)14857692c94SEric Anholt v3d_hub_irq(int irq, void *arg)
14957692c94SEric Anholt {
15057692c94SEric Anholt struct v3d_dev *v3d = arg;
15157692c94SEric Anholt u32 intsts;
15257692c94SEric Anholt irqreturn_t status = IRQ_NONE;
15357692c94SEric Anholt
15457692c94SEric Anholt intsts = V3D_READ(V3D_HUB_INT_STS);
15557692c94SEric Anholt
15657692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */
15757692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, intsts);
15857692c94SEric Anholt
1591584f16cSEric Anholt if (intsts & V3D_HUB_INT_TFUC) {
16055a9b748SEric Anholt struct v3d_fence *fence =
161a783a09eSEric Anholt to_v3d_fence(v3d->tfu_job->base.irq_fence);
16209a93cc4SMaíra Canal
163*52ce9776SMaíra Canal v3d_job_update_stats(&v3d->tfu_job->base, V3D_TFU);
16455a9b748SEric Anholt trace_v3d_tfu_irq(&v3d->drm, fence->seqno);
16555a9b748SEric Anholt dma_fence_signal(&fence->base);
1661584f16cSEric Anholt status = IRQ_HANDLED;
1671584f16cSEric Anholt }
1681584f16cSEric Anholt
16957692c94SEric Anholt if (intsts & (V3D_HUB_INT_MMU_WRV |
17057692c94SEric Anholt V3D_HUB_INT_MMU_PTI |
17157692c94SEric Anholt V3D_HUB_INT_MMU_CAP)) {
17257692c94SEric Anholt u32 axi_id = V3D_READ(V3D_MMU_VIO_ID);
17338c2c791SEric Anholt u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) <<
17438c2c791SEric Anholt (v3d->va_width - 32));
17538c2c791SEric Anholt static const char *const v3d41_axi_ids[] = {
17638c2c791SEric Anholt "L2T",
17738c2c791SEric Anholt "PTB",
17838c2c791SEric Anholt "PSE",
17938c2c791SEric Anholt "TLB",
18038c2c791SEric Anholt "CLE",
18138c2c791SEric Anholt "TFU",
18238c2c791SEric Anholt "MMU",
18338c2c791SEric Anholt "GMP",
18438c2c791SEric Anholt };
18538c2c791SEric Anholt const char *client = "?";
18657692c94SEric Anholt
187545d9d78SPhil Elwell V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
18838c2c791SEric Anholt
18938c2c791SEric Anholt if (v3d->ver >= 41) {
19038c2c791SEric Anholt axi_id = axi_id >> 5;
19138c2c791SEric Anholt if (axi_id < ARRAY_SIZE(v3d41_axi_ids))
19238c2c791SEric Anholt client = v3d41_axi_ids[axi_id];
19338c2c791SEric Anholt }
19438c2c791SEric Anholt
195bc662528SDaniel Vetter dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n",
19638c2c791SEric Anholt client, axi_id, (long long)vio_addr,
19757692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_WRV) ?
19857692c94SEric Anholt ", write violation" : ""),
19957692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_PTI) ?
20057692c94SEric Anholt ", pte invalid" : ""),
20157692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_CAP) ?
20257692c94SEric Anholt ", cap exceeded" : ""));
20357692c94SEric Anholt status = IRQ_HANDLED;
20457692c94SEric Anholt }
20557692c94SEric Anholt
2060ad5bc1cSIago Toral Quiroga if (v3d->ver >= 71 && (intsts & V3D_V7_HUB_INT_GMPV)) {
2070ad5bc1cSIago Toral Quiroga dev_err(v3d->drm.dev, "GMP Violation\n");
2080ad5bc1cSIago Toral Quiroga status = IRQ_HANDLED;
2090ad5bc1cSIago Toral Quiroga }
2100ad5bc1cSIago Toral Quiroga
21157692c94SEric Anholt return status;
21257692c94SEric Anholt }
21357692c94SEric Anholt
214fc227715SEric Anholt int
v3d_irq_init(struct v3d_dev * v3d)21557692c94SEric Anholt v3d_irq_init(struct v3d_dev *v3d)
21657692c94SEric Anholt {
217eea9b97bSEric Anholt int irq1, ret, core;
21857692c94SEric Anholt
21957692c94SEric Anholt INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work);
22057692c94SEric Anholt
22157692c94SEric Anholt /* Clear any pending interrupts someone might have left around
22257692c94SEric Anholt * for us.
22357692c94SEric Anholt */
22457692c94SEric Anholt for (core = 0; core < v3d->cores; core++)
2250ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));
2260ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));
22757692c94SEric Anholt
228f4f3beb7SNicolas Saenz Julienne irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);
229eea9b97bSEric Anholt if (irq1 == -EPROBE_DEFER)
230eea9b97bSEric Anholt return irq1;
231eea9b97bSEric Anholt if (irq1 > 0) {
232bc662528SDaniel Vetter ret = devm_request_irq(v3d->drm.dev, irq1,
233eea9b97bSEric Anholt v3d_irq, IRQF_SHARED,
234eea9b97bSEric Anholt "v3d_core0", v3d);
235eea9b97bSEric Anholt if (ret)
236eea9b97bSEric Anholt goto fail;
2370df3ac76SDaniel Vetter ret = devm_request_irq(v3d->drm.dev,
2380df3ac76SDaniel Vetter platform_get_irq(v3d_to_pdev(v3d), 0),
23957692c94SEric Anholt v3d_hub_irq, IRQF_SHARED,
24057692c94SEric Anholt "v3d_hub", v3d);
241fc227715SEric Anholt if (ret)
242fc227715SEric Anholt goto fail;
243eea9b97bSEric Anholt } else {
244eea9b97bSEric Anholt v3d->single_irq_line = true;
245fc227715SEric Anholt
2460df3ac76SDaniel Vetter ret = devm_request_irq(v3d->drm.dev,
2470df3ac76SDaniel Vetter platform_get_irq(v3d_to_pdev(v3d), 0),
24857692c94SEric Anholt v3d_irq, IRQF_SHARED,
249eea9b97bSEric Anholt "v3d", v3d);
25057692c94SEric Anholt if (ret)
251fc227715SEric Anholt goto fail;
252eea9b97bSEric Anholt }
25357692c94SEric Anholt
25457692c94SEric Anholt v3d_irq_enable(v3d);
255fc227715SEric Anholt return 0;
256fc227715SEric Anholt
257fc227715SEric Anholt fail:
258fc227715SEric Anholt if (ret != -EPROBE_DEFER)
259bc662528SDaniel Vetter dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret);
260fc227715SEric Anholt return ret;
26157692c94SEric Anholt }
26257692c94SEric Anholt
26357692c94SEric Anholt void
v3d_irq_enable(struct v3d_dev * v3d)26457692c94SEric Anholt v3d_irq_enable(struct v3d_dev *v3d)
26557692c94SEric Anholt {
26657692c94SEric Anholt int core;
26757692c94SEric Anholt
26857692c94SEric Anholt /* Enable our set of interrupts, masking out any others. */
26957692c94SEric Anholt for (core = 0; core < v3d->cores; core++) {
2700ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS(v3d->ver));
2710ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS(v3d->ver));
27257692c94SEric Anholt }
27357692c94SEric Anholt
2740ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS(v3d->ver));
2750ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS(v3d->ver));
27657692c94SEric Anholt }
27757692c94SEric Anholt
27857692c94SEric Anholt void
v3d_irq_disable(struct v3d_dev * v3d)27957692c94SEric Anholt v3d_irq_disable(struct v3d_dev *v3d)
28057692c94SEric Anholt {
28157692c94SEric Anholt int core;
28257692c94SEric Anholt
28357692c94SEric Anholt /* Disable all interrupts. */
28457692c94SEric Anholt for (core = 0; core < v3d->cores; core++)
28557692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0);
28657692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0);
28757692c94SEric Anholt
28857692c94SEric Anholt /* Clear any pending interrupts we might have left. */
28957692c94SEric Anholt for (core = 0; core < v3d->cores; core++)
2900ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));
2910ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));
29257692c94SEric Anholt
29357692c94SEric Anholt cancel_work_sync(&v3d->overflow_mem_work);
29457692c94SEric Anholt }
29557692c94SEric Anholt
29657692c94SEric Anholt /** Reinitializes interrupt registers when a GPU reset is performed. */
v3d_irq_reset(struct v3d_dev * v3d)29757692c94SEric Anholt void v3d_irq_reset(struct v3d_dev *v3d)
29857692c94SEric Anholt {
29957692c94SEric Anholt v3d_irq_enable(v3d);
30057692c94SEric Anholt }
301