157692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+ 257692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */ 357692c94SEric Anholt 457692c94SEric Anholt /** 557692c94SEric Anholt * DOC: Interrupt management for the V3D engine 657692c94SEric Anholt * 7*d223f98fSEric Anholt * When we take a bin, render, TFU done, or CSD done interrupt, we 8*d223f98fSEric Anholt * need to signal the fence for that job so that the scheduler can 9*d223f98fSEric Anholt * queue up the next one and unblock any waiters. 1057692c94SEric Anholt * 1157692c94SEric Anholt * When we take the binner out of memory interrupt, we need to 1257692c94SEric Anholt * allocate some new memory and pass it to the binner so that the 1357692c94SEric Anholt * current job can make progress. 1457692c94SEric Anholt */ 1557692c94SEric Anholt 1657692c94SEric Anholt #include "v3d_drv.h" 1757692c94SEric Anholt #include "v3d_regs.h" 1855a9b748SEric Anholt #include "v3d_trace.h" 1957692c94SEric Anholt 2057692c94SEric Anholt #define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM | \ 2157692c94SEric Anholt V3D_INT_FLDONE | \ 2257692c94SEric Anholt V3D_INT_FRDONE | \ 23*d223f98fSEric Anholt V3D_INT_CSDDONE | \ 2457692c94SEric Anholt V3D_INT_GMPV)) 2557692c94SEric Anholt 2657692c94SEric Anholt #define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \ 2757692c94SEric Anholt V3D_HUB_INT_MMU_PTI | \ 281584f16cSEric Anholt V3D_HUB_INT_MMU_CAP | \ 291584f16cSEric Anholt V3D_HUB_INT_TFUC)) 3057692c94SEric Anholt 31eea9b97bSEric Anholt static irqreturn_t 32eea9b97bSEric Anholt v3d_hub_irq(int irq, void *arg); 33eea9b97bSEric Anholt 3457692c94SEric Anholt static void 3557692c94SEric Anholt v3d_overflow_mem_work(struct work_struct *work) 3657692c94SEric Anholt { 3757692c94SEric Anholt struct v3d_dev *v3d = 3857692c94SEric Anholt container_of(work, struct v3d_dev, overflow_mem_work); 3957692c94SEric Anholt struct drm_device *dev = &v3d->drm; 4057692c94SEric Anholt struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024); 4140609d48SEric Anholt struct drm_gem_object *obj; 4257692c94SEric Anholt unsigned long irqflags; 4357692c94SEric Anholt 4457692c94SEric Anholt if (IS_ERR(bo)) { 4557692c94SEric Anholt DRM_ERROR("Couldn't allocate binner overflow mem\n"); 4657692c94SEric Anholt return; 4757692c94SEric Anholt } 4840609d48SEric Anholt obj = &bo->base.base; 4957692c94SEric Anholt 5057692c94SEric Anholt /* We lost a race, and our work task came in after the bin job 5157692c94SEric Anholt * completed and exited. This can happen because the HW 5257692c94SEric Anholt * signals OOM before it's fully OOM, so the binner might just 5357692c94SEric Anholt * barely complete. 5457692c94SEric Anholt * 5557692c94SEric Anholt * If we lose the race and our work task comes in after a new 5657692c94SEric Anholt * bin job got scheduled, that's fine. We'll just give them 5757692c94SEric Anholt * some binner pool anyway. 5857692c94SEric Anholt */ 5957692c94SEric Anholt spin_lock_irqsave(&v3d->job_lock, irqflags); 6057692c94SEric Anholt if (!v3d->bin_job) { 6157692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags); 6257692c94SEric Anholt goto out; 6357692c94SEric Anholt } 6457692c94SEric Anholt 6540609d48SEric Anholt drm_gem_object_get(obj); 66a783a09eSEric Anholt list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list); 6757692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags); 6857692c94SEric Anholt 6957692c94SEric Anholt V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT); 7040609d48SEric Anholt V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size); 7157692c94SEric Anholt 7257692c94SEric Anholt out: 7340609d48SEric Anholt drm_gem_object_put_unlocked(obj); 7457692c94SEric Anholt } 7557692c94SEric Anholt 7657692c94SEric Anholt static irqreturn_t 7757692c94SEric Anholt v3d_irq(int irq, void *arg) 7857692c94SEric Anholt { 7957692c94SEric Anholt struct v3d_dev *v3d = arg; 8057692c94SEric Anholt u32 intsts; 8157692c94SEric Anholt irqreturn_t status = IRQ_NONE; 8257692c94SEric Anholt 8357692c94SEric Anholt intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS); 8457692c94SEric Anholt 8557692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */ 8657692c94SEric Anholt V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts); 8757692c94SEric Anholt 8857692c94SEric Anholt if (intsts & V3D_INT_OUTOMEM) { 8957692c94SEric Anholt /* Note that the OOM status is edge signaled, so the 9057692c94SEric Anholt * interrupt won't happen again until the we actually 91ad8d68b2SEric Anholt * add more memory. Also, as of V3D 4.1, FLDONE won't 92ad8d68b2SEric Anholt * be reported until any OOM state has been cleared. 9357692c94SEric Anholt */ 9457692c94SEric Anholt schedule_work(&v3d->overflow_mem_work); 9557692c94SEric Anholt status = IRQ_HANDLED; 9657692c94SEric Anholt } 9757692c94SEric Anholt 9857692c94SEric Anholt if (intsts & V3D_INT_FLDONE) { 9955a9b748SEric Anholt struct v3d_fence *fence = 100a783a09eSEric Anholt to_v3d_fence(v3d->bin_job->base.irq_fence); 10155a9b748SEric Anholt 10255a9b748SEric Anholt trace_v3d_bcl_irq(&v3d->drm, fence->seqno); 10355a9b748SEric Anholt dma_fence_signal(&fence->base); 10457692c94SEric Anholt status = IRQ_HANDLED; 10557692c94SEric Anholt } 10657692c94SEric Anholt 10757692c94SEric Anholt if (intsts & V3D_INT_FRDONE) { 10855a9b748SEric Anholt struct v3d_fence *fence = 109a783a09eSEric Anholt to_v3d_fence(v3d->render_job->base.irq_fence); 11055a9b748SEric Anholt 11155a9b748SEric Anholt trace_v3d_rcl_irq(&v3d->drm, fence->seqno); 11255a9b748SEric Anholt dma_fence_signal(&fence->base); 11357692c94SEric Anholt status = IRQ_HANDLED; 11457692c94SEric Anholt } 11557692c94SEric Anholt 116*d223f98fSEric Anholt if (intsts & V3D_INT_CSDDONE) { 117*d223f98fSEric Anholt struct v3d_fence *fence = 118*d223f98fSEric Anholt to_v3d_fence(v3d->csd_job->base.irq_fence); 119*d223f98fSEric Anholt 120*d223f98fSEric Anholt trace_v3d_csd_irq(&v3d->drm, fence->seqno); 121*d223f98fSEric Anholt dma_fence_signal(&fence->base); 122*d223f98fSEric Anholt status = IRQ_HANDLED; 123*d223f98fSEric Anholt } 124*d223f98fSEric Anholt 12557692c94SEric Anholt /* We shouldn't be triggering these if we have GMP in 12657692c94SEric Anholt * always-allowed mode. 12757692c94SEric Anholt */ 12857692c94SEric Anholt if (intsts & V3D_INT_GMPV) 12957692c94SEric Anholt dev_err(v3d->dev, "GMP violation\n"); 13057692c94SEric Anholt 131eea9b97bSEric Anholt /* V3D 4.2 wires the hub and core IRQs together, so if we & 132eea9b97bSEric Anholt * didn't see the common one then check hub for MMU IRQs. 133eea9b97bSEric Anholt */ 134eea9b97bSEric Anholt if (v3d->single_irq_line && status == IRQ_NONE) 135eea9b97bSEric Anholt return v3d_hub_irq(irq, arg); 136eea9b97bSEric Anholt 13757692c94SEric Anholt return status; 13857692c94SEric Anholt } 13957692c94SEric Anholt 14057692c94SEric Anholt static irqreturn_t 14157692c94SEric Anholt v3d_hub_irq(int irq, void *arg) 14257692c94SEric Anholt { 14357692c94SEric Anholt struct v3d_dev *v3d = arg; 14457692c94SEric Anholt u32 intsts; 14557692c94SEric Anholt irqreturn_t status = IRQ_NONE; 14657692c94SEric Anholt 14757692c94SEric Anholt intsts = V3D_READ(V3D_HUB_INT_STS); 14857692c94SEric Anholt 14957692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */ 15057692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, intsts); 15157692c94SEric Anholt 1521584f16cSEric Anholt if (intsts & V3D_HUB_INT_TFUC) { 15355a9b748SEric Anholt struct v3d_fence *fence = 154a783a09eSEric Anholt to_v3d_fence(v3d->tfu_job->base.irq_fence); 15555a9b748SEric Anholt 15655a9b748SEric Anholt trace_v3d_tfu_irq(&v3d->drm, fence->seqno); 15755a9b748SEric Anholt dma_fence_signal(&fence->base); 1581584f16cSEric Anholt status = IRQ_HANDLED; 1591584f16cSEric Anholt } 1601584f16cSEric Anholt 16157692c94SEric Anholt if (intsts & (V3D_HUB_INT_MMU_WRV | 16257692c94SEric Anholt V3D_HUB_INT_MMU_PTI | 16357692c94SEric Anholt V3D_HUB_INT_MMU_CAP)) { 16457692c94SEric Anholt u32 axi_id = V3D_READ(V3D_MMU_VIO_ID); 16557692c94SEric Anholt u64 vio_addr = (u64)V3D_READ(V3D_MMU_VIO_ADDR) << 8; 16657692c94SEric Anholt 16757692c94SEric Anholt dev_err(v3d->dev, "MMU error from client %d at 0x%08llx%s%s%s\n", 16857692c94SEric Anholt axi_id, (long long)vio_addr, 16957692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_WRV) ? 17057692c94SEric Anholt ", write violation" : ""), 17157692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_PTI) ? 17257692c94SEric Anholt ", pte invalid" : ""), 17357692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_CAP) ? 17457692c94SEric Anholt ", cap exceeded" : "")); 17557692c94SEric Anholt status = IRQ_HANDLED; 17657692c94SEric Anholt } 17757692c94SEric Anholt 17857692c94SEric Anholt return status; 17957692c94SEric Anholt } 18057692c94SEric Anholt 181fc227715SEric Anholt int 18257692c94SEric Anholt v3d_irq_init(struct v3d_dev *v3d) 18357692c94SEric Anholt { 184eea9b97bSEric Anholt int irq1, ret, core; 18557692c94SEric Anholt 18657692c94SEric Anholt INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work); 18757692c94SEric Anholt 18857692c94SEric Anholt /* Clear any pending interrupts someone might have left around 18957692c94SEric Anholt * for us. 19057692c94SEric Anholt */ 19157692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 19257692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS); 19357692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); 19457692c94SEric Anholt 195eea9b97bSEric Anholt irq1 = platform_get_irq(v3d->pdev, 1); 196eea9b97bSEric Anholt if (irq1 == -EPROBE_DEFER) 197eea9b97bSEric Anholt return irq1; 198eea9b97bSEric Anholt if (irq1 > 0) { 199eea9b97bSEric Anholt ret = devm_request_irq(v3d->dev, irq1, 200eea9b97bSEric Anholt v3d_irq, IRQF_SHARED, 201eea9b97bSEric Anholt "v3d_core0", v3d); 202eea9b97bSEric Anholt if (ret) 203eea9b97bSEric Anholt goto fail; 20457692c94SEric Anholt ret = devm_request_irq(v3d->dev, platform_get_irq(v3d->pdev, 0), 20557692c94SEric Anholt v3d_hub_irq, IRQF_SHARED, 20657692c94SEric Anholt "v3d_hub", v3d); 207fc227715SEric Anholt if (ret) 208fc227715SEric Anholt goto fail; 209eea9b97bSEric Anholt } else { 210eea9b97bSEric Anholt v3d->single_irq_line = true; 211fc227715SEric Anholt 212eea9b97bSEric Anholt ret = devm_request_irq(v3d->dev, platform_get_irq(v3d->pdev, 0), 21357692c94SEric Anholt v3d_irq, IRQF_SHARED, 214eea9b97bSEric Anholt "v3d", v3d); 21557692c94SEric Anholt if (ret) 216fc227715SEric Anholt goto fail; 217eea9b97bSEric Anholt } 21857692c94SEric Anholt 21957692c94SEric Anholt v3d_irq_enable(v3d); 220fc227715SEric Anholt return 0; 221fc227715SEric Anholt 222fc227715SEric Anholt fail: 223fc227715SEric Anholt if (ret != -EPROBE_DEFER) 224fc227715SEric Anholt dev_err(v3d->dev, "IRQ setup failed: %d\n", ret); 225fc227715SEric Anholt return ret; 22657692c94SEric Anholt } 22757692c94SEric Anholt 22857692c94SEric Anholt void 22957692c94SEric Anholt v3d_irq_enable(struct v3d_dev *v3d) 23057692c94SEric Anholt { 23157692c94SEric Anholt int core; 23257692c94SEric Anholt 23357692c94SEric Anholt /* Enable our set of interrupts, masking out any others. */ 23457692c94SEric Anholt for (core = 0; core < v3d->cores; core++) { 23557692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS); 23657692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS); 23757692c94SEric Anholt } 23857692c94SEric Anholt 23957692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS); 24057692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS); 24157692c94SEric Anholt } 24257692c94SEric Anholt 24357692c94SEric Anholt void 24457692c94SEric Anholt v3d_irq_disable(struct v3d_dev *v3d) 24557692c94SEric Anholt { 24657692c94SEric Anholt int core; 24757692c94SEric Anholt 24857692c94SEric Anholt /* Disable all interrupts. */ 24957692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 25057692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0); 25157692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); 25257692c94SEric Anholt 25357692c94SEric Anholt /* Clear any pending interrupts we might have left. */ 25457692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 25557692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS); 25657692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); 25757692c94SEric Anholt 25857692c94SEric Anholt cancel_work_sync(&v3d->overflow_mem_work); 25957692c94SEric Anholt } 26057692c94SEric Anholt 26157692c94SEric Anholt /** Reinitializes interrupt registers when a GPU reset is performed. */ 26257692c94SEric Anholt void v3d_irq_reset(struct v3d_dev *v3d) 26357692c94SEric Anholt { 26457692c94SEric Anholt v3d_irq_enable(v3d); 26557692c94SEric Anholt } 266