157692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+ 257692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */ 357692c94SEric Anholt 457692c94SEric Anholt /** 557692c94SEric Anholt * DOC: Interrupt management for the V3D engine 657692c94SEric Anholt * 71584f16cSEric Anholt * When we take a bin, render, or TFU done interrupt, we need to 81584f16cSEric Anholt * signal the fence for that job so that the scheduler can queue up 957692c94SEric Anholt * the next one and unblock any waiters. 1057692c94SEric Anholt * 1157692c94SEric Anholt * When we take the binner out of memory interrupt, we need to 1257692c94SEric Anholt * allocate some new memory and pass it to the binner so that the 1357692c94SEric Anholt * current job can make progress. 1457692c94SEric Anholt */ 1557692c94SEric Anholt 1657692c94SEric Anholt #include "v3d_drv.h" 1757692c94SEric Anholt #include "v3d_regs.h" 1855a9b748SEric Anholt #include "v3d_trace.h" 1957692c94SEric Anholt 2057692c94SEric Anholt #define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM | \ 2157692c94SEric Anholt V3D_INT_FLDONE | \ 2257692c94SEric Anholt V3D_INT_FRDONE | \ 2357692c94SEric Anholt V3D_INT_GMPV)) 2457692c94SEric Anholt 2557692c94SEric Anholt #define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \ 2657692c94SEric Anholt V3D_HUB_INT_MMU_PTI | \ 271584f16cSEric Anholt V3D_HUB_INT_MMU_CAP | \ 281584f16cSEric Anholt V3D_HUB_INT_TFUC)) 2957692c94SEric Anholt 30eea9b97bSEric Anholt static irqreturn_t 31eea9b97bSEric Anholt v3d_hub_irq(int irq, void *arg); 32eea9b97bSEric Anholt 3357692c94SEric Anholt static void 3457692c94SEric Anholt v3d_overflow_mem_work(struct work_struct *work) 3557692c94SEric Anholt { 3657692c94SEric Anholt struct v3d_dev *v3d = 3757692c94SEric Anholt container_of(work, struct v3d_dev, overflow_mem_work); 3857692c94SEric Anholt struct drm_device *dev = &v3d->drm; 3957692c94SEric Anholt struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024); 4040609d48SEric Anholt struct drm_gem_object *obj; 4157692c94SEric Anholt unsigned long irqflags; 4257692c94SEric Anholt 4357692c94SEric Anholt if (IS_ERR(bo)) { 4457692c94SEric Anholt DRM_ERROR("Couldn't allocate binner overflow mem\n"); 4557692c94SEric Anholt return; 4657692c94SEric Anholt } 4740609d48SEric Anholt obj = &bo->base.base; 4857692c94SEric Anholt 4957692c94SEric Anholt /* We lost a race, and our work task came in after the bin job 5057692c94SEric Anholt * completed and exited. This can happen because the HW 5157692c94SEric Anholt * signals OOM before it's fully OOM, so the binner might just 5257692c94SEric Anholt * barely complete. 5357692c94SEric Anholt * 5457692c94SEric Anholt * If we lose the race and our work task comes in after a new 5557692c94SEric Anholt * bin job got scheduled, that's fine. We'll just give them 5657692c94SEric Anholt * some binner pool anyway. 5757692c94SEric Anholt */ 5857692c94SEric Anholt spin_lock_irqsave(&v3d->job_lock, irqflags); 5957692c94SEric Anholt if (!v3d->bin_job) { 6057692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags); 6157692c94SEric Anholt goto out; 6257692c94SEric Anholt } 6357692c94SEric Anholt 6440609d48SEric Anholt drm_gem_object_get(obj); 65*a783a09eSEric Anholt list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list); 6657692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags); 6757692c94SEric Anholt 6857692c94SEric Anholt V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT); 6940609d48SEric Anholt V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size); 7057692c94SEric Anholt 7157692c94SEric Anholt out: 7240609d48SEric Anholt drm_gem_object_put_unlocked(obj); 7357692c94SEric Anholt } 7457692c94SEric Anholt 7557692c94SEric Anholt static irqreturn_t 7657692c94SEric Anholt v3d_irq(int irq, void *arg) 7757692c94SEric Anholt { 7857692c94SEric Anholt struct v3d_dev *v3d = arg; 7957692c94SEric Anholt u32 intsts; 8057692c94SEric Anholt irqreturn_t status = IRQ_NONE; 8157692c94SEric Anholt 8257692c94SEric Anholt intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS); 8357692c94SEric Anholt 8457692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */ 8557692c94SEric Anholt V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts); 8657692c94SEric Anholt 8757692c94SEric Anholt if (intsts & V3D_INT_OUTOMEM) { 8857692c94SEric Anholt /* Note that the OOM status is edge signaled, so the 8957692c94SEric Anholt * interrupt won't happen again until the we actually 90ad8d68b2SEric Anholt * add more memory. Also, as of V3D 4.1, FLDONE won't 91ad8d68b2SEric Anholt * be reported until any OOM state has been cleared. 9257692c94SEric Anholt */ 9357692c94SEric Anholt schedule_work(&v3d->overflow_mem_work); 9457692c94SEric Anholt status = IRQ_HANDLED; 9557692c94SEric Anholt } 9657692c94SEric Anholt 9757692c94SEric Anholt if (intsts & V3D_INT_FLDONE) { 9855a9b748SEric Anholt struct v3d_fence *fence = 99*a783a09eSEric Anholt to_v3d_fence(v3d->bin_job->base.irq_fence); 10055a9b748SEric Anholt 10155a9b748SEric Anholt trace_v3d_bcl_irq(&v3d->drm, fence->seqno); 10255a9b748SEric Anholt dma_fence_signal(&fence->base); 10357692c94SEric Anholt status = IRQ_HANDLED; 10457692c94SEric Anholt } 10557692c94SEric Anholt 10657692c94SEric Anholt if (intsts & V3D_INT_FRDONE) { 10755a9b748SEric Anholt struct v3d_fence *fence = 108*a783a09eSEric Anholt to_v3d_fence(v3d->render_job->base.irq_fence); 10955a9b748SEric Anholt 11055a9b748SEric Anholt trace_v3d_rcl_irq(&v3d->drm, fence->seqno); 11155a9b748SEric Anholt dma_fence_signal(&fence->base); 11257692c94SEric Anholt status = IRQ_HANDLED; 11357692c94SEric Anholt } 11457692c94SEric Anholt 11557692c94SEric Anholt /* We shouldn't be triggering these if we have GMP in 11657692c94SEric Anholt * always-allowed mode. 11757692c94SEric Anholt */ 11857692c94SEric Anholt if (intsts & V3D_INT_GMPV) 11957692c94SEric Anholt dev_err(v3d->dev, "GMP violation\n"); 12057692c94SEric Anholt 121eea9b97bSEric Anholt /* V3D 4.2 wires the hub and core IRQs together, so if we & 122eea9b97bSEric Anholt * didn't see the common one then check hub for MMU IRQs. 123eea9b97bSEric Anholt */ 124eea9b97bSEric Anholt if (v3d->single_irq_line && status == IRQ_NONE) 125eea9b97bSEric Anholt return v3d_hub_irq(irq, arg); 126eea9b97bSEric Anholt 12757692c94SEric Anholt return status; 12857692c94SEric Anholt } 12957692c94SEric Anholt 13057692c94SEric Anholt static irqreturn_t 13157692c94SEric Anholt v3d_hub_irq(int irq, void *arg) 13257692c94SEric Anholt { 13357692c94SEric Anholt struct v3d_dev *v3d = arg; 13457692c94SEric Anholt u32 intsts; 13557692c94SEric Anholt irqreturn_t status = IRQ_NONE; 13657692c94SEric Anholt 13757692c94SEric Anholt intsts = V3D_READ(V3D_HUB_INT_STS); 13857692c94SEric Anholt 13957692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */ 14057692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, intsts); 14157692c94SEric Anholt 1421584f16cSEric Anholt if (intsts & V3D_HUB_INT_TFUC) { 14355a9b748SEric Anholt struct v3d_fence *fence = 144*a783a09eSEric Anholt to_v3d_fence(v3d->tfu_job->base.irq_fence); 14555a9b748SEric Anholt 14655a9b748SEric Anholt trace_v3d_tfu_irq(&v3d->drm, fence->seqno); 14755a9b748SEric Anholt dma_fence_signal(&fence->base); 1481584f16cSEric Anholt status = IRQ_HANDLED; 1491584f16cSEric Anholt } 1501584f16cSEric Anholt 15157692c94SEric Anholt if (intsts & (V3D_HUB_INT_MMU_WRV | 15257692c94SEric Anholt V3D_HUB_INT_MMU_PTI | 15357692c94SEric Anholt V3D_HUB_INT_MMU_CAP)) { 15457692c94SEric Anholt u32 axi_id = V3D_READ(V3D_MMU_VIO_ID); 15557692c94SEric Anholt u64 vio_addr = (u64)V3D_READ(V3D_MMU_VIO_ADDR) << 8; 15657692c94SEric Anholt 15757692c94SEric Anholt dev_err(v3d->dev, "MMU error from client %d at 0x%08llx%s%s%s\n", 15857692c94SEric Anholt axi_id, (long long)vio_addr, 15957692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_WRV) ? 16057692c94SEric Anholt ", write violation" : ""), 16157692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_PTI) ? 16257692c94SEric Anholt ", pte invalid" : ""), 16357692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_CAP) ? 16457692c94SEric Anholt ", cap exceeded" : "")); 16557692c94SEric Anholt status = IRQ_HANDLED; 16657692c94SEric Anholt } 16757692c94SEric Anholt 16857692c94SEric Anholt return status; 16957692c94SEric Anholt } 17057692c94SEric Anholt 171fc227715SEric Anholt int 17257692c94SEric Anholt v3d_irq_init(struct v3d_dev *v3d) 17357692c94SEric Anholt { 174eea9b97bSEric Anholt int irq1, ret, core; 17557692c94SEric Anholt 17657692c94SEric Anholt INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work); 17757692c94SEric Anholt 17857692c94SEric Anholt /* Clear any pending interrupts someone might have left around 17957692c94SEric Anholt * for us. 18057692c94SEric Anholt */ 18157692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 18257692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS); 18357692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); 18457692c94SEric Anholt 185eea9b97bSEric Anholt irq1 = platform_get_irq(v3d->pdev, 1); 186eea9b97bSEric Anholt if (irq1 == -EPROBE_DEFER) 187eea9b97bSEric Anholt return irq1; 188eea9b97bSEric Anholt if (irq1 > 0) { 189eea9b97bSEric Anholt ret = devm_request_irq(v3d->dev, irq1, 190eea9b97bSEric Anholt v3d_irq, IRQF_SHARED, 191eea9b97bSEric Anholt "v3d_core0", v3d); 192eea9b97bSEric Anholt if (ret) 193eea9b97bSEric Anholt goto fail; 19457692c94SEric Anholt ret = devm_request_irq(v3d->dev, platform_get_irq(v3d->pdev, 0), 19557692c94SEric Anholt v3d_hub_irq, IRQF_SHARED, 19657692c94SEric Anholt "v3d_hub", v3d); 197fc227715SEric Anholt if (ret) 198fc227715SEric Anholt goto fail; 199eea9b97bSEric Anholt } else { 200eea9b97bSEric Anholt v3d->single_irq_line = true; 201fc227715SEric Anholt 202eea9b97bSEric Anholt ret = devm_request_irq(v3d->dev, platform_get_irq(v3d->pdev, 0), 20357692c94SEric Anholt v3d_irq, IRQF_SHARED, 204eea9b97bSEric Anholt "v3d", v3d); 20557692c94SEric Anholt if (ret) 206fc227715SEric Anholt goto fail; 207eea9b97bSEric Anholt } 20857692c94SEric Anholt 20957692c94SEric Anholt v3d_irq_enable(v3d); 210fc227715SEric Anholt return 0; 211fc227715SEric Anholt 212fc227715SEric Anholt fail: 213fc227715SEric Anholt if (ret != -EPROBE_DEFER) 214fc227715SEric Anholt dev_err(v3d->dev, "IRQ setup failed: %d\n", ret); 215fc227715SEric Anholt return ret; 21657692c94SEric Anholt } 21757692c94SEric Anholt 21857692c94SEric Anholt void 21957692c94SEric Anholt v3d_irq_enable(struct v3d_dev *v3d) 22057692c94SEric Anholt { 22157692c94SEric Anholt int core; 22257692c94SEric Anholt 22357692c94SEric Anholt /* Enable our set of interrupts, masking out any others. */ 22457692c94SEric Anholt for (core = 0; core < v3d->cores; core++) { 22557692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS); 22657692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS); 22757692c94SEric Anholt } 22857692c94SEric Anholt 22957692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS); 23057692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS); 23157692c94SEric Anholt } 23257692c94SEric Anholt 23357692c94SEric Anholt void 23457692c94SEric Anholt v3d_irq_disable(struct v3d_dev *v3d) 23557692c94SEric Anholt { 23657692c94SEric Anholt int core; 23757692c94SEric Anholt 23857692c94SEric Anholt /* Disable all interrupts. */ 23957692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 24057692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0); 24157692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); 24257692c94SEric Anholt 24357692c94SEric Anholt /* Clear any pending interrupts we might have left. */ 24457692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 24557692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS); 24657692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); 24757692c94SEric Anholt 24857692c94SEric Anholt cancel_work_sync(&v3d->overflow_mem_work); 24957692c94SEric Anholt } 25057692c94SEric Anholt 25157692c94SEric Anholt /** Reinitializes interrupt registers when a GPU reset is performed. */ 25257692c94SEric Anholt void v3d_irq_reset(struct v3d_dev *v3d) 25357692c94SEric Anholt { 25457692c94SEric Anholt v3d_irq_enable(v3d); 25557692c94SEric Anholt } 256