157692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+ 257692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */ 357692c94SEric Anholt 457692c94SEric Anholt /** 557692c94SEric Anholt * DOC: Interrupt management for the V3D engine 657692c94SEric Anholt * 7d223f98fSEric Anholt * When we take a bin, render, TFU done, or CSD done interrupt, we 8d223f98fSEric Anholt * need to signal the fence for that job so that the scheduler can 9d223f98fSEric Anholt * queue up the next one and unblock any waiters. 1057692c94SEric Anholt * 1157692c94SEric Anholt * When we take the binner out of memory interrupt, we need to 1257692c94SEric Anholt * allocate some new memory and pass it to the binner so that the 1357692c94SEric Anholt * current job can make progress. 1457692c94SEric Anholt */ 1557692c94SEric Anholt 16220989e7SSam Ravnborg #include <linux/platform_device.h> 1709a93cc4SMaíra Canal #include <linux/sched/clock.h> 18220989e7SSam Ravnborg 1957692c94SEric Anholt #include "v3d_drv.h" 2057692c94SEric Anholt #include "v3d_regs.h" 2155a9b748SEric Anholt #include "v3d_trace.h" 2257692c94SEric Anholt 230ad5bc1cSIago Toral Quiroga #define V3D_CORE_IRQS(ver) ((u32)(V3D_INT_OUTOMEM | \ 2457692c94SEric Anholt V3D_INT_FLDONE | \ 2557692c94SEric Anholt V3D_INT_FRDONE | \ 260ad5bc1cSIago Toral Quiroga V3D_INT_CSDDONE(ver) | \ 270ad5bc1cSIago Toral Quiroga (ver < 71 ? V3D_INT_GMPV : 0))) 2857692c94SEric Anholt 290ad5bc1cSIago Toral Quiroga #define V3D_HUB_IRQS(ver) ((u32)(V3D_HUB_INT_MMU_WRV | \ 3057692c94SEric Anholt V3D_HUB_INT_MMU_PTI | \ 311584f16cSEric Anholt V3D_HUB_INT_MMU_CAP | \ 320ad5bc1cSIago Toral Quiroga V3D_HUB_INT_TFUC | \ 330ad5bc1cSIago Toral Quiroga (ver >= 71 ? V3D_V7_HUB_INT_GMPV : 0))) 3457692c94SEric Anholt 35eea9b97bSEric Anholt static irqreturn_t 36eea9b97bSEric Anholt v3d_hub_irq(int irq, void *arg); 37eea9b97bSEric Anholt 3857692c94SEric Anholt static void 3957692c94SEric Anholt v3d_overflow_mem_work(struct work_struct *work) 4057692c94SEric Anholt { 4157692c94SEric Anholt struct v3d_dev *v3d = 4257692c94SEric Anholt container_of(work, struct v3d_dev, overflow_mem_work); 4357692c94SEric Anholt struct drm_device *dev = &v3d->drm; 4457692c94SEric Anholt struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024); 4540609d48SEric Anholt struct drm_gem_object *obj; 4657692c94SEric Anholt unsigned long irqflags; 4757692c94SEric Anholt 4857692c94SEric Anholt if (IS_ERR(bo)) { 4957692c94SEric Anholt DRM_ERROR("Couldn't allocate binner overflow mem\n"); 5057692c94SEric Anholt return; 5157692c94SEric Anholt } 5240609d48SEric Anholt obj = &bo->base.base; 5357692c94SEric Anholt 5457692c94SEric Anholt /* We lost a race, and our work task came in after the bin job 5557692c94SEric Anholt * completed and exited. This can happen because the HW 5657692c94SEric Anholt * signals OOM before it's fully OOM, so the binner might just 5757692c94SEric Anholt * barely complete. 5857692c94SEric Anholt * 5957692c94SEric Anholt * If we lose the race and our work task comes in after a new 6057692c94SEric Anholt * bin job got scheduled, that's fine. We'll just give them 6157692c94SEric Anholt * some binner pool anyway. 6257692c94SEric Anholt */ 6357692c94SEric Anholt spin_lock_irqsave(&v3d->job_lock, irqflags); 6457692c94SEric Anholt if (!v3d->bin_job) { 6557692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags); 6657692c94SEric Anholt goto out; 6757692c94SEric Anholt } 6857692c94SEric Anholt 6940609d48SEric Anholt drm_gem_object_get(obj); 70a783a09eSEric Anholt list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list); 7157692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags); 7257692c94SEric Anholt 73*51b76c1fSMaíra Canal V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << V3D_MMU_PAGE_SHIFT); 7440609d48SEric Anholt V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size); 7557692c94SEric Anholt 7657692c94SEric Anholt out: 772b86189eSEmil Velikov drm_gem_object_put(obj); 7857692c94SEric Anholt } 7957692c94SEric Anholt 8057692c94SEric Anholt static irqreturn_t 8157692c94SEric Anholt v3d_irq(int irq, void *arg) 8257692c94SEric Anholt { 8357692c94SEric Anholt struct v3d_dev *v3d = arg; 8457692c94SEric Anholt u32 intsts; 8557692c94SEric Anholt irqreturn_t status = IRQ_NONE; 8657692c94SEric Anholt 8757692c94SEric Anholt intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS); 8857692c94SEric Anholt 8957692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */ 9057692c94SEric Anholt V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts); 9157692c94SEric Anholt 9257692c94SEric Anholt if (intsts & V3D_INT_OUTOMEM) { 9357692c94SEric Anholt /* Note that the OOM status is edge signaled, so the 9457692c94SEric Anholt * interrupt won't happen again until the we actually 95ad8d68b2SEric Anholt * add more memory. Also, as of V3D 4.1, FLDONE won't 96ad8d68b2SEric Anholt * be reported until any OOM state has been cleared. 9757692c94SEric Anholt */ 9857692c94SEric Anholt schedule_work(&v3d->overflow_mem_work); 9957692c94SEric Anholt status = IRQ_HANDLED; 10057692c94SEric Anholt } 10157692c94SEric Anholt 10257692c94SEric Anholt if (intsts & V3D_INT_FLDONE) { 10355a9b748SEric Anholt struct v3d_fence *fence = 104a783a09eSEric Anholt to_v3d_fence(v3d->bin_job->base.irq_fence); 10509a93cc4SMaíra Canal struct v3d_file_priv *file = v3d->bin_job->base.file->driver_priv; 106509433d8SMaíra Canal u64 runtime = local_clock() - file->start_ns[V3D_BIN]; 10709a93cc4SMaíra Canal 10809a93cc4SMaíra Canal file->enabled_ns[V3D_BIN] += local_clock() - file->start_ns[V3D_BIN]; 10909a93cc4SMaíra Canal file->jobs_sent[V3D_BIN]++; 110509433d8SMaíra Canal v3d->queue[V3D_BIN].jobs_sent++; 111509433d8SMaíra Canal 11209a93cc4SMaíra Canal file->start_ns[V3D_BIN] = 0; 113509433d8SMaíra Canal v3d->queue[V3D_BIN].start_ns = 0; 114509433d8SMaíra Canal 115509433d8SMaíra Canal file->enabled_ns[V3D_BIN] += runtime; 116509433d8SMaíra Canal v3d->queue[V3D_BIN].enabled_ns += runtime; 11755a9b748SEric Anholt 11855a9b748SEric Anholt trace_v3d_bcl_irq(&v3d->drm, fence->seqno); 11955a9b748SEric Anholt dma_fence_signal(&fence->base); 12057692c94SEric Anholt status = IRQ_HANDLED; 12157692c94SEric Anholt } 12257692c94SEric Anholt 12357692c94SEric Anholt if (intsts & V3D_INT_FRDONE) { 12455a9b748SEric Anholt struct v3d_fence *fence = 125a783a09eSEric Anholt to_v3d_fence(v3d->render_job->base.irq_fence); 12609a93cc4SMaíra Canal struct v3d_file_priv *file = v3d->render_job->base.file->driver_priv; 127509433d8SMaíra Canal u64 runtime = local_clock() - file->start_ns[V3D_RENDER]; 12809a93cc4SMaíra Canal 12909a93cc4SMaíra Canal file->enabled_ns[V3D_RENDER] += local_clock() - file->start_ns[V3D_RENDER]; 13009a93cc4SMaíra Canal file->jobs_sent[V3D_RENDER]++; 131509433d8SMaíra Canal v3d->queue[V3D_RENDER].jobs_sent++; 132509433d8SMaíra Canal 13309a93cc4SMaíra Canal file->start_ns[V3D_RENDER] = 0; 134509433d8SMaíra Canal v3d->queue[V3D_RENDER].start_ns = 0; 135509433d8SMaíra Canal 136509433d8SMaíra Canal file->enabled_ns[V3D_RENDER] += runtime; 137509433d8SMaíra Canal v3d->queue[V3D_RENDER].enabled_ns += runtime; 13855a9b748SEric Anholt 13955a9b748SEric Anholt trace_v3d_rcl_irq(&v3d->drm, fence->seqno); 14055a9b748SEric Anholt dma_fence_signal(&fence->base); 14157692c94SEric Anholt status = IRQ_HANDLED; 14257692c94SEric Anholt } 14357692c94SEric Anholt 1440ad5bc1cSIago Toral Quiroga if (intsts & V3D_INT_CSDDONE(v3d->ver)) { 145d223f98fSEric Anholt struct v3d_fence *fence = 146d223f98fSEric Anholt to_v3d_fence(v3d->csd_job->base.irq_fence); 14709a93cc4SMaíra Canal struct v3d_file_priv *file = v3d->csd_job->base.file->driver_priv; 148509433d8SMaíra Canal u64 runtime = local_clock() - file->start_ns[V3D_CSD]; 14909a93cc4SMaíra Canal 15009a93cc4SMaíra Canal file->enabled_ns[V3D_CSD] += local_clock() - file->start_ns[V3D_CSD]; 15109a93cc4SMaíra Canal file->jobs_sent[V3D_CSD]++; 152509433d8SMaíra Canal v3d->queue[V3D_CSD].jobs_sent++; 153509433d8SMaíra Canal 15409a93cc4SMaíra Canal file->start_ns[V3D_CSD] = 0; 155509433d8SMaíra Canal v3d->queue[V3D_CSD].start_ns = 0; 156509433d8SMaíra Canal 157509433d8SMaíra Canal file->enabled_ns[V3D_CSD] += runtime; 158509433d8SMaíra Canal v3d->queue[V3D_CSD].enabled_ns += runtime; 159d223f98fSEric Anholt 160d223f98fSEric Anholt trace_v3d_csd_irq(&v3d->drm, fence->seqno); 161d223f98fSEric Anholt dma_fence_signal(&fence->base); 162d223f98fSEric Anholt status = IRQ_HANDLED; 163d223f98fSEric Anholt } 164d223f98fSEric Anholt 16557692c94SEric Anholt /* We shouldn't be triggering these if we have GMP in 16657692c94SEric Anholt * always-allowed mode. 16757692c94SEric Anholt */ 1680ad5bc1cSIago Toral Quiroga if (v3d->ver < 71 && (intsts & V3D_INT_GMPV)) 169bc662528SDaniel Vetter dev_err(v3d->drm.dev, "GMP violation\n"); 17057692c94SEric Anholt 171eea9b97bSEric Anholt /* V3D 4.2 wires the hub and core IRQs together, so if we & 172eea9b97bSEric Anholt * didn't see the common one then check hub for MMU IRQs. 173eea9b97bSEric Anholt */ 174eea9b97bSEric Anholt if (v3d->single_irq_line && status == IRQ_NONE) 175eea9b97bSEric Anholt return v3d_hub_irq(irq, arg); 176eea9b97bSEric Anholt 17757692c94SEric Anholt return status; 17857692c94SEric Anholt } 17957692c94SEric Anholt 18057692c94SEric Anholt static irqreturn_t 18157692c94SEric Anholt v3d_hub_irq(int irq, void *arg) 18257692c94SEric Anholt { 18357692c94SEric Anholt struct v3d_dev *v3d = arg; 18457692c94SEric Anholt u32 intsts; 18557692c94SEric Anholt irqreturn_t status = IRQ_NONE; 18657692c94SEric Anholt 18757692c94SEric Anholt intsts = V3D_READ(V3D_HUB_INT_STS); 18857692c94SEric Anholt 18957692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */ 19057692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, intsts); 19157692c94SEric Anholt 1921584f16cSEric Anholt if (intsts & V3D_HUB_INT_TFUC) { 19355a9b748SEric Anholt struct v3d_fence *fence = 194a783a09eSEric Anholt to_v3d_fence(v3d->tfu_job->base.irq_fence); 19509a93cc4SMaíra Canal struct v3d_file_priv *file = v3d->tfu_job->base.file->driver_priv; 196509433d8SMaíra Canal u64 runtime = local_clock() - file->start_ns[V3D_TFU]; 19709a93cc4SMaíra Canal 19809a93cc4SMaíra Canal file->enabled_ns[V3D_TFU] += local_clock() - file->start_ns[V3D_TFU]; 19909a93cc4SMaíra Canal file->jobs_sent[V3D_TFU]++; 200509433d8SMaíra Canal v3d->queue[V3D_TFU].jobs_sent++; 201509433d8SMaíra Canal 20209a93cc4SMaíra Canal file->start_ns[V3D_TFU] = 0; 203509433d8SMaíra Canal v3d->queue[V3D_TFU].start_ns = 0; 204509433d8SMaíra Canal 205509433d8SMaíra Canal file->enabled_ns[V3D_TFU] += runtime; 206509433d8SMaíra Canal v3d->queue[V3D_TFU].enabled_ns += runtime; 20755a9b748SEric Anholt 20855a9b748SEric Anholt trace_v3d_tfu_irq(&v3d->drm, fence->seqno); 20955a9b748SEric Anholt dma_fence_signal(&fence->base); 2101584f16cSEric Anholt status = IRQ_HANDLED; 2111584f16cSEric Anholt } 2121584f16cSEric Anholt 21357692c94SEric Anholt if (intsts & (V3D_HUB_INT_MMU_WRV | 21457692c94SEric Anholt V3D_HUB_INT_MMU_PTI | 21557692c94SEric Anholt V3D_HUB_INT_MMU_CAP)) { 21657692c94SEric Anholt u32 axi_id = V3D_READ(V3D_MMU_VIO_ID); 21738c2c791SEric Anholt u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) << 21838c2c791SEric Anholt (v3d->va_width - 32)); 21938c2c791SEric Anholt static const char *const v3d41_axi_ids[] = { 22038c2c791SEric Anholt "L2T", 22138c2c791SEric Anholt "PTB", 22238c2c791SEric Anholt "PSE", 22338c2c791SEric Anholt "TLB", 22438c2c791SEric Anholt "CLE", 22538c2c791SEric Anholt "TFU", 22638c2c791SEric Anholt "MMU", 22738c2c791SEric Anholt "GMP", 22838c2c791SEric Anholt }; 22938c2c791SEric Anholt const char *client = "?"; 23057692c94SEric Anholt 231545d9d78SPhil Elwell V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL)); 23238c2c791SEric Anholt 23338c2c791SEric Anholt if (v3d->ver >= 41) { 23438c2c791SEric Anholt axi_id = axi_id >> 5; 23538c2c791SEric Anholt if (axi_id < ARRAY_SIZE(v3d41_axi_ids)) 23638c2c791SEric Anholt client = v3d41_axi_ids[axi_id]; 23738c2c791SEric Anholt } 23838c2c791SEric Anholt 239bc662528SDaniel Vetter dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n", 24038c2c791SEric Anholt client, axi_id, (long long)vio_addr, 24157692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_WRV) ? 24257692c94SEric Anholt ", write violation" : ""), 24357692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_PTI) ? 24457692c94SEric Anholt ", pte invalid" : ""), 24557692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_CAP) ? 24657692c94SEric Anholt ", cap exceeded" : "")); 24757692c94SEric Anholt status = IRQ_HANDLED; 24857692c94SEric Anholt } 24957692c94SEric Anholt 2500ad5bc1cSIago Toral Quiroga if (v3d->ver >= 71 && (intsts & V3D_V7_HUB_INT_GMPV)) { 2510ad5bc1cSIago Toral Quiroga dev_err(v3d->drm.dev, "GMP Violation\n"); 2520ad5bc1cSIago Toral Quiroga status = IRQ_HANDLED; 2530ad5bc1cSIago Toral Quiroga } 2540ad5bc1cSIago Toral Quiroga 25557692c94SEric Anholt return status; 25657692c94SEric Anholt } 25757692c94SEric Anholt 258fc227715SEric Anholt int 25957692c94SEric Anholt v3d_irq_init(struct v3d_dev *v3d) 26057692c94SEric Anholt { 261eea9b97bSEric Anholt int irq1, ret, core; 26257692c94SEric Anholt 26357692c94SEric Anholt INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work); 26457692c94SEric Anholt 26557692c94SEric Anholt /* Clear any pending interrupts someone might have left around 26657692c94SEric Anholt * for us. 26757692c94SEric Anholt */ 26857692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 2690ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver)); 2700ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver)); 27157692c94SEric Anholt 272f4f3beb7SNicolas Saenz Julienne irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1); 273eea9b97bSEric Anholt if (irq1 == -EPROBE_DEFER) 274eea9b97bSEric Anholt return irq1; 275eea9b97bSEric Anholt if (irq1 > 0) { 276bc662528SDaniel Vetter ret = devm_request_irq(v3d->drm.dev, irq1, 277eea9b97bSEric Anholt v3d_irq, IRQF_SHARED, 278eea9b97bSEric Anholt "v3d_core0", v3d); 279eea9b97bSEric Anholt if (ret) 280eea9b97bSEric Anholt goto fail; 2810df3ac76SDaniel Vetter ret = devm_request_irq(v3d->drm.dev, 2820df3ac76SDaniel Vetter platform_get_irq(v3d_to_pdev(v3d), 0), 28357692c94SEric Anholt v3d_hub_irq, IRQF_SHARED, 28457692c94SEric Anholt "v3d_hub", v3d); 285fc227715SEric Anholt if (ret) 286fc227715SEric Anholt goto fail; 287eea9b97bSEric Anholt } else { 288eea9b97bSEric Anholt v3d->single_irq_line = true; 289fc227715SEric Anholt 2900df3ac76SDaniel Vetter ret = devm_request_irq(v3d->drm.dev, 2910df3ac76SDaniel Vetter platform_get_irq(v3d_to_pdev(v3d), 0), 29257692c94SEric Anholt v3d_irq, IRQF_SHARED, 293eea9b97bSEric Anholt "v3d", v3d); 29457692c94SEric Anholt if (ret) 295fc227715SEric Anholt goto fail; 296eea9b97bSEric Anholt } 29757692c94SEric Anholt 29857692c94SEric Anholt v3d_irq_enable(v3d); 299fc227715SEric Anholt return 0; 300fc227715SEric Anholt 301fc227715SEric Anholt fail: 302fc227715SEric Anholt if (ret != -EPROBE_DEFER) 303bc662528SDaniel Vetter dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret); 304fc227715SEric Anholt return ret; 30557692c94SEric Anholt } 30657692c94SEric Anholt 30757692c94SEric Anholt void 30857692c94SEric Anholt v3d_irq_enable(struct v3d_dev *v3d) 30957692c94SEric Anholt { 31057692c94SEric Anholt int core; 31157692c94SEric Anholt 31257692c94SEric Anholt /* Enable our set of interrupts, masking out any others. */ 31357692c94SEric Anholt for (core = 0; core < v3d->cores; core++) { 3140ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS(v3d->ver)); 3150ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS(v3d->ver)); 31657692c94SEric Anholt } 31757692c94SEric Anholt 3180ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS(v3d->ver)); 3190ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS(v3d->ver)); 32057692c94SEric Anholt } 32157692c94SEric Anholt 32257692c94SEric Anholt void 32357692c94SEric Anholt v3d_irq_disable(struct v3d_dev *v3d) 32457692c94SEric Anholt { 32557692c94SEric Anholt int core; 32657692c94SEric Anholt 32757692c94SEric Anholt /* Disable all interrupts. */ 32857692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 32957692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0); 33057692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); 33157692c94SEric Anholt 33257692c94SEric Anholt /* Clear any pending interrupts we might have left. */ 33357692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 3340ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver)); 3350ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver)); 33657692c94SEric Anholt 33757692c94SEric Anholt cancel_work_sync(&v3d->overflow_mem_work); 33857692c94SEric Anholt } 33957692c94SEric Anholt 34057692c94SEric Anholt /** Reinitializes interrupt registers when a GPU reset is performed. */ 34157692c94SEric Anholt void v3d_irq_reset(struct v3d_dev *v3d) 34257692c94SEric Anholt { 34357692c94SEric Anholt v3d_irq_enable(v3d); 34457692c94SEric Anholt } 345