157692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+ 257692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */ 357692c94SEric Anholt 457692c94SEric Anholt /** 557692c94SEric Anholt * DOC: Interrupt management for the V3D engine 657692c94SEric Anholt * 7d223f98fSEric Anholt * When we take a bin, render, TFU done, or CSD done interrupt, we 8d223f98fSEric Anholt * need to signal the fence for that job so that the scheduler can 9d223f98fSEric Anholt * queue up the next one and unblock any waiters. 1057692c94SEric Anholt * 1157692c94SEric Anholt * When we take the binner out of memory interrupt, we need to 1257692c94SEric Anholt * allocate some new memory and pass it to the binner so that the 1357692c94SEric Anholt * current job can make progress. 1457692c94SEric Anholt */ 1557692c94SEric Anholt 16220989e7SSam Ravnborg #include <linux/platform_device.h> 17220989e7SSam Ravnborg 1857692c94SEric Anholt #include "v3d_drv.h" 1957692c94SEric Anholt #include "v3d_regs.h" 2055a9b748SEric Anholt #include "v3d_trace.h" 2157692c94SEric Anholt 22*0ad5bc1cSIago Toral Quiroga #define V3D_CORE_IRQS(ver) ((u32)(V3D_INT_OUTOMEM | \ 2357692c94SEric Anholt V3D_INT_FLDONE | \ 2457692c94SEric Anholt V3D_INT_FRDONE | \ 25*0ad5bc1cSIago Toral Quiroga V3D_INT_CSDDONE(ver) | \ 26*0ad5bc1cSIago Toral Quiroga (ver < 71 ? V3D_INT_GMPV : 0))) 2757692c94SEric Anholt 28*0ad5bc1cSIago Toral Quiroga #define V3D_HUB_IRQS(ver) ((u32)(V3D_HUB_INT_MMU_WRV | \ 2957692c94SEric Anholt V3D_HUB_INT_MMU_PTI | \ 301584f16cSEric Anholt V3D_HUB_INT_MMU_CAP | \ 31*0ad5bc1cSIago Toral Quiroga V3D_HUB_INT_TFUC | \ 32*0ad5bc1cSIago Toral Quiroga (ver >= 71 ? V3D_V7_HUB_INT_GMPV : 0))) 3357692c94SEric Anholt 34eea9b97bSEric Anholt static irqreturn_t 35eea9b97bSEric Anholt v3d_hub_irq(int irq, void *arg); 36eea9b97bSEric Anholt 3757692c94SEric Anholt static void 3857692c94SEric Anholt v3d_overflow_mem_work(struct work_struct *work) 3957692c94SEric Anholt { 4057692c94SEric Anholt struct v3d_dev *v3d = 4157692c94SEric Anholt container_of(work, struct v3d_dev, overflow_mem_work); 4257692c94SEric Anholt struct drm_device *dev = &v3d->drm; 4357692c94SEric Anholt struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024); 4440609d48SEric Anholt struct drm_gem_object *obj; 4557692c94SEric Anholt unsigned long irqflags; 4657692c94SEric Anholt 4757692c94SEric Anholt if (IS_ERR(bo)) { 4857692c94SEric Anholt DRM_ERROR("Couldn't allocate binner overflow mem\n"); 4957692c94SEric Anholt return; 5057692c94SEric Anholt } 5140609d48SEric Anholt obj = &bo->base.base; 5257692c94SEric Anholt 5357692c94SEric Anholt /* We lost a race, and our work task came in after the bin job 5457692c94SEric Anholt * completed and exited. This can happen because the HW 5557692c94SEric Anholt * signals OOM before it's fully OOM, so the binner might just 5657692c94SEric Anholt * barely complete. 5757692c94SEric Anholt * 5857692c94SEric Anholt * If we lose the race and our work task comes in after a new 5957692c94SEric Anholt * bin job got scheduled, that's fine. We'll just give them 6057692c94SEric Anholt * some binner pool anyway. 6157692c94SEric Anholt */ 6257692c94SEric Anholt spin_lock_irqsave(&v3d->job_lock, irqflags); 6357692c94SEric Anholt if (!v3d->bin_job) { 6457692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags); 6557692c94SEric Anholt goto out; 6657692c94SEric Anholt } 6757692c94SEric Anholt 6840609d48SEric Anholt drm_gem_object_get(obj); 69a783a09eSEric Anholt list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list); 7057692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags); 7157692c94SEric Anholt 7257692c94SEric Anholt V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT); 7340609d48SEric Anholt V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size); 7457692c94SEric Anholt 7557692c94SEric Anholt out: 762b86189eSEmil Velikov drm_gem_object_put(obj); 7757692c94SEric Anholt } 7857692c94SEric Anholt 7957692c94SEric Anholt static irqreturn_t 8057692c94SEric Anholt v3d_irq(int irq, void *arg) 8157692c94SEric Anholt { 8257692c94SEric Anholt struct v3d_dev *v3d = arg; 8357692c94SEric Anholt u32 intsts; 8457692c94SEric Anholt irqreturn_t status = IRQ_NONE; 8557692c94SEric Anholt 8657692c94SEric Anholt intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS); 8757692c94SEric Anholt 8857692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */ 8957692c94SEric Anholt V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts); 9057692c94SEric Anholt 9157692c94SEric Anholt if (intsts & V3D_INT_OUTOMEM) { 9257692c94SEric Anholt /* Note that the OOM status is edge signaled, so the 9357692c94SEric Anholt * interrupt won't happen again until the we actually 94ad8d68b2SEric Anholt * add more memory. Also, as of V3D 4.1, FLDONE won't 95ad8d68b2SEric Anholt * be reported until any OOM state has been cleared. 9657692c94SEric Anholt */ 9757692c94SEric Anholt schedule_work(&v3d->overflow_mem_work); 9857692c94SEric Anholt status = IRQ_HANDLED; 9957692c94SEric Anholt } 10057692c94SEric Anholt 10157692c94SEric Anholt if (intsts & V3D_INT_FLDONE) { 10255a9b748SEric Anholt struct v3d_fence *fence = 103a783a09eSEric Anholt to_v3d_fence(v3d->bin_job->base.irq_fence); 10455a9b748SEric Anholt 10555a9b748SEric Anholt trace_v3d_bcl_irq(&v3d->drm, fence->seqno); 10655a9b748SEric Anholt dma_fence_signal(&fence->base); 10757692c94SEric Anholt status = IRQ_HANDLED; 10857692c94SEric Anholt } 10957692c94SEric Anholt 11057692c94SEric Anholt if (intsts & V3D_INT_FRDONE) { 11155a9b748SEric Anholt struct v3d_fence *fence = 112a783a09eSEric Anholt to_v3d_fence(v3d->render_job->base.irq_fence); 11355a9b748SEric Anholt 11455a9b748SEric Anholt trace_v3d_rcl_irq(&v3d->drm, fence->seqno); 11555a9b748SEric Anholt dma_fence_signal(&fence->base); 11657692c94SEric Anholt status = IRQ_HANDLED; 11757692c94SEric Anholt } 11857692c94SEric Anholt 119*0ad5bc1cSIago Toral Quiroga if (intsts & V3D_INT_CSDDONE(v3d->ver)) { 120d223f98fSEric Anholt struct v3d_fence *fence = 121d223f98fSEric Anholt to_v3d_fence(v3d->csd_job->base.irq_fence); 122d223f98fSEric Anholt 123d223f98fSEric Anholt trace_v3d_csd_irq(&v3d->drm, fence->seqno); 124d223f98fSEric Anholt dma_fence_signal(&fence->base); 125d223f98fSEric Anholt status = IRQ_HANDLED; 126d223f98fSEric Anholt } 127d223f98fSEric Anholt 12857692c94SEric Anholt /* We shouldn't be triggering these if we have GMP in 12957692c94SEric Anholt * always-allowed mode. 13057692c94SEric Anholt */ 131*0ad5bc1cSIago Toral Quiroga if (v3d->ver < 71 && (intsts & V3D_INT_GMPV)) 132bc662528SDaniel Vetter dev_err(v3d->drm.dev, "GMP violation\n"); 13357692c94SEric Anholt 134eea9b97bSEric Anholt /* V3D 4.2 wires the hub and core IRQs together, so if we & 135eea9b97bSEric Anholt * didn't see the common one then check hub for MMU IRQs. 136eea9b97bSEric Anholt */ 137eea9b97bSEric Anholt if (v3d->single_irq_line && status == IRQ_NONE) 138eea9b97bSEric Anholt return v3d_hub_irq(irq, arg); 139eea9b97bSEric Anholt 14057692c94SEric Anholt return status; 14157692c94SEric Anholt } 14257692c94SEric Anholt 14357692c94SEric Anholt static irqreturn_t 14457692c94SEric Anholt v3d_hub_irq(int irq, void *arg) 14557692c94SEric Anholt { 14657692c94SEric Anholt struct v3d_dev *v3d = arg; 14757692c94SEric Anholt u32 intsts; 14857692c94SEric Anholt irqreturn_t status = IRQ_NONE; 14957692c94SEric Anholt 15057692c94SEric Anholt intsts = V3D_READ(V3D_HUB_INT_STS); 15157692c94SEric Anholt 15257692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */ 15357692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, intsts); 15457692c94SEric Anholt 1551584f16cSEric Anholt if (intsts & V3D_HUB_INT_TFUC) { 15655a9b748SEric Anholt struct v3d_fence *fence = 157a783a09eSEric Anholt to_v3d_fence(v3d->tfu_job->base.irq_fence); 15855a9b748SEric Anholt 15955a9b748SEric Anholt trace_v3d_tfu_irq(&v3d->drm, fence->seqno); 16055a9b748SEric Anholt dma_fence_signal(&fence->base); 1611584f16cSEric Anholt status = IRQ_HANDLED; 1621584f16cSEric Anholt } 1631584f16cSEric Anholt 16457692c94SEric Anholt if (intsts & (V3D_HUB_INT_MMU_WRV | 16557692c94SEric Anholt V3D_HUB_INT_MMU_PTI | 16657692c94SEric Anholt V3D_HUB_INT_MMU_CAP)) { 16757692c94SEric Anholt u32 axi_id = V3D_READ(V3D_MMU_VIO_ID); 16838c2c791SEric Anholt u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) << 16938c2c791SEric Anholt (v3d->va_width - 32)); 17038c2c791SEric Anholt static const char *const v3d41_axi_ids[] = { 17138c2c791SEric Anholt "L2T", 17238c2c791SEric Anholt "PTB", 17338c2c791SEric Anholt "PSE", 17438c2c791SEric Anholt "TLB", 17538c2c791SEric Anholt "CLE", 17638c2c791SEric Anholt "TFU", 17738c2c791SEric Anholt "MMU", 17838c2c791SEric Anholt "GMP", 17938c2c791SEric Anholt }; 18038c2c791SEric Anholt const char *client = "?"; 18157692c94SEric Anholt 182545d9d78SPhil Elwell V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL)); 18338c2c791SEric Anholt 18438c2c791SEric Anholt if (v3d->ver >= 41) { 18538c2c791SEric Anholt axi_id = axi_id >> 5; 18638c2c791SEric Anholt if (axi_id < ARRAY_SIZE(v3d41_axi_ids)) 18738c2c791SEric Anholt client = v3d41_axi_ids[axi_id]; 18838c2c791SEric Anholt } 18938c2c791SEric Anholt 190bc662528SDaniel Vetter dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n", 19138c2c791SEric Anholt client, axi_id, (long long)vio_addr, 19257692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_WRV) ? 19357692c94SEric Anholt ", write violation" : ""), 19457692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_PTI) ? 19557692c94SEric Anholt ", pte invalid" : ""), 19657692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_CAP) ? 19757692c94SEric Anholt ", cap exceeded" : "")); 19857692c94SEric Anholt status = IRQ_HANDLED; 19957692c94SEric Anholt } 20057692c94SEric Anholt 201*0ad5bc1cSIago Toral Quiroga if (v3d->ver >= 71 && (intsts & V3D_V7_HUB_INT_GMPV)) { 202*0ad5bc1cSIago Toral Quiroga dev_err(v3d->drm.dev, "GMP Violation\n"); 203*0ad5bc1cSIago Toral Quiroga status = IRQ_HANDLED; 204*0ad5bc1cSIago Toral Quiroga } 205*0ad5bc1cSIago Toral Quiroga 20657692c94SEric Anholt return status; 20757692c94SEric Anholt } 20857692c94SEric Anholt 209fc227715SEric Anholt int 21057692c94SEric Anholt v3d_irq_init(struct v3d_dev *v3d) 21157692c94SEric Anholt { 212eea9b97bSEric Anholt int irq1, ret, core; 21357692c94SEric Anholt 21457692c94SEric Anholt INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work); 21557692c94SEric Anholt 21657692c94SEric Anholt /* Clear any pending interrupts someone might have left around 21757692c94SEric Anholt * for us. 21857692c94SEric Anholt */ 21957692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 220*0ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver)); 221*0ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver)); 22257692c94SEric Anholt 223f4f3beb7SNicolas Saenz Julienne irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1); 224eea9b97bSEric Anholt if (irq1 == -EPROBE_DEFER) 225eea9b97bSEric Anholt return irq1; 226eea9b97bSEric Anholt if (irq1 > 0) { 227bc662528SDaniel Vetter ret = devm_request_irq(v3d->drm.dev, irq1, 228eea9b97bSEric Anholt v3d_irq, IRQF_SHARED, 229eea9b97bSEric Anholt "v3d_core0", v3d); 230eea9b97bSEric Anholt if (ret) 231eea9b97bSEric Anholt goto fail; 2320df3ac76SDaniel Vetter ret = devm_request_irq(v3d->drm.dev, 2330df3ac76SDaniel Vetter platform_get_irq(v3d_to_pdev(v3d), 0), 23457692c94SEric Anholt v3d_hub_irq, IRQF_SHARED, 23557692c94SEric Anholt "v3d_hub", v3d); 236fc227715SEric Anholt if (ret) 237fc227715SEric Anholt goto fail; 238eea9b97bSEric Anholt } else { 239eea9b97bSEric Anholt v3d->single_irq_line = true; 240fc227715SEric Anholt 2410df3ac76SDaniel Vetter ret = devm_request_irq(v3d->drm.dev, 2420df3ac76SDaniel Vetter platform_get_irq(v3d_to_pdev(v3d), 0), 24357692c94SEric Anholt v3d_irq, IRQF_SHARED, 244eea9b97bSEric Anholt "v3d", v3d); 24557692c94SEric Anholt if (ret) 246fc227715SEric Anholt goto fail; 247eea9b97bSEric Anholt } 24857692c94SEric Anholt 24957692c94SEric Anholt v3d_irq_enable(v3d); 250fc227715SEric Anholt return 0; 251fc227715SEric Anholt 252fc227715SEric Anholt fail: 253fc227715SEric Anholt if (ret != -EPROBE_DEFER) 254bc662528SDaniel Vetter dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret); 255fc227715SEric Anholt return ret; 25657692c94SEric Anholt } 25757692c94SEric Anholt 25857692c94SEric Anholt void 25957692c94SEric Anholt v3d_irq_enable(struct v3d_dev *v3d) 26057692c94SEric Anholt { 26157692c94SEric Anholt int core; 26257692c94SEric Anholt 26357692c94SEric Anholt /* Enable our set of interrupts, masking out any others. */ 26457692c94SEric Anholt for (core = 0; core < v3d->cores; core++) { 265*0ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS(v3d->ver)); 266*0ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS(v3d->ver)); 26757692c94SEric Anholt } 26857692c94SEric Anholt 269*0ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS(v3d->ver)); 270*0ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS(v3d->ver)); 27157692c94SEric Anholt } 27257692c94SEric Anholt 27357692c94SEric Anholt void 27457692c94SEric Anholt v3d_irq_disable(struct v3d_dev *v3d) 27557692c94SEric Anholt { 27657692c94SEric Anholt int core; 27757692c94SEric Anholt 27857692c94SEric Anholt /* Disable all interrupts. */ 27957692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 28057692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0); 28157692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); 28257692c94SEric Anholt 28357692c94SEric Anholt /* Clear any pending interrupts we might have left. */ 28457692c94SEric Anholt for (core = 0; core < v3d->cores; core++) 285*0ad5bc1cSIago Toral Quiroga V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver)); 286*0ad5bc1cSIago Toral Quiroga V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver)); 28757692c94SEric Anholt 28857692c94SEric Anholt cancel_work_sync(&v3d->overflow_mem_work); 28957692c94SEric Anholt } 29057692c94SEric Anholt 29157692c94SEric Anholt /** Reinitializes interrupt registers when a GPU reset is performed. */ 29257692c94SEric Anholt void v3d_irq_reset(struct v3d_dev *v3d) 29357692c94SEric Anholt { 29457692c94SEric Anholt v3d_irq_enable(v3d); 29557692c94SEric Anholt } 296