1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 #include <linux/device.h> 5 #include <linux/dma-mapping.h> 6 #include <linux/io.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/reset.h> 10 #include <linux/sched/signal.h> 11 #include <linux/uaccess.h> 12 13 #include <drm/drm_managed.h> 14 15 #include "v3d_drv.h" 16 #include "v3d_regs.h" 17 #include "v3d_trace.h" 18 19 static void 20 v3d_init_core(struct v3d_dev *v3d, int core) 21 { 22 /* Set OVRTMUOUT, which means that the texture sampler uniform 23 * configuration's tmu output type field is used, instead of 24 * using the hardware default behavior based on the texture 25 * type. If you want the default behavior, you can still put 26 * "2" in the indirect texture state's output_type field. 27 */ 28 if (v3d->ver < V3D_GEN_41) 29 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT); 30 31 /* Whenever we flush the L2T cache, we always want to flush 32 * the whole thing. 33 */ 34 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0); 35 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0); 36 } 37 38 /* Sets invariant state for the HW. */ 39 static void 40 v3d_init_hw_state(struct v3d_dev *v3d) 41 { 42 v3d_init_core(v3d, 0); 43 } 44 45 static void 46 v3d_idle_axi(struct v3d_dev *v3d, int core) 47 { 48 V3D_CORE_WRITE(core, V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ); 49 50 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS(v3d->ver)) & 51 (V3D_GMP_STATUS_RD_COUNT_MASK | 52 V3D_GMP_STATUS_WR_COUNT_MASK | 53 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) { 54 DRM_ERROR("Failed to wait for safe GMP shutdown\n"); 55 } 56 } 57 58 static void 59 v3d_idle_gca(struct v3d_dev *v3d) 60 { 61 if (v3d->ver >= V3D_GEN_41) 62 return; 63 64 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN); 65 66 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) & 67 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) == 68 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) { 69 DRM_ERROR("Failed to wait for safe GCA shutdown\n"); 70 } 71 } 72 73 static void 74 v3d_reset_by_bridge(struct v3d_dev *v3d) 75 { 76 int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION); 77 78 if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) { 79 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 80 V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT); 81 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0); 82 83 /* GFXH-1383: The SW_INIT may cause a stray write to address 0 84 * of the unit, so reset it to its power-on value here. 85 */ 86 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK); 87 } else { 88 WARN_ON_ONCE(V3D_GET_FIELD(version, 89 V3D_TOP_GR_BRIDGE_MAJOR) != 7); 90 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 91 V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT); 92 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0); 93 } 94 } 95 96 static void 97 v3d_reset_v3d(struct v3d_dev *v3d) 98 { 99 if (v3d->reset) 100 reset_control_reset(v3d->reset); 101 else 102 v3d_reset_by_bridge(v3d); 103 104 v3d_init_hw_state(v3d); 105 } 106 107 void 108 v3d_reset_sms(struct v3d_dev *v3d) 109 { 110 if (v3d->ver < V3D_GEN_71) 111 return; 112 113 V3D_SMS_WRITE(V3D_SMS_REE_CS, V3D_SET_FIELD(0x4, V3D_SMS_STATE)); 114 115 if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 116 V3D_SMS_STATE) == V3D_SMS_ISOLATING_FOR_RESET) && 117 !(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 118 V3D_SMS_STATE) == V3D_SMS_RESETTING), 100)) { 119 DRM_ERROR("Failed to wait for SMS reset\n"); 120 } 121 } 122 123 void 124 v3d_reset(struct v3d_dev *v3d) 125 { 126 struct drm_device *dev = &v3d->drm; 127 128 DRM_DEV_ERROR(dev->dev, "Resetting GPU for hang.\n"); 129 DRM_DEV_ERROR(dev->dev, "V3D_ERR_STAT: 0x%08x\n", 130 V3D_CORE_READ(0, V3D_ERR_STAT)); 131 trace_v3d_reset_begin(dev); 132 133 /* XXX: only needed for safe powerdown, not reset. */ 134 if (false) 135 v3d_idle_axi(v3d, 0); 136 137 v3d_idle_gca(v3d); 138 v3d_reset_sms(v3d); 139 v3d_reset_v3d(v3d); 140 141 v3d_mmu_set_page_table(v3d); 142 v3d_irq_reset(v3d); 143 144 v3d_perfmon_stop(v3d, v3d->active_perfmon, false); 145 146 trace_v3d_reset_end(dev); 147 } 148 149 static void 150 v3d_flush_l3(struct v3d_dev *v3d) 151 { 152 if (v3d->ver < V3D_GEN_41) { 153 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL); 154 155 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 156 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH); 157 158 if (v3d->ver < V3D_GEN_33) { 159 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 160 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH); 161 } 162 } 163 } 164 165 /* Invalidates the (read-only) L2C cache. This was the L2 cache for 166 * uniforms and instructions on V3D 3.2. 167 */ 168 static void 169 v3d_invalidate_l2c(struct v3d_dev *v3d, int core) 170 { 171 if (v3d->ver >= V3D_GEN_33) 172 return; 173 174 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL, 175 V3D_L2CACTL_L2CCLR | 176 V3D_L2CACTL_L2CENA); 177 } 178 179 /* Invalidates texture L2 cachelines */ 180 static void 181 v3d_flush_l2t(struct v3d_dev *v3d, int core) 182 { 183 /* While there is a busy bit (V3D_L2TCACTL_L2TFLS), we don't 184 * need to wait for completion before dispatching the job -- 185 * L2T accesses will be stalled until the flush has completed. 186 * However, we do need to make sure we don't try to trigger a 187 * new flush while the L2_CLEAN queue is trying to 188 * synchronously clean after a job. 189 */ 190 mutex_lock(&v3d->cache_clean_lock); 191 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 192 V3D_L2TCACTL_L2TFLS | 193 V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM)); 194 mutex_unlock(&v3d->cache_clean_lock); 195 } 196 197 /* Cleans texture L1 and L2 cachelines (writing back dirty data). 198 * 199 * For cleaning, which happens from the CACHE_CLEAN queue after CSD has 200 * executed, we need to make sure that the clean is done before 201 * signaling job completion. So, we synchronously wait before 202 * returning, and we make sure that L2 invalidates don't happen in the 203 * meantime to confuse our are-we-done checks. 204 */ 205 void 206 v3d_clean_caches(struct v3d_dev *v3d) 207 { 208 struct drm_device *dev = &v3d->drm; 209 int core = 0; 210 211 trace_v3d_cache_clean_begin(dev); 212 213 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); 214 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 215 V3D_L2TCACTL_TMUWCF), 100)) { 216 DRM_ERROR("Timeout waiting for TMU write combiner flush\n"); 217 } 218 219 mutex_lock(&v3d->cache_clean_lock); 220 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 221 V3D_L2TCACTL_L2TFLS | 222 V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAN, V3D_L2TCACTL_FLM)); 223 224 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 225 V3D_L2TCACTL_L2TFLS), 100)) { 226 DRM_ERROR("Timeout waiting for L2T clean\n"); 227 } 228 229 mutex_unlock(&v3d->cache_clean_lock); 230 231 trace_v3d_cache_clean_end(dev); 232 } 233 234 /* Invalidates the slice caches. These are read-only caches. */ 235 static void 236 v3d_invalidate_slices(struct v3d_dev *v3d, int core) 237 { 238 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL, 239 V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) | 240 V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) | 241 V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) | 242 V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC)); 243 } 244 245 void 246 v3d_invalidate_caches(struct v3d_dev *v3d) 247 { 248 /* Invalidate the caches from the outside in. That way if 249 * another CL's concurrent use of nearby memory were to pull 250 * an invalidated cacheline back in, we wouldn't leave stale 251 * data in the inner cache. 252 */ 253 v3d_flush_l3(v3d); 254 v3d_invalidate_l2c(v3d, 0); 255 v3d_flush_l2t(v3d, 0); 256 v3d_invalidate_slices(v3d, 0); 257 } 258 259 int 260 v3d_gem_init(struct drm_device *dev) 261 { 262 struct v3d_dev *v3d = to_v3d_dev(dev); 263 u32 pt_size = 4096 * 1024; 264 int ret, i; 265 266 for (i = 0; i < V3D_MAX_QUEUES; i++) { 267 struct v3d_queue_state *queue = &v3d->queue[i]; 268 269 queue->fence_context = dma_fence_context_alloc(1); 270 memset(&queue->stats, 0, sizeof(queue->stats)); 271 seqcount_init(&queue->stats.lock); 272 } 273 274 spin_lock_init(&v3d->mm_lock); 275 spin_lock_init(&v3d->job_lock); 276 ret = drmm_mutex_init(dev, &v3d->bo_lock); 277 if (ret) 278 return ret; 279 ret = drmm_mutex_init(dev, &v3d->reset_lock); 280 if (ret) 281 return ret; 282 ret = drmm_mutex_init(dev, &v3d->sched_lock); 283 if (ret) 284 return ret; 285 ret = drmm_mutex_init(dev, &v3d->cache_clean_lock); 286 if (ret) 287 return ret; 288 289 /* Note: We don't allocate address 0. Various bits of HW 290 * treat 0 as special, such as the occlusion query counters 291 * where 0 means "disabled". 292 */ 293 drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1); 294 295 v3d->pt = dma_alloc_wc(v3d->drm.dev, pt_size, 296 &v3d->pt_paddr, 297 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 298 if (!v3d->pt) { 299 drm_mm_takedown(&v3d->mm); 300 dev_err(v3d->drm.dev, 301 "Failed to allocate page tables. Please ensure you have DMA enabled.\n"); 302 return -ENOMEM; 303 } 304 305 v3d_init_hw_state(v3d); 306 v3d_mmu_set_page_table(v3d); 307 308 v3d_gemfs_init(v3d); 309 310 ret = v3d_sched_init(v3d); 311 if (ret) { 312 drm_mm_takedown(&v3d->mm); 313 dma_free_coherent(v3d->drm.dev, pt_size, (void *)v3d->pt, 314 v3d->pt_paddr); 315 return ret; 316 } 317 318 return 0; 319 } 320 321 void 322 v3d_gem_destroy(struct drm_device *dev) 323 { 324 struct v3d_dev *v3d = to_v3d_dev(dev); 325 326 v3d_sched_fini(v3d); 327 v3d_gemfs_fini(v3d); 328 329 /* Waiting for jobs to finish would need to be done before 330 * unregistering V3D. 331 */ 332 WARN_ON(v3d->bin_job); 333 WARN_ON(v3d->render_job); 334 WARN_ON(v3d->tfu_job); 335 WARN_ON(v3d->csd_job); 336 337 drm_mm_takedown(&v3d->mm); 338 339 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt, 340 v3d->pt_paddr); 341 } 342