1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 #include <linux/device.h> 5 #include <linux/dma-mapping.h> 6 #include <linux/io.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/reset.h> 10 #include <linux/sched/signal.h> 11 #include <linux/uaccess.h> 12 13 #include <drm/drm_managed.h> 14 15 #include "v3d_drv.h" 16 #include "v3d_regs.h" 17 #include "v3d_trace.h" 18 19 static void 20 v3d_init_core(struct v3d_dev *v3d, int core) 21 { 22 /* Set OVRTMUOUT, which means that the texture sampler uniform 23 * configuration's tmu output type field is used, instead of 24 * using the hardware default behavior based on the texture 25 * type. If you want the default behavior, you can still put 26 * "2" in the indirect texture state's output_type field. 27 */ 28 if (v3d->ver < V3D_GEN_41) 29 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT); 30 31 /* Whenever we flush the L2T cache, we always want to flush 32 * the whole thing. 33 */ 34 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0); 35 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0); 36 } 37 38 /* Sets invariant state for the HW. */ 39 static void 40 v3d_init_hw_state(struct v3d_dev *v3d) 41 { 42 v3d_init_core(v3d, 0); 43 } 44 45 static void 46 v3d_idle_axi(struct v3d_dev *v3d, int core) 47 { 48 V3D_CORE_WRITE(core, V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ); 49 50 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS(v3d->ver)) & 51 (V3D_GMP_STATUS_RD_COUNT_MASK | 52 V3D_GMP_STATUS_WR_COUNT_MASK | 53 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) { 54 DRM_ERROR("Failed to wait for safe GMP shutdown\n"); 55 } 56 } 57 58 static void 59 v3d_idle_gca(struct v3d_dev *v3d) 60 { 61 if (v3d->ver >= V3D_GEN_41) 62 return; 63 64 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN); 65 66 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) & 67 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) == 68 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) { 69 DRM_ERROR("Failed to wait for safe GCA shutdown\n"); 70 } 71 } 72 73 static void 74 v3d_reset_by_bridge(struct v3d_dev *v3d) 75 { 76 int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION); 77 78 if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) { 79 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 80 V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT); 81 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0); 82 83 /* GFXH-1383: The SW_INIT may cause a stray write to address 0 84 * of the unit, so reset it to its power-on value here. 85 */ 86 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK); 87 } else { 88 WARN_ON_ONCE(V3D_GET_FIELD(version, 89 V3D_TOP_GR_BRIDGE_MAJOR) != 7); 90 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 91 V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT); 92 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0); 93 } 94 } 95 96 static void 97 v3d_reset_v3d(struct v3d_dev *v3d) 98 { 99 if (v3d->reset) 100 reset_control_reset(v3d->reset); 101 else 102 v3d_reset_by_bridge(v3d); 103 104 v3d_init_hw_state(v3d); 105 } 106 107 void 108 v3d_reset_sms(struct v3d_dev *v3d) 109 { 110 if (v3d->ver < V3D_GEN_71) 111 return; 112 113 V3D_SMS_WRITE(V3D_SMS_REE_CS, V3D_SET_FIELD(0x4, V3D_SMS_STATE)); 114 115 if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 116 V3D_SMS_STATE) == V3D_SMS_ISOLATING_FOR_RESET) && 117 !(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 118 V3D_SMS_STATE) == V3D_SMS_RESETTING), 100)) { 119 DRM_ERROR("Failed to wait for SMS reset\n"); 120 } 121 } 122 123 void 124 v3d_reset(struct v3d_dev *v3d) 125 { 126 struct drm_device *dev = &v3d->drm; 127 128 DRM_DEV_ERROR(dev->dev, "Resetting GPU for hang.\n"); 129 DRM_DEV_ERROR(dev->dev, "V3D_ERR_STAT: 0x%08x\n", 130 V3D_CORE_READ(0, V3D_ERR_STAT)); 131 trace_v3d_reset_begin(dev); 132 133 /* XXX: only needed for safe powerdown, not reset. */ 134 if (false) 135 v3d_idle_axi(v3d, 0); 136 137 v3d_irq_disable(v3d); 138 139 v3d_idle_gca(v3d); 140 v3d_reset_sms(v3d); 141 v3d_reset_v3d(v3d); 142 143 v3d_mmu_set_page_table(v3d); 144 v3d_irq_reset(v3d); 145 146 v3d_perfmon_stop(v3d, v3d->active_perfmon, false); 147 148 trace_v3d_reset_end(dev); 149 } 150 151 static void 152 v3d_flush_l3(struct v3d_dev *v3d) 153 { 154 if (v3d->ver < V3D_GEN_41) { 155 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL); 156 157 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 158 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH); 159 160 if (v3d->ver < V3D_GEN_33) { 161 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 162 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH); 163 } 164 } 165 } 166 167 /* Invalidates the (read-only) L2C cache. This was the L2 cache for 168 * uniforms and instructions on V3D 3.2. 169 */ 170 static void 171 v3d_invalidate_l2c(struct v3d_dev *v3d, int core) 172 { 173 if (v3d->ver >= V3D_GEN_33) 174 return; 175 176 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL, 177 V3D_L2CACTL_L2CCLR | 178 V3D_L2CACTL_L2CENA); 179 } 180 181 /* Invalidates texture L2 cachelines */ 182 static void 183 v3d_flush_l2t(struct v3d_dev *v3d, int core) 184 { 185 /* While there is a busy bit (V3D_L2TCACTL_L2TFLS), we don't 186 * need to wait for completion before dispatching the job -- 187 * L2T accesses will be stalled until the flush has completed. 188 * However, we do need to make sure we don't try to trigger a 189 * new flush while the L2_CLEAN queue is trying to 190 * synchronously clean after a job. 191 */ 192 mutex_lock(&v3d->cache_clean_lock); 193 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 194 V3D_L2TCACTL_L2TFLS | 195 V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM)); 196 mutex_unlock(&v3d->cache_clean_lock); 197 } 198 199 /* Cleans texture L1 and L2 cachelines (writing back dirty data). 200 * 201 * For cleaning, which happens from the CACHE_CLEAN queue after CSD has 202 * executed, we need to make sure that the clean is done before 203 * signaling job completion. So, we synchronously wait before 204 * returning, and we make sure that L2 invalidates don't happen in the 205 * meantime to confuse our are-we-done checks. 206 */ 207 void 208 v3d_clean_caches(struct v3d_dev *v3d) 209 { 210 struct drm_device *dev = &v3d->drm; 211 int core = 0; 212 213 trace_v3d_cache_clean_begin(dev); 214 215 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); 216 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 217 V3D_L2TCACTL_TMUWCF), 100)) { 218 DRM_ERROR("Timeout waiting for TMU write combiner flush\n"); 219 } 220 221 mutex_lock(&v3d->cache_clean_lock); 222 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 223 V3D_L2TCACTL_L2TFLS | 224 V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAN, V3D_L2TCACTL_FLM)); 225 226 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 227 V3D_L2TCACTL_L2TFLS), 100)) { 228 DRM_ERROR("Timeout waiting for L2T clean\n"); 229 } 230 231 mutex_unlock(&v3d->cache_clean_lock); 232 233 trace_v3d_cache_clean_end(dev); 234 } 235 236 /* Invalidates the slice caches. These are read-only caches. */ 237 static void 238 v3d_invalidate_slices(struct v3d_dev *v3d, int core) 239 { 240 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL, 241 V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) | 242 V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) | 243 V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) | 244 V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC)); 245 } 246 247 void 248 v3d_invalidate_caches(struct v3d_dev *v3d) 249 { 250 /* Invalidate the caches from the outside in. That way if 251 * another CL's concurrent use of nearby memory were to pull 252 * an invalidated cacheline back in, we wouldn't leave stale 253 * data in the inner cache. 254 */ 255 v3d_flush_l3(v3d); 256 v3d_invalidate_l2c(v3d, 0); 257 v3d_flush_l2t(v3d, 0); 258 v3d_invalidate_slices(v3d, 0); 259 } 260 261 int 262 v3d_gem_init(struct drm_device *dev) 263 { 264 struct v3d_dev *v3d = to_v3d_dev(dev); 265 u32 pt_size = 4096 * 1024; 266 int ret, i; 267 268 for (i = 0; i < V3D_MAX_QUEUES; i++) { 269 struct v3d_queue_state *queue = &v3d->queue[i]; 270 271 queue->fence_context = dma_fence_context_alloc(1); 272 memset(&queue->stats, 0, sizeof(queue->stats)); 273 seqcount_init(&queue->stats.lock); 274 } 275 276 spin_lock_init(&v3d->mm_lock); 277 spin_lock_init(&v3d->job_lock); 278 ret = drmm_mutex_init(dev, &v3d->bo_lock); 279 if (ret) 280 return ret; 281 ret = drmm_mutex_init(dev, &v3d->reset_lock); 282 if (ret) 283 return ret; 284 ret = drmm_mutex_init(dev, &v3d->sched_lock); 285 if (ret) 286 return ret; 287 ret = drmm_mutex_init(dev, &v3d->cache_clean_lock); 288 if (ret) 289 return ret; 290 291 /* Note: We don't allocate address 0. Various bits of HW 292 * treat 0 as special, such as the occlusion query counters 293 * where 0 means "disabled". 294 */ 295 drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1); 296 297 v3d->pt = dma_alloc_wc(v3d->drm.dev, pt_size, 298 &v3d->pt_paddr, 299 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 300 if (!v3d->pt) { 301 drm_mm_takedown(&v3d->mm); 302 dev_err(v3d->drm.dev, 303 "Failed to allocate page tables. Please ensure you have DMA enabled.\n"); 304 return -ENOMEM; 305 } 306 307 v3d_init_hw_state(v3d); 308 v3d_mmu_set_page_table(v3d); 309 310 v3d_gemfs_init(v3d); 311 312 ret = v3d_sched_init(v3d); 313 if (ret) { 314 drm_mm_takedown(&v3d->mm); 315 dma_free_coherent(v3d->drm.dev, pt_size, (void *)v3d->pt, 316 v3d->pt_paddr); 317 return ret; 318 } 319 320 return 0; 321 } 322 323 void 324 v3d_gem_destroy(struct drm_device *dev) 325 { 326 struct v3d_dev *v3d = to_v3d_dev(dev); 327 328 v3d_sched_fini(v3d); 329 v3d_gemfs_fini(v3d); 330 331 /* Waiting for jobs to finish would need to be done before 332 * unregistering V3D. 333 */ 334 WARN_ON(v3d->bin_job); 335 WARN_ON(v3d->render_job); 336 WARN_ON(v3d->tfu_job); 337 WARN_ON(v3d->csd_job); 338 339 drm_mm_takedown(&v3d->mm); 340 341 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt, 342 v3d->pt_paddr); 343 } 344