1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 #include <linux/device.h> 5 #include <linux/dma-mapping.h> 6 #include <linux/io.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/reset.h> 10 #include <linux/sched/signal.h> 11 #include <linux/uaccess.h> 12 13 #include <drm/drm_managed.h> 14 #include <drm/drm_print.h> 15 16 #include "v3d_drv.h" 17 #include "v3d_regs.h" 18 #include "v3d_trace.h" 19 20 static void 21 v3d_init_core(struct v3d_dev *v3d, int core) 22 { 23 /* Set OVRTMUOUT, which means that the texture sampler uniform 24 * configuration's tmu output type field is used, instead of 25 * using the hardware default behavior based on the texture 26 * type. If you want the default behavior, you can still put 27 * "2" in the indirect texture state's output_type field. 28 */ 29 if (v3d->ver < V3D_GEN_41) 30 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT); 31 32 /* Whenever we flush the L2T cache, we always want to flush 33 * the whole thing. 34 */ 35 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0); 36 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0); 37 } 38 39 static void 40 v3d_idle_axi(struct v3d_dev *v3d, int core) 41 { 42 V3D_CORE_WRITE(core, V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ); 43 44 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS(v3d->ver)) & 45 (V3D_GMP_STATUS_RD_COUNT_MASK | 46 V3D_GMP_STATUS_WR_COUNT_MASK | 47 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) { 48 drm_err(&v3d->drm, "Failed to wait for safe GMP shutdown\n"); 49 } 50 } 51 52 static void 53 v3d_idle_gca(struct v3d_dev *v3d) 54 { 55 if (v3d->ver >= V3D_GEN_41) 56 return; 57 58 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN); 59 60 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) & 61 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) == 62 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) { 63 drm_err(&v3d->drm, "Failed to wait for safe GCA shutdown\n"); 64 } 65 } 66 67 static void 68 v3d_reset_by_bridge(struct v3d_dev *v3d) 69 { 70 int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION); 71 72 if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) { 73 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 74 V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT); 75 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0); 76 77 /* GFXH-1383: The SW_INIT may cause a stray write to address 0 78 * of the unit, so reset it to its power-on value here. 79 */ 80 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK); 81 } else { 82 WARN_ON_ONCE(V3D_GET_FIELD(version, 83 V3D_TOP_GR_BRIDGE_MAJOR) != 7); 84 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 85 V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT); 86 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0); 87 } 88 } 89 90 static void 91 v3d_reset_v3d(struct v3d_dev *v3d) 92 { 93 if (v3d->reset) 94 reset_control_reset(v3d->reset); 95 else 96 v3d_reset_by_bridge(v3d); 97 98 v3d_init_hw_state(v3d); 99 } 100 101 void 102 v3d_reset_sms(struct v3d_dev *v3d) 103 { 104 if (v3d->ver < V3D_GEN_71) 105 return; 106 107 V3D_SMS_WRITE(V3D_SMS_REE_CS, V3D_SET_FIELD(0x4, V3D_SMS_STATE)); 108 109 if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 110 V3D_SMS_STATE) == V3D_SMS_ISOLATING_FOR_RESET) && 111 !(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 112 V3D_SMS_STATE) == V3D_SMS_RESETTING), 100)) { 113 drm_err(&v3d->drm, "Failed to wait for SMS reset\n"); 114 } 115 } 116 117 void 118 v3d_reset(struct v3d_dev *v3d) 119 { 120 struct drm_device *dev = &v3d->drm; 121 122 drm_err(dev, "Resetting GPU for hang.\n"); 123 drm_err(dev, "V3D_ERR_STAT: 0x%08x\n", V3D_CORE_READ(0, V3D_ERR_STAT)); 124 125 trace_v3d_reset_begin(dev); 126 127 /* XXX: only needed for safe powerdown, not reset. */ 128 if (false) 129 v3d_idle_axi(v3d, 0); 130 131 v3d_irq_disable(v3d); 132 133 v3d_idle_gca(v3d); 134 v3d_reset_sms(v3d); 135 v3d_reset_v3d(v3d); 136 137 v3d_mmu_set_page_table(v3d); 138 v3d_irq_reset(v3d); 139 140 /* Re-arm the global perfmon HW counters that the reset zeroed. */ 141 v3d_perfmon_resume(v3d); 142 143 trace_v3d_reset_end(dev); 144 } 145 146 static void 147 v3d_flush_l3(struct v3d_dev *v3d) 148 { 149 if (v3d->ver < V3D_GEN_41) { 150 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL); 151 152 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 153 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH); 154 155 if (v3d->ver < V3D_GEN_33) { 156 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 157 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH); 158 } 159 } 160 } 161 162 /* Invalidates the (read-only) L2C cache. This was the L2 cache for 163 * uniforms and instructions on V3D 3.2. 164 */ 165 static void 166 v3d_invalidate_l2c(struct v3d_dev *v3d, int core) 167 { 168 if (v3d->ver >= V3D_GEN_33) 169 return; 170 171 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL, 172 V3D_L2CACTL_L2CCLR | 173 V3D_L2CACTL_L2CENA); 174 } 175 176 /* Invalidates texture L2 cachelines */ 177 static void 178 v3d_flush_l2t(struct v3d_dev *v3d, int core) 179 { 180 /* While there is a busy bit (V3D_L2TCACTL_L2TFLS), we don't 181 * need to wait for completion before dispatching the job -- 182 * L2T accesses will be stalled until the flush has completed. 183 * However, we do need to make sure we don't try to trigger a 184 * new flush while the L2_CLEAN queue is trying to 185 * synchronously clean after a job. 186 */ 187 mutex_lock(&v3d->cache_clean_lock); 188 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 189 V3D_L2TCACTL_L2TFLS | 190 V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM)); 191 mutex_unlock(&v3d->cache_clean_lock); 192 } 193 194 /* Cleans texture L1 and L2 cachelines (writing back dirty data). 195 * 196 * For cleaning, which happens from the CACHE_CLEAN queue after CSD has 197 * executed, we need to make sure that the clean is done before 198 * signaling job completion. So, we synchronously wait before 199 * returning, and we make sure that L2 invalidates don't happen in the 200 * meantime to confuse our are-we-done checks. 201 */ 202 void 203 v3d_clean_caches(struct v3d_dev *v3d) 204 { 205 struct drm_device *dev = &v3d->drm; 206 int core = 0; 207 208 trace_v3d_cache_clean_begin(dev); 209 210 /* GFXH-1897: Ensure pending flushes complete before writing L2TCACTL */ 211 if (v3d->ver < V3D_GEN_71) { 212 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 213 V3D_L2TCACTL_L2TFLS), 100)) { 214 drm_err(dev, "Timeout waiting for L2T clean\n"); 215 } 216 } 217 218 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); 219 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 220 V3D_L2TCACTL_TMUWCF), 100)) { 221 drm_err(dev, "Timeout waiting for TMU write combiner flush\n"); 222 } 223 224 mutex_lock(&v3d->cache_clean_lock); 225 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 226 V3D_L2TCACTL_L2TFLS | 227 V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAN, V3D_L2TCACTL_FLM)); 228 229 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 230 V3D_L2TCACTL_L2TFLS), 100)) { 231 drm_err(dev, "Timeout waiting for L2T clean\n"); 232 } 233 234 mutex_unlock(&v3d->cache_clean_lock); 235 236 trace_v3d_cache_clean_end(dev); 237 } 238 239 /* Invalidates the slice caches. These are read-only caches. */ 240 static void 241 v3d_invalidate_slices(struct v3d_dev *v3d, int core) 242 { 243 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL, 244 V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) | 245 V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) | 246 V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) | 247 V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC)); 248 } 249 250 void 251 v3d_invalidate_caches(struct v3d_dev *v3d) 252 { 253 /* Invalidate the caches from the outside in. That way if 254 * another CL's concurrent use of nearby memory were to pull 255 * an invalidated cacheline back in, we wouldn't leave stale 256 * data in the inner cache. 257 */ 258 v3d_flush_l3(v3d); 259 v3d_invalidate_l2c(v3d, 0); 260 v3d_flush_l2t(v3d, 0); 261 v3d_invalidate_slices(v3d, 0); 262 } 263 264 /* Sets invariant state for the HW. */ 265 void 266 v3d_init_hw_state(struct v3d_dev *v3d) 267 { 268 v3d_init_core(v3d, 0); 269 } 270 271 static void 272 v3d_huge_mnt_init(struct v3d_dev *v3d) 273 { 274 int err = 0; 275 276 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) && super_pages) 277 err = drm_gem_huge_mnt_create(&v3d->drm, "within_size"); 278 279 if (drm_gem_get_huge_mnt(&v3d->drm)) 280 drm_info(&v3d->drm, "Using Transparent Hugepages\n"); 281 else if (err) 282 drm_warn(&v3d->drm, "Can't use Transparent Hugepages (%d)\n", 283 err); 284 else 285 drm_notice(&v3d->drm, 286 "Transparent Hugepage support is recommended for optimal performance on this platform!\n"); 287 } 288 289 int 290 v3d_gem_init(struct drm_device *dev) 291 { 292 struct v3d_dev *v3d = to_v3d_dev(dev); 293 u32 pt_size = 4096 * 1024; 294 int ret, i; 295 296 for (i = 0; i < V3D_MAX_QUEUES; i++) { 297 struct v3d_queue_state *queue = &v3d->queue[i]; 298 299 queue->stats = v3d_stats_alloc(); 300 if (!queue->stats) { 301 ret = -ENOMEM; 302 goto err_stats; 303 } 304 305 queue->fence_context = dma_fence_context_alloc(1); 306 307 spin_lock_init(&queue->queue_lock); 308 } 309 310 spin_lock_init(&v3d->mm_lock); 311 spin_lock_init(&v3d->perfmon_state.lock); 312 ret = drmm_mutex_init(dev, &v3d->bo_lock); 313 if (ret) 314 goto err_stats; 315 ret = drmm_mutex_init(dev, &v3d->reset_lock); 316 if (ret) 317 goto err_stats; 318 ret = drmm_mutex_init(dev, &v3d->sched_lock); 319 if (ret) 320 goto err_stats; 321 ret = drmm_mutex_init(dev, &v3d->cache_clean_lock); 322 if (ret) 323 goto err_stats; 324 325 /* Note: We don't allocate address 0. Various bits of HW 326 * treat 0 as special, such as the occlusion query counters 327 * where 0 means "disabled". 328 */ 329 drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1); 330 331 v3d->pt = dma_alloc_wc(v3d->drm.dev, pt_size, 332 &v3d->pt_paddr, 333 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 334 if (!v3d->pt) { 335 dev_err(v3d->drm.dev, 336 "Failed to allocate page tables. Please ensure you have DMA enabled.\n"); 337 ret = -ENOMEM; 338 goto err_dma_alloc; 339 } 340 341 v3d_huge_mnt_init(v3d); 342 343 ret = v3d_sched_init(v3d); 344 if (ret) 345 goto err_sched; 346 347 return 0; 348 349 err_sched: 350 dma_free_coherent(v3d->drm.dev, pt_size, (void *)v3d->pt, v3d->pt_paddr); 351 err_dma_alloc: 352 drm_mm_takedown(&v3d->mm); 353 err_stats: 354 for (i--; i >= 0; i--) 355 v3d_stats_put(v3d->queue[i].stats); 356 357 return ret; 358 } 359 360 void 361 v3d_gem_destroy(struct drm_device *dev) 362 { 363 struct v3d_dev *v3d = to_v3d_dev(dev); 364 enum v3d_queue q; 365 366 v3d_sched_fini(v3d); 367 368 /* Waiting for jobs to finish would need to be done before 369 * unregistering V3D. 370 */ 371 for (q = 0; q < V3D_MAX_QUEUES; q++) { 372 WARN_ON(v3d->queue[q].active_job); 373 v3d_stats_put(v3d->queue[q].stats); 374 dma_fence_put(v3d->perfmon_state.last_hw_fence[q]); 375 } 376 377 dma_fence_put(v3d->perfmon_state.fence); 378 379 drm_mm_takedown(&v3d->mm); 380 381 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt, 382 v3d->pt_paddr); 383 } 384