1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 #include <linux/device.h> 5 #include <linux/dma-mapping.h> 6 #include <linux/io.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/reset.h> 10 #include <linux/sched/signal.h> 11 #include <linux/uaccess.h> 12 13 #include <drm/drm_managed.h> 14 #include <drm/drm_print.h> 15 16 #include "v3d_drv.h" 17 #include "v3d_regs.h" 18 #include "v3d_trace.h" 19 20 static void 21 v3d_init_core(struct v3d_dev *v3d, int core) 22 { 23 /* Set OVRTMUOUT, which means that the texture sampler uniform 24 * configuration's tmu output type field is used, instead of 25 * using the hardware default behavior based on the texture 26 * type. If you want the default behavior, you can still put 27 * "2" in the indirect texture state's output_type field. 28 */ 29 if (v3d->ver < V3D_GEN_41) 30 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT); 31 32 /* Whenever we flush the L2T cache, we always want to flush 33 * the whole thing. 34 */ 35 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0); 36 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0); 37 } 38 39 void 40 v3d_idle_axi(struct v3d_dev *v3d, int core) 41 { 42 if (v3d->ver >= V3D_GEN_71) { 43 V3D_WRITE(V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ); 44 45 if (wait_for((V3D_READ(V3D_GMP_STATUS(v3d->ver)) & 46 (V3D_GMP_STATUS_RD_COUNT_MASK | 47 V3D_GMP_STATUS_WR_COUNT_MASK | 48 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) { 49 drm_err(&v3d->drm, "Failed to wait for safe GMP shutdown\n"); 50 } 51 return; 52 } 53 54 V3D_CORE_WRITE(core, V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ); 55 56 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS(v3d->ver)) & 57 (V3D_GMP_STATUS_RD_COUNT_MASK | 58 V3D_GMP_STATUS_WR_COUNT_MASK | 59 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) { 60 drm_err(&v3d->drm, "Failed to wait for safe GMP shutdown\n"); 61 } 62 } 63 64 void 65 v3d_idle_gca(struct v3d_dev *v3d) 66 { 67 if (v3d->ver >= V3D_GEN_41) 68 return; 69 70 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN); 71 72 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) & 73 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) == 74 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) { 75 drm_err(&v3d->drm, "Failed to wait for safe GCA shutdown\n"); 76 } 77 } 78 79 static void 80 v3d_reset_by_bridge(struct v3d_dev *v3d) 81 { 82 int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION); 83 84 if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) { 85 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 86 V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT); 87 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0); 88 89 /* GFXH-1383: The SW_INIT may cause a stray write to address 0 90 * of the unit, so reset it to its power-on value here. 91 */ 92 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK); 93 } else { 94 WARN_ON_ONCE(V3D_GET_FIELD(version, 95 V3D_TOP_GR_BRIDGE_MAJOR) != 7); 96 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 97 V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT); 98 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0); 99 } 100 } 101 102 static void 103 v3d_reset_v3d(struct v3d_dev *v3d) 104 { 105 if (v3d->reset) 106 reset_control_reset(v3d->reset); 107 else 108 v3d_reset_by_bridge(v3d); 109 110 v3d_init_hw_state(v3d); 111 } 112 113 void 114 v3d_reset_sms(struct v3d_dev *v3d) 115 { 116 if (v3d->ver < V3D_GEN_71) 117 return; 118 119 V3D_SMS_WRITE(V3D_SMS_REE_CS, V3D_SET_FIELD(0x4, V3D_SMS_STATE)); 120 121 if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 122 V3D_SMS_STATE) == V3D_SMS_ISOLATING_FOR_RESET) && 123 !(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 124 V3D_SMS_STATE) == V3D_SMS_RESETTING), 100)) { 125 drm_err(&v3d->drm, "Failed to wait for SMS reset\n"); 126 } 127 } 128 129 void 130 v3d_reset(struct v3d_dev *v3d) 131 { 132 struct drm_device *dev = &v3d->drm; 133 134 drm_err(dev, "Resetting GPU for hang.\n"); 135 drm_err(dev, "V3D_ERR_STAT: 0x%08x\n", V3D_CORE_READ(0, V3D_ERR_STAT)); 136 137 trace_v3d_reset_begin(dev); 138 139 /* XXX: only needed for safe powerdown, not reset. */ 140 if (false) 141 v3d_idle_axi(v3d, 0); 142 143 v3d_irq_disable(v3d); 144 145 v3d_idle_gca(v3d); 146 v3d_reset_sms(v3d); 147 v3d_reset_v3d(v3d); 148 149 v3d_mmu_set_page_table(v3d); 150 v3d_irq_reset(v3d); 151 152 v3d_perfmon_stop(v3d, v3d->active_perfmon, false); 153 154 trace_v3d_reset_end(dev); 155 } 156 157 static void 158 v3d_flush_l3(struct v3d_dev *v3d) 159 { 160 if (v3d->ver < V3D_GEN_41) { 161 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL); 162 163 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 164 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH); 165 166 if (v3d->ver < V3D_GEN_33) { 167 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 168 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH); 169 } 170 } 171 } 172 173 /* Invalidates the (read-only) L2C cache. This was the L2 cache for 174 * uniforms and instructions on V3D 3.2. 175 */ 176 static void 177 v3d_invalidate_l2c(struct v3d_dev *v3d, int core) 178 { 179 if (v3d->ver >= V3D_GEN_33) 180 return; 181 182 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL, 183 V3D_L2CACTL_L2CCLR | 184 V3D_L2CACTL_L2CENA); 185 } 186 187 /* Invalidates texture L2 cachelines */ 188 static void 189 v3d_flush_l2t(struct v3d_dev *v3d, int core) 190 { 191 /* While there is a busy bit (V3D_L2TCACTL_L2TFLS), we don't 192 * need to wait for completion before dispatching the job -- 193 * L2T accesses will be stalled until the flush has completed. 194 * However, we do need to make sure we don't try to trigger a 195 * new flush while the L2_CLEAN queue is trying to 196 * synchronously clean after a job. 197 */ 198 mutex_lock(&v3d->cache_clean_lock); 199 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 200 V3D_L2TCACTL_L2TFLS | 201 V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM)); 202 mutex_unlock(&v3d->cache_clean_lock); 203 } 204 205 /* Cleans texture L1 and L2 cachelines (writing back dirty data). 206 * 207 * For cleaning, which happens from the CACHE_CLEAN queue after CSD has 208 * executed, we need to make sure that the clean is done before 209 * signaling job completion. So, we synchronously wait before 210 * returning, and we make sure that L2 invalidates don't happen in the 211 * meantime to confuse our are-we-done checks. 212 */ 213 void 214 v3d_clean_caches(struct v3d_dev *v3d) 215 { 216 struct drm_device *dev = &v3d->drm; 217 int core = 0; 218 219 trace_v3d_cache_clean_begin(dev); 220 221 /* GFXH-1897: Ensure pending flushes complete before writing L2TCACTL */ 222 if (v3d->ver < V3D_GEN_71) { 223 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 224 V3D_L2TCACTL_L2TFLS), 100)) { 225 drm_err(dev, "Timeout waiting for L2T clean\n"); 226 } 227 } 228 229 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); 230 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 231 V3D_L2TCACTL_TMUWCF), 100)) { 232 drm_err(dev, "Timeout waiting for TMU write combiner flush\n"); 233 } 234 235 mutex_lock(&v3d->cache_clean_lock); 236 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 237 V3D_L2TCACTL_L2TFLS | 238 V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAN, V3D_L2TCACTL_FLM)); 239 240 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 241 V3D_L2TCACTL_L2TFLS), 100)) { 242 drm_err(dev, "Timeout waiting for L2T clean\n"); 243 } 244 245 mutex_unlock(&v3d->cache_clean_lock); 246 247 trace_v3d_cache_clean_end(dev); 248 } 249 250 /* Invalidates the slice caches. These are read-only caches. */ 251 static void 252 v3d_invalidate_slices(struct v3d_dev *v3d, int core) 253 { 254 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL, 255 V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) | 256 V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) | 257 V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) | 258 V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC)); 259 } 260 261 void 262 v3d_invalidate_caches(struct v3d_dev *v3d) 263 { 264 /* Invalidate the caches from the outside in. That way if 265 * another CL's concurrent use of nearby memory were to pull 266 * an invalidated cacheline back in, we wouldn't leave stale 267 * data in the inner cache. 268 */ 269 v3d_flush_l3(v3d); 270 v3d_invalidate_l2c(v3d, 0); 271 v3d_flush_l2t(v3d, 0); 272 v3d_invalidate_slices(v3d, 0); 273 } 274 275 /* Sets invariant state for the HW. */ 276 void 277 v3d_init_hw_state(struct v3d_dev *v3d) 278 { 279 v3d_init_core(v3d, 0); 280 } 281 282 static void 283 v3d_huge_mnt_init(struct v3d_dev *v3d) 284 { 285 int err = 0; 286 287 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) && super_pages) 288 err = drm_gem_huge_mnt_create(&v3d->drm, "within_size"); 289 290 if (drm_gem_get_huge_mnt(&v3d->drm)) 291 drm_info(&v3d->drm, "Using Transparent Hugepages\n"); 292 else if (err) 293 drm_warn(&v3d->drm, "Can't use Transparent Hugepages (%d)\n", 294 err); 295 else 296 drm_notice(&v3d->drm, 297 "Transparent Hugepage support is recommended for optimal performance on this platform!\n"); 298 } 299 300 int 301 v3d_gem_init(struct drm_device *dev) 302 { 303 struct v3d_dev *v3d = to_v3d_dev(dev); 304 u32 pt_size = 4096 * 1024; 305 int ret, i; 306 307 for (i = 0; i < V3D_MAX_QUEUES; i++) { 308 struct v3d_queue_state *queue = &v3d->queue[i]; 309 310 queue->stats = v3d_stats_alloc(); 311 if (!queue->stats) { 312 ret = -ENOMEM; 313 goto err_stats; 314 } 315 316 queue->fence_context = dma_fence_context_alloc(1); 317 318 spin_lock_init(&queue->queue_lock); 319 } 320 321 spin_lock_init(&v3d->mm_lock); 322 ret = drmm_mutex_init(dev, &v3d->bo_lock); 323 if (ret) 324 goto err_stats; 325 ret = drmm_mutex_init(dev, &v3d->reset_lock); 326 if (ret) 327 goto err_stats; 328 ret = drmm_mutex_init(dev, &v3d->sched_lock); 329 if (ret) 330 goto err_stats; 331 ret = drmm_mutex_init(dev, &v3d->cache_clean_lock); 332 if (ret) 333 goto err_stats; 334 335 /* Note: We don't allocate address 0. Various bits of HW 336 * treat 0 as special, such as the occlusion query counters 337 * where 0 means "disabled". 338 */ 339 drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1); 340 341 v3d->pt = dma_alloc_wc(v3d->drm.dev, pt_size, 342 &v3d->pt_paddr, 343 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 344 if (!v3d->pt) { 345 dev_err(v3d->drm.dev, 346 "Failed to allocate page tables. Please ensure you have DMA enabled.\n"); 347 ret = -ENOMEM; 348 goto err_dma_alloc; 349 } 350 351 v3d_huge_mnt_init(v3d); 352 353 ret = v3d_sched_init(v3d); 354 if (ret) 355 goto err_sched; 356 357 return 0; 358 359 err_sched: 360 dma_free_coherent(v3d->drm.dev, pt_size, (void *)v3d->pt, v3d->pt_paddr); 361 err_dma_alloc: 362 drm_mm_takedown(&v3d->mm); 363 err_stats: 364 for (i--; i >= 0; i--) 365 v3d_stats_put(v3d->queue[i].stats); 366 367 return ret; 368 } 369 370 void 371 v3d_gem_destroy(struct drm_device *dev) 372 { 373 struct v3d_dev *v3d = to_v3d_dev(dev); 374 enum v3d_queue q; 375 376 v3d_sched_fini(v3d); 377 378 /* Waiting for jobs to finish would need to be done before 379 * unregistering V3D. 380 */ 381 for (q = 0; q < V3D_MAX_QUEUES; q++) { 382 WARN_ON(v3d->queue[q].active_job); 383 v3d_stats_put(v3d->queue[q].stats); 384 } 385 386 drm_mm_takedown(&v3d->mm); 387 388 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt, 389 v3d->pt_paddr); 390 } 391