1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 #include <linux/device.h> 5 #include <linux/dma-mapping.h> 6 #include <linux/io.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/reset.h> 10 #include <linux/sched/signal.h> 11 #include <linux/uaccess.h> 12 13 #include <drm/drm_managed.h> 14 #include <drm/drm_print.h> 15 16 #include "v3d_drv.h" 17 #include "v3d_regs.h" 18 #include "v3d_trace.h" 19 20 static void 21 v3d_init_core(struct v3d_dev *v3d, int core) 22 { 23 /* Set OVRTMUOUT, which means that the texture sampler uniform 24 * configuration's tmu output type field is used, instead of 25 * using the hardware default behavior based on the texture 26 * type. If you want the default behavior, you can still put 27 * "2" in the indirect texture state's output_type field. 28 */ 29 if (v3d->ver < V3D_GEN_41) 30 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT); 31 32 /* Whenever we flush the L2T cache, we always want to flush 33 * the whole thing. 34 */ 35 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0); 36 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0); 37 } 38 39 void 40 v3d_idle_axi(struct v3d_dev *v3d, int core) 41 { 42 if (v3d->ver >= V3D_GEN_71) { 43 V3D_WRITE(V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ); 44 45 if (wait_for((V3D_READ(V3D_GMP_STATUS(v3d->ver)) & 46 (V3D_GMP_STATUS_RD_COUNT_MASK | 47 V3D_GMP_STATUS_WR_COUNT_MASK | 48 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) { 49 drm_err(&v3d->drm, "Failed to wait for safe GMP shutdown\n"); 50 } 51 return; 52 } 53 54 V3D_CORE_WRITE(core, V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ); 55 56 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS(v3d->ver)) & 57 (V3D_GMP_STATUS_RD_COUNT_MASK | 58 V3D_GMP_STATUS_WR_COUNT_MASK | 59 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) { 60 drm_err(&v3d->drm, "Failed to wait for safe GMP shutdown\n"); 61 } 62 } 63 64 void 65 v3d_idle_gca(struct v3d_dev *v3d) 66 { 67 if (v3d->ver >= V3D_GEN_41) 68 return; 69 70 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN); 71 72 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) & 73 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) == 74 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) { 75 drm_err(&v3d->drm, "Failed to wait for safe GCA shutdown\n"); 76 } 77 } 78 79 static void 80 v3d_reset_by_bridge(struct v3d_dev *v3d) 81 { 82 int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION); 83 84 if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) { 85 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 86 V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT); 87 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0); 88 89 /* GFXH-1383: The SW_INIT may cause a stray write to address 0 90 * of the unit, so reset it to its power-on value here. 91 */ 92 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK); 93 } else { 94 WARN_ON_ONCE(V3D_GET_FIELD(version, 95 V3D_TOP_GR_BRIDGE_MAJOR) != 7); 96 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 97 V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT); 98 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0); 99 } 100 } 101 102 static void 103 v3d_reset_v3d(struct v3d_dev *v3d) 104 { 105 if (v3d->reset) 106 reset_control_reset(v3d->reset); 107 else 108 v3d_reset_by_bridge(v3d); 109 110 v3d_init_hw_state(v3d); 111 } 112 113 void 114 v3d_reset_sms(struct v3d_dev *v3d) 115 { 116 if (v3d->ver < V3D_GEN_71) 117 return; 118 119 V3D_SMS_WRITE(V3D_SMS_REE_CS, V3D_SET_FIELD(0x4, V3D_SMS_STATE)); 120 121 if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 122 V3D_SMS_STATE) == V3D_SMS_ISOLATING_FOR_RESET) && 123 !(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 124 V3D_SMS_STATE) == V3D_SMS_RESETTING), 100)) { 125 drm_err(&v3d->drm, "Failed to wait for SMS reset\n"); 126 } 127 } 128 129 void 130 v3d_reset(struct v3d_dev *v3d) 131 { 132 struct drm_device *dev = &v3d->drm; 133 134 drm_err(dev, "Resetting GPU for hang.\n"); 135 drm_err(dev, "V3D_ERR_STAT: 0x%08x\n", V3D_CORE_READ(0, V3D_ERR_STAT)); 136 137 trace_v3d_reset_begin(dev); 138 139 /* XXX: only needed for safe powerdown, not reset. */ 140 if (false) 141 v3d_idle_axi(v3d, 0); 142 143 v3d_irq_disable(v3d); 144 145 v3d_idle_gca(v3d); 146 v3d_reset_sms(v3d); 147 v3d_reset_v3d(v3d); 148 149 v3d_mmu_set_page_table(v3d); 150 v3d_irq_reset(v3d); 151 152 /* Re-arm the global perfmon HW counters that the reset zeroed. */ 153 v3d_perfmon_resume(v3d); 154 155 trace_v3d_reset_end(dev); 156 } 157 158 static void 159 v3d_flush_l3(struct v3d_dev *v3d) 160 { 161 if (v3d->ver < V3D_GEN_41) { 162 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL); 163 164 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 165 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH); 166 167 if (v3d->ver < V3D_GEN_33) { 168 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 169 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH); 170 } 171 } 172 } 173 174 /* Invalidates the (read-only) L2C cache. This was the L2 cache for 175 * uniforms and instructions on V3D 3.2. 176 */ 177 static void 178 v3d_invalidate_l2c(struct v3d_dev *v3d, int core) 179 { 180 if (v3d->ver >= V3D_GEN_33) 181 return; 182 183 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL, 184 V3D_L2CACTL_L2CCLR | 185 V3D_L2CACTL_L2CENA); 186 } 187 188 /* Invalidates texture L2 cachelines */ 189 static void 190 v3d_flush_l2t(struct v3d_dev *v3d, int core) 191 { 192 /* While there is a busy bit (V3D_L2TCACTL_L2TFLS), we don't 193 * need to wait for completion before dispatching the job -- 194 * L2T accesses will be stalled until the flush has completed. 195 * However, we do need to make sure we don't try to trigger a 196 * new flush while the L2_CLEAN queue is trying to 197 * synchronously clean after a job. 198 */ 199 mutex_lock(&v3d->cache_clean_lock); 200 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 201 V3D_L2TCACTL_L2TFLS | 202 V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM)); 203 mutex_unlock(&v3d->cache_clean_lock); 204 } 205 206 /* Cleans texture L1 and L2 cachelines (writing back dirty data). 207 * 208 * For cleaning, which happens from the CACHE_CLEAN queue after CSD has 209 * executed, we need to make sure that the clean is done before 210 * signaling job completion. So, we synchronously wait before 211 * returning, and we make sure that L2 invalidates don't happen in the 212 * meantime to confuse our are-we-done checks. 213 */ 214 void 215 v3d_clean_caches(struct v3d_dev *v3d) 216 { 217 struct drm_device *dev = &v3d->drm; 218 int core = 0; 219 220 trace_v3d_cache_clean_begin(dev); 221 222 /* GFXH-1897: Ensure pending flushes complete before writing L2TCACTL */ 223 if (v3d->ver < V3D_GEN_71) { 224 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 225 V3D_L2TCACTL_L2TFLS), 100)) { 226 drm_err(dev, "Timeout waiting for L2T clean\n"); 227 } 228 } 229 230 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); 231 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 232 V3D_L2TCACTL_TMUWCF), 100)) { 233 drm_err(dev, "Timeout waiting for TMU write combiner flush\n"); 234 } 235 236 mutex_lock(&v3d->cache_clean_lock); 237 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 238 V3D_L2TCACTL_L2TFLS | 239 V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAN, V3D_L2TCACTL_FLM)); 240 241 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 242 V3D_L2TCACTL_L2TFLS), 100)) { 243 drm_err(dev, "Timeout waiting for L2T clean\n"); 244 } 245 246 mutex_unlock(&v3d->cache_clean_lock); 247 248 trace_v3d_cache_clean_end(dev); 249 } 250 251 /* Invalidates the slice caches. These are read-only caches. */ 252 static void 253 v3d_invalidate_slices(struct v3d_dev *v3d, int core) 254 { 255 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL, 256 V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) | 257 V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) | 258 V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) | 259 V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC)); 260 } 261 262 void 263 v3d_invalidate_caches(struct v3d_dev *v3d) 264 { 265 /* Invalidate the caches from the outside in. That way if 266 * another CL's concurrent use of nearby memory were to pull 267 * an invalidated cacheline back in, we wouldn't leave stale 268 * data in the inner cache. 269 */ 270 v3d_flush_l3(v3d); 271 v3d_invalidate_l2c(v3d, 0); 272 v3d_flush_l2t(v3d, 0); 273 v3d_invalidate_slices(v3d, 0); 274 } 275 276 /* Sets invariant state for the HW. */ 277 void 278 v3d_init_hw_state(struct v3d_dev *v3d) 279 { 280 v3d_init_core(v3d, 0); 281 } 282 283 static void 284 v3d_huge_mnt_init(struct v3d_dev *v3d) 285 { 286 int err = 0; 287 288 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) && super_pages) 289 err = drm_gem_huge_mnt_create(&v3d->drm, "within_size"); 290 291 if (drm_gem_get_huge_mnt(&v3d->drm)) 292 drm_info(&v3d->drm, "Using Transparent Hugepages\n"); 293 else if (err) 294 drm_warn(&v3d->drm, "Can't use Transparent Hugepages (%d)\n", 295 err); 296 else 297 drm_notice(&v3d->drm, 298 "Transparent Hugepage support is recommended for optimal performance on this platform!\n"); 299 } 300 301 int 302 v3d_gem_init(struct drm_device *dev) 303 { 304 struct v3d_dev *v3d = to_v3d_dev(dev); 305 u32 pt_size = 4096 * 1024; 306 int ret, i; 307 308 for (i = 0; i < V3D_MAX_QUEUES; i++) { 309 struct v3d_queue_state *queue = &v3d->queue[i]; 310 311 queue->stats = v3d_stats_alloc(); 312 if (!queue->stats) { 313 ret = -ENOMEM; 314 goto err_stats; 315 } 316 317 queue->fence_context = dma_fence_context_alloc(1); 318 319 spin_lock_init(&queue->queue_lock); 320 } 321 322 spin_lock_init(&v3d->mm_lock); 323 spin_lock_init(&v3d->perfmon_state.lock); 324 ret = drmm_mutex_init(dev, &v3d->bo_lock); 325 if (ret) 326 goto err_stats; 327 ret = drmm_mutex_init(dev, &v3d->reset_lock); 328 if (ret) 329 goto err_stats; 330 ret = drmm_mutex_init(dev, &v3d->sched_lock); 331 if (ret) 332 goto err_stats; 333 ret = drmm_mutex_init(dev, &v3d->cache_clean_lock); 334 if (ret) 335 goto err_stats; 336 337 /* Note: We don't allocate address 0. Various bits of HW 338 * treat 0 as special, such as the occlusion query counters 339 * where 0 means "disabled". 340 */ 341 drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1); 342 343 v3d->pt = dma_alloc_wc(v3d->drm.dev, pt_size, 344 &v3d->pt_paddr, 345 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 346 if (!v3d->pt) { 347 dev_err(v3d->drm.dev, 348 "Failed to allocate page tables. Please ensure you have DMA enabled.\n"); 349 ret = -ENOMEM; 350 goto err_dma_alloc; 351 } 352 353 v3d_huge_mnt_init(v3d); 354 355 ret = v3d_sched_init(v3d); 356 if (ret) 357 goto err_sched; 358 359 return 0; 360 361 err_sched: 362 dma_free_coherent(v3d->drm.dev, pt_size, (void *)v3d->pt, v3d->pt_paddr); 363 err_dma_alloc: 364 drm_mm_takedown(&v3d->mm); 365 err_stats: 366 for (i--; i >= 0; i--) 367 v3d_stats_put(v3d->queue[i].stats); 368 369 return ret; 370 } 371 372 void 373 v3d_gem_destroy(struct drm_device *dev) 374 { 375 struct v3d_dev *v3d = to_v3d_dev(dev); 376 enum v3d_queue q; 377 378 v3d_sched_fini(v3d); 379 380 /* Waiting for jobs to finish would need to be done before 381 * unregistering V3D. 382 */ 383 for (q = 0; q < V3D_MAX_QUEUES; q++) { 384 WARN_ON(v3d->queue[q].active_job); 385 v3d_stats_put(v3d->queue[q].stats); 386 dma_fence_put(v3d->perfmon_state.last_hw_fence[q]); 387 } 388 389 dma_fence_put(v3d->perfmon_state.fence); 390 391 drm_mm_takedown(&v3d->mm); 392 393 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt, 394 v3d->pt_paddr); 395 } 396