1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/spinlock_types.h> 7 #include <linux/workqueue.h> 8 9 #include <drm/drm_encoder.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_gem_shmem_helper.h> 12 #include <drm/gpu_scheduler.h> 13 14 #include "v3d_performance_counters.h" 15 16 #include "uapi/drm/v3d_drm.h" 17 18 struct clk; 19 struct platform_device; 20 struct reset_control; 21 22 #define V3D_MMU_PAGE_SHIFT 12 23 #define V3D_PAGE_FACTOR (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) 24 25 #define V3D_MAX_QUEUES (V3D_CPU + 1) 26 27 static inline char *v3d_queue_to_string(enum v3d_queue queue) 28 { 29 switch (queue) { 30 case V3D_BIN: return "bin"; 31 case V3D_RENDER: return "render"; 32 case V3D_TFU: return "tfu"; 33 case V3D_CSD: return "csd"; 34 case V3D_CACHE_CLEAN: return "cache_clean"; 35 case V3D_CPU: return "cpu"; 36 } 37 return "UNKNOWN"; 38 } 39 40 struct v3d_stats { 41 u64 start_ns; 42 u64 enabled_ns; 43 u64 jobs_completed; 44 45 /* 46 * This seqcount is used to protect the access to the GPU stats 47 * variables. It must be used as, while we are reading the stats, 48 * IRQs can happen and the stats can be updated. 49 */ 50 seqcount_t lock; 51 }; 52 53 struct v3d_queue_state { 54 struct drm_gpu_scheduler sched; 55 56 u64 fence_context; 57 u64 emit_seqno; 58 59 /* Stores the GPU stats for this queue in the global context. */ 60 struct v3d_stats stats; 61 }; 62 63 /* Performance monitor object. The perform lifetime is controlled by userspace 64 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 65 * request, and when this is the case, HW perf counters will be activated just 66 * before the submit_cl is submitted to the GPU and disabled when the job is 67 * done. This way, only events related to a specific job will be counted. 68 */ 69 struct v3d_perfmon { 70 /* Tracks the number of users of the perfmon, when this counter reaches 71 * zero the perfmon is destroyed. 72 */ 73 refcount_t refcnt; 74 75 /* Protects perfmon stop, as it can be invoked from multiple places. */ 76 struct mutex lock; 77 78 /* Number of counters activated in this perfmon instance 79 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 80 */ 81 u8 ncounters; 82 83 /* Events counted by the HW perf counters. */ 84 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 85 86 /* Storage for counter values. Counters are incremented by the 87 * HW perf counter values every time the perfmon is attached 88 * to a GPU job. This way, perfmon users don't have to 89 * retrieve the results after each job if they want to track 90 * events covering several submissions. Note that counter 91 * values can't be reset, but you can fake a reset by 92 * destroying the perfmon and creating a new one. 93 */ 94 u64 values[] __counted_by(ncounters); 95 }; 96 97 enum v3d_gen { 98 V3D_GEN_33 = 33, 99 V3D_GEN_41 = 41, 100 V3D_GEN_42 = 42, 101 V3D_GEN_71 = 71, 102 }; 103 104 struct v3d_dev { 105 struct drm_device drm; 106 107 /* Short representation (e.g. 33, 41) of the V3D tech version */ 108 enum v3d_gen ver; 109 110 /* Short representation (e.g. 5, 6) of the V3D tech revision */ 111 int rev; 112 113 bool single_irq_line; 114 115 struct v3d_perfmon_info perfmon_info; 116 117 void __iomem *hub_regs; 118 void __iomem *core_regs[3]; 119 void __iomem *bridge_regs; 120 void __iomem *gca_regs; 121 void __iomem *sms_regs; 122 struct clk *clk; 123 struct reset_control *reset; 124 125 /* Virtual and DMA addresses of the single shared page table. */ 126 volatile u32 *pt; 127 dma_addr_t pt_paddr; 128 129 /* Virtual and DMA addresses of the MMU's scratch page. When 130 * a read or write is invalid in the MMU, it will be 131 * redirected here. 132 */ 133 void *mmu_scratch; 134 dma_addr_t mmu_scratch_paddr; 135 /* virtual address bits from V3D to the MMU. */ 136 int va_width; 137 138 /* Number of V3D cores. */ 139 u32 cores; 140 141 /* Allocator managing the address space. All units are in 142 * number of pages. 143 */ 144 struct drm_mm mm; 145 spinlock_t mm_lock; 146 147 /* 148 * tmpfs instance used for shmem backed objects 149 */ 150 struct vfsmount *gemfs; 151 152 struct work_struct overflow_mem_work; 153 154 struct v3d_bin_job *bin_job; 155 struct v3d_render_job *render_job; 156 struct v3d_tfu_job *tfu_job; 157 struct v3d_csd_job *csd_job; 158 159 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 160 161 /* Spinlock used to synchronize the overflow memory 162 * management against bin job submission. 163 */ 164 spinlock_t job_lock; 165 166 /* Used to track the active perfmon if any. */ 167 struct v3d_perfmon *active_perfmon; 168 169 /* Protects bo_stats */ 170 struct mutex bo_lock; 171 172 /* Lock taken when resetting the GPU, to keep multiple 173 * processes from trying to park the scheduler threads and 174 * reset at once. 175 */ 176 struct mutex reset_lock; 177 178 /* Lock taken when creating and pushing the GPU scheduler 179 * jobs, to keep the sched-fence seqnos in order. 180 */ 181 struct mutex sched_lock; 182 183 /* Lock taken during a cache clean and when initiating an L2 184 * flush, to keep L2 flushes from interfering with the 185 * synchronous L2 cleans. 186 */ 187 struct mutex cache_clean_lock; 188 189 struct { 190 u32 num_allocated; 191 u32 pages_allocated; 192 } bo_stats; 193 194 /* To support a performance analysis tool in user space, we require 195 * a single, globally configured performance monitor (perfmon) for 196 * all jobs. 197 */ 198 struct v3d_perfmon *global_perfmon; 199 200 /* Global reset counter. The counter must be incremented when 201 * a GPU reset happens. It must be protected by @reset_lock. 202 */ 203 unsigned int reset_counter; 204 }; 205 206 static inline struct v3d_dev * 207 to_v3d_dev(struct drm_device *dev) 208 { 209 return container_of(dev, struct v3d_dev, drm); 210 } 211 212 static inline bool 213 v3d_has_csd(struct v3d_dev *v3d) 214 { 215 return v3d->ver >= V3D_GEN_41; 216 } 217 218 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 219 220 /* The per-fd struct, which tracks the MMU mappings. */ 221 struct v3d_file_priv { 222 struct v3d_dev *v3d; 223 224 struct { 225 struct idr idr; 226 struct mutex lock; 227 } perfmon; 228 229 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 230 231 /* Stores the GPU stats for a specific queue for this fd. */ 232 struct v3d_stats stats[V3D_MAX_QUEUES]; 233 234 /* Per-fd reset counter, must be incremented when a job submitted 235 * by this fd causes a GPU reset. It must be protected by 236 * &struct v3d_dev->reset_lock. 237 */ 238 unsigned int reset_counter; 239 }; 240 241 struct v3d_bo { 242 struct drm_gem_shmem_object base; 243 244 struct drm_mm_node node; 245 246 /* List entry for the BO's position in 247 * v3d_render_job->unref_list 248 */ 249 struct list_head unref_head; 250 251 void *vaddr; 252 }; 253 254 static inline struct v3d_bo * 255 to_v3d_bo(struct drm_gem_object *bo) 256 { 257 return (struct v3d_bo *)bo; 258 } 259 260 struct v3d_fence { 261 struct dma_fence base; 262 struct drm_device *dev; 263 /* v3d seqno for signaled() test */ 264 u64 seqno; 265 enum v3d_queue queue; 266 }; 267 268 static inline struct v3d_fence * 269 to_v3d_fence(struct dma_fence *fence) 270 { 271 return (struct v3d_fence *)fence; 272 } 273 274 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 275 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 276 277 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 278 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 279 280 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 281 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 282 283 #define V3D_SMS_IDLE 0x0 284 #define V3D_SMS_ISOLATING_FOR_RESET 0xa 285 #define V3D_SMS_RESETTING 0xb 286 #define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc 287 #define V3D_SMS_POWER_OFF_STATE 0xd 288 289 #define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset)) 290 #define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset)) 291 292 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 293 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 294 295 struct v3d_job { 296 struct drm_sched_job base; 297 298 struct kref refcount; 299 300 struct v3d_dev *v3d; 301 302 /* This is the array of BOs that were looked up at the start 303 * of submission. 304 */ 305 struct drm_gem_object **bo; 306 u32 bo_count; 307 308 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 309 struct dma_fence *irq_fence; 310 311 /* scheduler fence for when the job is considered complete and 312 * the BO reservations can be released. 313 */ 314 struct dma_fence *done_fence; 315 316 /* Pointer to a performance monitor object if the user requested it, 317 * NULL otherwise. 318 */ 319 struct v3d_perfmon *perfmon; 320 321 /* File descriptor of the process that submitted the job that could be used 322 * for collecting stats by process of GPU usage. 323 */ 324 struct drm_file *file; 325 326 /* Callback for the freeing of the job on refcount going to 0. */ 327 void (*free)(struct kref *ref); 328 }; 329 330 struct v3d_bin_job { 331 struct v3d_job base; 332 333 /* GPU virtual addresses of the start/end of the CL job. */ 334 u32 start, end; 335 336 u32 timedout_ctca, timedout_ctra; 337 338 /* Corresponding render job, for attaching our overflow memory. */ 339 struct v3d_render_job *render; 340 341 /* Submitted tile memory allocation start/size, tile state. */ 342 u32 qma, qms, qts; 343 }; 344 345 struct v3d_render_job { 346 struct v3d_job base; 347 348 /* GPU virtual addresses of the start/end of the CL job. */ 349 u32 start, end; 350 351 u32 timedout_ctca, timedout_ctra; 352 353 /* List of overflow BOs used in the job that need to be 354 * released once the job is complete. 355 */ 356 struct list_head unref_list; 357 }; 358 359 struct v3d_tfu_job { 360 struct v3d_job base; 361 362 struct drm_v3d_submit_tfu args; 363 }; 364 365 struct v3d_csd_job { 366 struct v3d_job base; 367 368 u32 timedout_batches; 369 370 struct drm_v3d_submit_csd args; 371 }; 372 373 enum v3d_cpu_job_type { 374 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 375 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 376 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 377 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 378 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 379 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 380 }; 381 382 struct v3d_timestamp_query { 383 /* Offset of this query in the timestamp BO for its value. */ 384 u32 offset; 385 386 /* Syncobj that indicates the timestamp availability */ 387 struct drm_syncobj *syncobj; 388 }; 389 390 struct v3d_performance_query { 391 /* Performance monitor IDs for this query */ 392 u32 *kperfmon_ids; 393 394 /* Syncobj that indicates the query availability */ 395 struct drm_syncobj *syncobj; 396 }; 397 398 struct v3d_indirect_csd_info { 399 /* Indirect CSD */ 400 struct v3d_csd_job *job; 401 402 /* Clean cache job associated to the Indirect CSD job */ 403 struct v3d_job *clean_job; 404 405 /* Offset within the BO where the workgroup counts are stored */ 406 u32 offset; 407 408 /* Workgroups size */ 409 u32 wg_size; 410 411 /* Indices of the uniforms with the workgroup dispatch counts 412 * in the uniform stream. 413 */ 414 u32 wg_uniform_offsets[3]; 415 416 /* Indirect BO */ 417 struct drm_gem_object *indirect; 418 419 /* Context of the Indirect CSD job */ 420 struct ww_acquire_ctx acquire_ctx; 421 }; 422 423 struct v3d_timestamp_query_info { 424 struct v3d_timestamp_query *queries; 425 426 u32 count; 427 }; 428 429 struct v3d_performance_query_info { 430 struct v3d_performance_query *queries; 431 432 /* Number of performance queries */ 433 u32 count; 434 435 /* Number of performance monitors related to that query pool */ 436 u32 nperfmons; 437 438 /* Number of performance counters related to that query pool */ 439 u32 ncounters; 440 }; 441 442 struct v3d_copy_query_results_info { 443 /* Define if should write to buffer using 64 or 32 bits */ 444 bool do_64bit; 445 446 /* Define if it can write to buffer even if the query is not available */ 447 bool do_partial; 448 449 /* Define if it should write availability bit to buffer */ 450 bool availability_bit; 451 452 /* Offset of the copy buffer in the BO */ 453 u32 offset; 454 455 /* Stride of the copy buffer in the BO */ 456 u32 stride; 457 }; 458 459 struct v3d_cpu_job { 460 struct v3d_job base; 461 462 enum v3d_cpu_job_type job_type; 463 464 struct v3d_indirect_csd_info indirect_csd; 465 466 struct v3d_timestamp_query_info timestamp_query; 467 468 struct v3d_copy_query_results_info copy; 469 470 struct v3d_performance_query_info performance_query; 471 }; 472 473 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 474 475 struct v3d_submit_outsync { 476 struct drm_syncobj *syncobj; 477 }; 478 479 struct v3d_submit_ext { 480 u32 flags; 481 u32 wait_stage; 482 483 u32 in_sync_count; 484 u64 in_syncs; 485 486 u32 out_sync_count; 487 struct v3d_submit_outsync *out_syncs; 488 }; 489 490 /** 491 * __wait_for - magic wait macro 492 * 493 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 494 * important that we check the condition again after having timed out, since the 495 * timeout could be due to preemption or similar and we've never had a chance to 496 * check the condition before the timeout. 497 */ 498 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 499 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 500 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 501 int ret__; \ 502 might_sleep(); \ 503 for (;;) { \ 504 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 505 OP; \ 506 /* Guarantee COND check prior to timeout */ \ 507 barrier(); \ 508 if (COND) { \ 509 ret__ = 0; \ 510 break; \ 511 } \ 512 if (expired__) { \ 513 ret__ = -ETIMEDOUT; \ 514 break; \ 515 } \ 516 usleep_range(wait__, wait__ * 2); \ 517 if (wait__ < (Wmax)) \ 518 wait__ <<= 1; \ 519 } \ 520 ret__; \ 521 }) 522 523 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 524 (Wmax)) 525 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 526 527 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 528 { 529 /* nsecs_to_jiffies64() does not guard against overflow */ 530 if ((NSEC_PER_SEC % HZ) != 0 && 531 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 532 return MAX_JIFFY_OFFSET; 533 534 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 535 } 536 537 /* v3d_bo.c */ 538 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 539 void v3d_free_object(struct drm_gem_object *gem_obj); 540 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 541 size_t size); 542 void v3d_get_bo_vaddr(struct v3d_bo *bo); 543 void v3d_put_bo_vaddr(struct v3d_bo *bo); 544 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 545 struct drm_file *file_priv); 546 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 547 struct drm_file *file_priv); 548 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 549 struct drm_file *file_priv); 550 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 551 struct drm_file *file_priv); 552 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 553 struct dma_buf_attachment *attach, 554 struct sg_table *sgt); 555 556 /* v3d_debugfs.c */ 557 void v3d_debugfs_init(struct drm_minor *minor); 558 559 /* v3d_drv.c */ 560 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 561 u64 *active_runtime, u64 *jobs_completed); 562 563 /* v3d_fence.c */ 564 extern const struct dma_fence_ops v3d_fence_ops; 565 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue); 566 567 /* v3d_gem.c */ 568 int v3d_gem_init(struct drm_device *dev); 569 void v3d_gem_destroy(struct drm_device *dev); 570 void v3d_reset_sms(struct v3d_dev *v3d); 571 void v3d_reset(struct v3d_dev *v3d); 572 void v3d_invalidate_caches(struct v3d_dev *v3d); 573 void v3d_clean_caches(struct v3d_dev *v3d); 574 575 /* v3d_gemfs.c */ 576 extern bool super_pages; 577 void v3d_gemfs_init(struct v3d_dev *v3d); 578 void v3d_gemfs_fini(struct v3d_dev *v3d); 579 580 /* v3d_submit.c */ 581 void v3d_job_cleanup(struct v3d_job *job); 582 void v3d_job_put(struct v3d_job *job); 583 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 584 struct drm_file *file_priv); 585 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 586 struct drm_file *file_priv); 587 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 588 struct drm_file *file_priv); 589 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 590 struct drm_file *file_priv); 591 592 /* v3d_irq.c */ 593 int v3d_irq_init(struct v3d_dev *v3d); 594 void v3d_irq_enable(struct v3d_dev *v3d); 595 void v3d_irq_disable(struct v3d_dev *v3d); 596 void v3d_irq_reset(struct v3d_dev *v3d); 597 598 /* v3d_mmu.c */ 599 int v3d_mmu_flush_all(struct v3d_dev *v3d); 600 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 601 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 602 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 603 604 /* v3d_sched.c */ 605 void v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info, 606 unsigned int count); 607 void v3d_performance_query_info_free(struct v3d_performance_query_info *query_info, 608 unsigned int count); 609 void v3d_job_update_stats(struct v3d_job *job, enum v3d_queue queue); 610 int v3d_sched_init(struct v3d_dev *v3d); 611 void v3d_sched_fini(struct v3d_dev *v3d); 612 613 /* v3d_perfmon.c */ 614 void v3d_perfmon_init(struct v3d_dev *v3d); 615 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 616 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 617 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 618 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 619 bool capture); 620 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 621 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 622 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 623 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 624 struct drm_file *file_priv); 625 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 626 struct drm_file *file_priv); 627 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 628 struct drm_file *file_priv); 629 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data, 630 struct drm_file *file_priv); 631 int v3d_perfmon_set_global_ioctl(struct drm_device *dev, void *data, 632 struct drm_file *file_priv); 633 634 /* v3d_sysfs.c */ 635 int v3d_sysfs_init(struct device *dev); 636 void v3d_sysfs_destroy(struct device *dev); 637