1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/pm_runtime.h> 7 #include <linux/spinlock_types.h> 8 #include <linux/workqueue.h> 9 10 #include <drm/drm_encoder.h> 11 #include <drm/drm_gem.h> 12 #include <drm/drm_gem_shmem_helper.h> 13 #include <drm/gpu_scheduler.h> 14 15 #include "v3d_performance_counters.h" 16 17 #include "uapi/drm/v3d_drm.h" 18 19 struct clk; 20 struct platform_device; 21 struct reset_control; 22 23 #define V3D_MMU_PAGE_SHIFT 12 24 #define V3D_PAGE_FACTOR (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) 25 26 #define V3D_MAX_QUEUES (V3D_CPU + 1) 27 28 static inline char *v3d_queue_to_string(enum v3d_queue queue) 29 { 30 switch (queue) { 31 case V3D_BIN: return "bin"; 32 case V3D_RENDER: return "render"; 33 case V3D_TFU: return "tfu"; 34 case V3D_CSD: return "csd"; 35 case V3D_CACHE_CLEAN: return "cache_clean"; 36 case V3D_CPU: return "cpu"; 37 } 38 return "UNKNOWN"; 39 } 40 41 struct v3d_stats { 42 struct kref refcount; 43 44 u64 start_ns; 45 u64 enabled_ns; 46 u64 jobs_completed; 47 48 /* 49 * This seqcount is used to protect the access to the GPU stats 50 * variables. It must be used as, while we are reading the stats, 51 * IRQs can happen and the stats can be updated. 52 * 53 * However, we use the raw seqcount helpers to interact with this lock 54 * to avoid false positives from lockdep, which is unable to detect that 55 * our readers are never from irq or softirq context, and that, for CPU 56 * job queues, even the write side never is. 57 */ 58 seqcount_t lock; 59 60 atomic_t reset_counter; 61 }; 62 63 struct v3d_queue_state { 64 struct drm_gpu_scheduler sched; 65 66 u64 fence_context; 67 u64 emit_seqno; 68 69 /* Stores the GPU stats for this queue in the global context. */ 70 struct v3d_stats *stats; 71 72 /* Currently active job for this queue */ 73 struct v3d_job *active_job; 74 spinlock_t queue_lock; 75 }; 76 77 /* Performance monitor object. The perform lifetime is controlled by userspace 78 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 79 * request, and when this is the case, HW perf counters will be activated just 80 * before the submit_cl is submitted to the GPU and disabled when the job is 81 * done. This way, only events related to a specific job will be counted. 82 */ 83 struct v3d_perfmon { 84 /* Tracks the number of users of the perfmon, when this counter reaches 85 * zero the perfmon is destroyed. 86 */ 87 refcount_t refcnt; 88 89 /* Protects perfmon stop, as it can be invoked from multiple places. */ 90 struct mutex lock; 91 92 /* Number of counters activated in this perfmon instance 93 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 94 */ 95 u8 ncounters; 96 97 /* Events counted by the HW perf counters. */ 98 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 99 100 /* Storage for counter values. Counters are incremented by the 101 * HW perf counter values every time the perfmon is attached 102 * to a GPU job. This way, perfmon users don't have to 103 * retrieve the results after each job if they want to track 104 * events covering several submissions. Note that counter 105 * values can't be reset, but you can fake a reset by 106 * destroying the perfmon and creating a new one. 107 */ 108 u64 values[] __counted_by(ncounters); 109 }; 110 111 enum v3d_gen { 112 V3D_GEN_33 = 33, 113 V3D_GEN_41 = 41, 114 V3D_GEN_42 = 42, 115 V3D_GEN_71 = 71, 116 }; 117 118 enum v3d_irq { 119 V3D_CORE_IRQ, 120 V3D_HUB_IRQ, 121 V3D_MAX_IRQS, 122 }; 123 124 struct v3d_dev { 125 struct drm_device drm; 126 127 /* Short representation (e.g. 33, 41) of the V3D tech version */ 128 enum v3d_gen ver; 129 130 /* Short representation (e.g. 5, 6) of the V3D tech revision */ 131 int rev; 132 133 bool single_irq_line; 134 135 int irq[V3D_MAX_IRQS]; 136 137 struct v3d_perfmon_info perfmon_info; 138 139 void __iomem *hub_regs; 140 void __iomem *core_regs[3]; 141 void __iomem *bridge_regs; 142 void __iomem *gca_regs; 143 void __iomem *sms_regs; 144 struct clk *clk; 145 struct reset_control *reset; 146 147 /* Virtual and DMA addresses of the single shared page table. */ 148 volatile u32 *pt; 149 dma_addr_t pt_paddr; 150 151 /* Virtual and DMA addresses of the MMU's scratch page. When 152 * a read or write is invalid in the MMU, it will be 153 * redirected here. 154 */ 155 void *mmu_scratch; 156 dma_addr_t mmu_scratch_paddr; 157 /* virtual address bits from V3D to the MMU. */ 158 int va_width; 159 160 /* Number of V3D cores. */ 161 u32 cores; 162 163 /* Allocator managing the address space. All units are in 164 * number of pages. 165 */ 166 struct drm_mm mm; 167 spinlock_t mm_lock; 168 169 struct work_struct overflow_mem_work; 170 171 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 172 173 /* Used to track the active perfmon if any. */ 174 struct v3d_perfmon *active_perfmon; 175 176 /* Protects bo_stats */ 177 struct mutex bo_lock; 178 179 /* Lock taken when resetting the GPU, to keep multiple 180 * processes from trying to park the scheduler threads and 181 * reset at once. 182 */ 183 struct mutex reset_lock; 184 185 /* Ordered workqueue shared by every queue's scheduler timeout work. 186 * V3D reset is global to all queues, so the timeout handlers must not 187 * run concurrently. 188 */ 189 struct workqueue_struct *reset_wq; 190 191 /* Lock taken when creating and pushing the GPU scheduler 192 * jobs, to keep the sched-fence seqnos in order. 193 */ 194 struct mutex sched_lock; 195 196 /* Lock taken during a cache clean and when initiating an L2 197 * flush, to keep L2 flushes from interfering with the 198 * synchronous L2 cleans. 199 */ 200 struct mutex cache_clean_lock; 201 202 struct { 203 u32 num_allocated; 204 u32 pages_allocated; 205 } bo_stats; 206 207 /* To support a performance analysis tool in user space, we require 208 * a single, globally configured performance monitor (perfmon) for 209 * all jobs. 210 */ 211 struct v3d_perfmon *global_perfmon; 212 213 /* Global reset counter incremented on each GPU reset. */ 214 atomic_t reset_counter; 215 }; 216 217 static inline struct v3d_dev * 218 to_v3d_dev(struct drm_device *dev) 219 { 220 return container_of(dev, struct v3d_dev, drm); 221 } 222 223 static inline bool 224 v3d_has_csd(struct v3d_dev *v3d) 225 { 226 return v3d->ver >= V3D_GEN_41; 227 } 228 229 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 230 231 /* The per-fd struct, which tracks the MMU mappings. */ 232 struct v3d_file_priv { 233 struct v3d_dev *v3d; 234 235 struct xarray perfmons; 236 237 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 238 239 /* Stores the GPU stats for a specific queue for this fd. */ 240 struct v3d_stats *stats[V3D_MAX_QUEUES]; 241 }; 242 243 struct v3d_bo { 244 struct drm_gem_shmem_object base; 245 246 struct drm_mm_node node; 247 248 /* List entry for the BO's position in 249 * v3d_render_job->unref_list 250 */ 251 struct list_head unref_head; 252 253 void *vaddr; 254 }; 255 256 static inline struct v3d_bo * 257 to_v3d_bo(struct drm_gem_object *bo) 258 { 259 return (struct v3d_bo *)bo; 260 } 261 262 struct v3d_fence { 263 struct dma_fence base; 264 struct drm_device *dev; 265 /* v3d seqno for signaled() test */ 266 u64 seqno; 267 enum v3d_queue queue; 268 }; 269 270 static inline struct v3d_fence * 271 to_v3d_fence(struct dma_fence *fence) 272 { 273 return (struct v3d_fence *)fence; 274 } 275 276 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 277 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 278 279 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 280 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 281 282 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 283 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 284 285 #define V3D_SMS_IDLE 0x0 286 #define V3D_SMS_ISOLATING_FOR_RESET 0xa 287 #define V3D_SMS_RESETTING 0xb 288 #define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc 289 #define V3D_SMS_POWER_OFF_STATE 0xd 290 291 #define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset)) 292 #define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset)) 293 294 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 295 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 296 297 struct v3d_job { 298 struct drm_sched_job base; 299 300 struct kref refcount; 301 302 struct v3d_dev *v3d; 303 304 /* This is the array of BOs that were looked up at the start 305 * of submission. 306 */ 307 struct drm_gem_object **bo; 308 u32 bo_count; 309 310 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 311 struct dma_fence *irq_fence; 312 313 /* scheduler fence for when the job is considered complete and 314 * the BO reservations can be released. 315 */ 316 struct dma_fence *done_fence; 317 318 /* Pointer to a performance monitor object if the user requested it, 319 * NULL otherwise. 320 */ 321 struct v3d_perfmon *perfmon; 322 323 /* File descriptor of the process that submitted the job that could be used 324 * to collect per-process information about the GPU. 325 */ 326 struct v3d_file_priv *file_priv; 327 328 /* Pointers to this job's per-fd and global queue stats. */ 329 struct v3d_stats *client_stats; 330 struct v3d_stats *global_stats; 331 332 /* Callback for the freeing of the job on refcount going to 0. */ 333 void (*free)(struct kref *ref); 334 335 bool has_pm_ref; 336 }; 337 338 struct v3d_bin_job { 339 struct v3d_job base; 340 341 /* GPU virtual addresses of the start/end of the CL job. */ 342 u32 start, end; 343 344 u32 timedout_ctca, timedout_ctra; 345 346 /* Corresponding render job, for attaching our overflow memory. */ 347 struct v3d_render_job *render; 348 349 /* Submitted tile memory allocation start/size, tile state. */ 350 u32 qma, qms, qts; 351 }; 352 353 struct v3d_render_job { 354 struct v3d_job base; 355 356 /* GPU virtual addresses of the start/end of the CL job. */ 357 u32 start, end; 358 359 u32 timedout_ctca, timedout_ctra; 360 361 /* List of overflow BOs used in the job that need to be 362 * released once the job is complete. 363 */ 364 struct list_head unref_list; 365 }; 366 367 struct v3d_tfu_job { 368 struct v3d_job base; 369 370 struct drm_v3d_submit_tfu args; 371 }; 372 373 struct v3d_csd_job { 374 struct v3d_job base; 375 376 u32 timedout_batches; 377 378 struct drm_v3d_submit_csd args; 379 }; 380 381 enum v3d_cpu_job_type { 382 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 383 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 384 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 385 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 386 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 387 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 388 }; 389 390 struct v3d_timestamp_query { 391 /* Offset of this query in the timestamp BO for its value. */ 392 u32 offset; 393 394 /* Syncobj that indicates the timestamp availability */ 395 struct drm_syncobj *syncobj; 396 }; 397 398 struct v3d_performance_query { 399 /* Performance monitor IDs for this query */ 400 u32 *kperfmon_ids; 401 402 /* Syncobj that indicates the query availability */ 403 struct drm_syncobj *syncobj; 404 }; 405 406 struct v3d_indirect_csd_info { 407 /* Indirect CSD */ 408 struct v3d_csd_job *job; 409 410 /* Clean cache job associated to the Indirect CSD job */ 411 struct v3d_job *clean_job; 412 413 /* Offset within the BO where the workgroup counts are stored */ 414 u32 offset; 415 416 /* Workgroups size */ 417 u32 wg_size; 418 419 /* Indices of the uniforms with the workgroup dispatch counts 420 * in the uniform stream. 421 */ 422 u32 wg_uniform_offsets[3]; 423 424 /* Indirect BO */ 425 struct drm_gem_object *indirect; 426 427 /* Context of the Indirect CSD job */ 428 struct ww_acquire_ctx acquire_ctx; 429 }; 430 431 struct v3d_timestamp_query_info { 432 struct v3d_timestamp_query *queries; 433 434 u32 count; 435 }; 436 437 struct v3d_performance_query_info { 438 struct v3d_performance_query *queries; 439 440 /* Number of performance queries */ 441 u32 count; 442 443 /* Number of performance monitors related to that query pool */ 444 u32 nperfmons; 445 446 /* Number of performance counters related to that query pool */ 447 u32 ncounters; 448 }; 449 450 struct v3d_copy_query_results_info { 451 /* Define if should write to buffer using 64 or 32 bits */ 452 bool do_64bit; 453 454 /* Define if it can write to buffer even if the query is not available */ 455 bool do_partial; 456 457 /* Define if it should write availability bit to buffer */ 458 bool availability_bit; 459 460 /* Offset of the copy buffer in the BO */ 461 u32 offset; 462 463 /* Stride of the copy buffer in the BO */ 464 u32 stride; 465 }; 466 467 struct v3d_cpu_job { 468 struct v3d_job base; 469 470 enum v3d_cpu_job_type job_type; 471 472 struct v3d_indirect_csd_info indirect_csd; 473 474 struct v3d_timestamp_query_info timestamp_query; 475 476 struct v3d_copy_query_results_info copy; 477 478 struct v3d_performance_query_info performance_query; 479 }; 480 481 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 482 483 struct v3d_submit_outsync { 484 struct drm_syncobj *syncobj; 485 }; 486 487 struct v3d_submit_ext { 488 u32 flags; 489 u32 wait_stage; 490 491 u32 in_sync_count; 492 u64 in_syncs; 493 494 u32 out_sync_count; 495 struct v3d_submit_outsync *out_syncs; 496 }; 497 498 /** 499 * __wait_for - magic wait macro 500 * 501 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 502 * important that we check the condition again after having timed out, since the 503 * timeout could be due to preemption or similar and we've never had a chance to 504 * check the condition before the timeout. 505 */ 506 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 507 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 508 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 509 int ret__; \ 510 might_sleep(); \ 511 for (;;) { \ 512 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 513 OP; \ 514 /* Guarantee COND check prior to timeout */ \ 515 barrier(); \ 516 if (COND) { \ 517 ret__ = 0; \ 518 break; \ 519 } \ 520 if (expired__) { \ 521 ret__ = -ETIMEDOUT; \ 522 break; \ 523 } \ 524 usleep_range(wait__, wait__ * 2); \ 525 if (wait__ < (Wmax)) \ 526 wait__ <<= 1; \ 527 } \ 528 ret__; \ 529 }) 530 531 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 532 (Wmax)) 533 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 534 535 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 536 { 537 /* nsecs_to_jiffies64() does not guard against overflow */ 538 if ((NSEC_PER_SEC % HZ) != 0 && 539 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 540 return MAX_JIFFY_OFFSET; 541 542 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 543 } 544 545 /* v3d_bo.c */ 546 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 547 void v3d_free_object(struct drm_gem_object *gem_obj); 548 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 549 size_t size); 550 void v3d_get_bo_vaddr(struct v3d_bo *bo); 551 void v3d_put_bo_vaddr(struct v3d_bo *bo); 552 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 553 struct drm_file *file_priv); 554 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 555 struct drm_file *file_priv); 556 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 557 struct drm_file *file_priv); 558 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 559 struct drm_file *file_priv); 560 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 561 struct dma_buf_attachment *attach, 562 struct sg_table *sgt); 563 564 /* v3d_debugfs.c */ 565 void v3d_debugfs_init(struct drm_minor *minor); 566 567 /* v3d_drv.c */ 568 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 569 u64 *active_runtime, u64 *jobs_completed); 570 571 /* v3d_fence.c */ 572 extern const struct dma_fence_ops v3d_fence_ops; 573 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue q); 574 575 /* v3d_gem.c */ 576 extern bool super_pages; 577 void v3d_init_hw_state(struct v3d_dev *v3d); 578 int v3d_gem_init(struct drm_device *dev); 579 void v3d_gem_destroy(struct drm_device *dev); 580 void v3d_idle_axi(struct v3d_dev *v3d, int core); 581 void v3d_idle_gca(struct v3d_dev *v3d); 582 void v3d_reset_sms(struct v3d_dev *v3d); 583 void v3d_reset(struct v3d_dev *v3d); 584 void v3d_invalidate_caches(struct v3d_dev *v3d); 585 void v3d_clean_caches(struct v3d_dev *v3d); 586 587 /* v3d_submit.c */ 588 void v3d_job_cleanup(struct v3d_job *job); 589 void v3d_job_put(struct v3d_job *job); 590 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 591 struct drm_file *file_priv); 592 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 593 struct drm_file *file_priv); 594 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 595 struct drm_file *file_priv); 596 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 597 struct drm_file *file_priv); 598 599 /* v3d_irq.c */ 600 int v3d_irq_init(struct v3d_dev *v3d); 601 void v3d_irq_enable(struct v3d_dev *v3d); 602 void v3d_irq_disable(struct v3d_dev *v3d); 603 void v3d_irq_reset(struct v3d_dev *v3d); 604 605 /* v3d_mmu.c */ 606 int v3d_mmu_flush_all(struct v3d_dev *v3d); 607 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 608 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 609 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 610 611 /* v3d_power.c */ 612 int v3d_power_suspend(struct device *dev); 613 int v3d_power_resume(struct device *dev); 614 615 static __always_inline int v3d_pm_runtime_get(struct v3d_dev *v3d) 616 { 617 return pm_runtime_resume_and_get(v3d->drm.dev); 618 } 619 620 static __always_inline int v3d_pm_runtime_put(struct v3d_dev *v3d) 621 { 622 return pm_runtime_put_autosuspend(v3d->drm.dev); 623 } 624 625 /* v3d_sched.c */ 626 void v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info, 627 unsigned int count); 628 void v3d_performance_query_info_free(struct v3d_performance_query_info *query_info, 629 unsigned int count); 630 struct v3d_stats *v3d_stats_alloc(void); 631 void v3d_stats_release(struct kref *refcount); 632 void v3d_job_update_stats(struct v3d_job *job); 633 int v3d_sched_init(struct v3d_dev *v3d); 634 void v3d_sched_fini(struct v3d_dev *v3d); 635 636 static inline struct v3d_stats *v3d_stats_get(struct v3d_stats *stats) 637 { 638 kref_get(&stats->refcount); 639 return stats; 640 } 641 642 static inline void v3d_stats_put(struct v3d_stats *stats) 643 { 644 kref_put(&stats->refcount, v3d_stats_release); 645 } 646 647 /* v3d_perfmon.c */ 648 void v3d_perfmon_init(struct v3d_dev *v3d); 649 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 650 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 651 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 652 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 653 bool capture); 654 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 655 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 656 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 657 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 658 struct drm_file *file_priv); 659 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 660 struct drm_file *file_priv); 661 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 662 struct drm_file *file_priv); 663 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data, 664 struct drm_file *file_priv); 665 int v3d_perfmon_set_global_ioctl(struct drm_device *dev, void *data, 666 struct drm_file *file_priv); 667 668 /* v3d_sysfs.c */ 669 int v3d_sysfs_init(struct device *dev); 670 void v3d_sysfs_destroy(struct device *dev); 671