1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/pm_runtime.h> 7 #include <linux/spinlock_types.h> 8 #include <linux/workqueue.h> 9 10 #include <drm/drm_encoder.h> 11 #include <drm/drm_gem.h> 12 #include <drm/drm_gem_shmem_helper.h> 13 #include <drm/gpu_scheduler.h> 14 15 #include "v3d_performance_counters.h" 16 17 #include "uapi/drm/v3d_drm.h" 18 19 struct clk; 20 struct platform_device; 21 struct reset_control; 22 23 #define V3D_MMU_PAGE_SHIFT 12 24 #define V3D_PAGE_FACTOR (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) 25 26 #define V3D_MAX_QUEUES (V3D_CPU + 1) 27 28 static inline char *v3d_queue_to_string(enum v3d_queue queue) 29 { 30 switch (queue) { 31 case V3D_BIN: return "bin"; 32 case V3D_RENDER: return "render"; 33 case V3D_TFU: return "tfu"; 34 case V3D_CSD: return "csd"; 35 case V3D_CACHE_CLEAN: return "cache_clean"; 36 case V3D_CPU: return "cpu"; 37 } 38 return "UNKNOWN"; 39 } 40 41 struct v3d_stats { 42 struct kref refcount; 43 44 u64 start_ns; 45 u64 enabled_ns; 46 u64 jobs_completed; 47 48 /* 49 * This seqcount is used to protect the access to the GPU stats 50 * variables. It must be used as, while we are reading the stats, 51 * IRQs can happen and the stats can be updated. 52 * 53 * However, we use the raw seqcount helpers to interact with this lock 54 * to avoid false positives from lockdep, which is unable to detect that 55 * our readers are never from irq or softirq context, and that, for CPU 56 * job queues, even the write side never is. 57 */ 58 seqcount_t lock; 59 60 atomic_t reset_counter; 61 }; 62 63 struct v3d_queue_state { 64 struct drm_gpu_scheduler sched; 65 66 u64 fence_context; 67 u64 emit_seqno; 68 69 /* Stores the GPU stats for this queue in the global context. */ 70 struct v3d_stats *stats; 71 72 /* Currently active job for this queue */ 73 struct v3d_job *active_job; 74 spinlock_t queue_lock; 75 }; 76 77 /* Performance monitor object. The perform lifetime is controlled by userspace 78 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 79 * request, and when this is the case, HW perf counters will be activated just 80 * before the submit_cl is submitted to the GPU and disabled when the job is 81 * done. This way, only events related to a specific job will be counted. 82 */ 83 struct v3d_perfmon { 84 /* Tracks the number of users of the perfmon, when this counter reaches 85 * zero the perfmon is destroyed. 86 */ 87 refcount_t refcnt; 88 89 /* Protects perfmon stop, as it can be invoked from multiple places. */ 90 struct mutex lock; 91 92 /* Number of counters activated in this perfmon instance 93 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 94 */ 95 u8 ncounters; 96 97 /* Events counted by the HW perf counters. */ 98 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 99 100 /* Storage for counter values. Counters are incremented by the 101 * HW perf counter values every time the perfmon is attached 102 * to a GPU job. This way, perfmon users don't have to 103 * retrieve the results after each job if they want to track 104 * events covering several submissions. Note that counter 105 * values can't be reset, but you can fake a reset by 106 * destroying the perfmon and creating a new one. 107 */ 108 u64 values[] __counted_by(ncounters); 109 }; 110 111 enum v3d_gen { 112 V3D_GEN_33 = 33, 113 V3D_GEN_41 = 41, 114 V3D_GEN_42 = 42, 115 V3D_GEN_71 = 71, 116 }; 117 118 enum v3d_irq { 119 V3D_CORE_IRQ, 120 V3D_HUB_IRQ, 121 V3D_MAX_IRQS, 122 }; 123 124 struct v3d_dev { 125 struct drm_device drm; 126 127 /* Short representation (e.g. 33, 41) of the V3D tech version */ 128 enum v3d_gen ver; 129 130 /* Short representation (e.g. 5, 6) of the V3D tech revision */ 131 int rev; 132 133 bool single_irq_line; 134 135 int irq[V3D_MAX_IRQS]; 136 137 struct v3d_perfmon_info perfmon_info; 138 139 void __iomem *hub_regs; 140 void __iomem *core_regs[3]; 141 void __iomem *bridge_regs; 142 void __iomem *gca_regs; 143 void __iomem *sms_regs; 144 struct clk *clk; 145 struct reset_control *reset; 146 147 /* Virtual and DMA addresses of the single shared page table. */ 148 volatile u32 *pt; 149 dma_addr_t pt_paddr; 150 151 /* Virtual and DMA addresses of the MMU's scratch page. When 152 * a read or write is invalid in the MMU, it will be 153 * redirected here. 154 */ 155 void *mmu_scratch; 156 dma_addr_t mmu_scratch_paddr; 157 /* virtual address bits from V3D to the MMU. */ 158 int va_width; 159 160 /* Number of V3D cores. */ 161 u32 cores; 162 163 /* Allocator managing the address space. All units are in 164 * number of pages. 165 */ 166 struct drm_mm mm; 167 spinlock_t mm_lock; 168 169 struct work_struct overflow_mem_work; 170 171 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 172 173 /* Used to track the active perfmon if any. */ 174 struct v3d_perfmon *active_perfmon; 175 176 /* Protects bo_stats */ 177 struct mutex bo_lock; 178 179 /* Lock taken when resetting the GPU, to keep multiple 180 * processes from trying to park the scheduler threads and 181 * reset at once. 182 */ 183 struct mutex reset_lock; 184 185 /* Lock taken when creating and pushing the GPU scheduler 186 * jobs, to keep the sched-fence seqnos in order. 187 */ 188 struct mutex sched_lock; 189 190 /* Lock taken during a cache clean and when initiating an L2 191 * flush, to keep L2 flushes from interfering with the 192 * synchronous L2 cleans. 193 */ 194 struct mutex cache_clean_lock; 195 196 struct { 197 u32 num_allocated; 198 u32 pages_allocated; 199 } bo_stats; 200 201 /* To support a performance analysis tool in user space, we require 202 * a single, globally configured performance monitor (perfmon) for 203 * all jobs. 204 */ 205 struct v3d_perfmon *global_perfmon; 206 207 /* Global reset counter incremented on each GPU reset. */ 208 atomic_t reset_counter; 209 }; 210 211 static inline struct v3d_dev * 212 to_v3d_dev(struct drm_device *dev) 213 { 214 return container_of(dev, struct v3d_dev, drm); 215 } 216 217 static inline bool 218 v3d_has_csd(struct v3d_dev *v3d) 219 { 220 return v3d->ver >= V3D_GEN_41; 221 } 222 223 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 224 225 /* The per-fd struct, which tracks the MMU mappings. */ 226 struct v3d_file_priv { 227 struct v3d_dev *v3d; 228 229 struct xarray perfmons; 230 231 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 232 233 /* Stores the GPU stats for a specific queue for this fd. */ 234 struct v3d_stats *stats[V3D_MAX_QUEUES]; 235 }; 236 237 struct v3d_bo { 238 struct drm_gem_shmem_object base; 239 240 struct drm_mm_node node; 241 242 /* List entry for the BO's position in 243 * v3d_render_job->unref_list 244 */ 245 struct list_head unref_head; 246 247 void *vaddr; 248 }; 249 250 static inline struct v3d_bo * 251 to_v3d_bo(struct drm_gem_object *bo) 252 { 253 return (struct v3d_bo *)bo; 254 } 255 256 struct v3d_fence { 257 struct dma_fence base; 258 struct drm_device *dev; 259 /* v3d seqno for signaled() test */ 260 u64 seqno; 261 enum v3d_queue queue; 262 }; 263 264 static inline struct v3d_fence * 265 to_v3d_fence(struct dma_fence *fence) 266 { 267 return (struct v3d_fence *)fence; 268 } 269 270 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 271 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 272 273 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 274 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 275 276 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 277 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 278 279 #define V3D_SMS_IDLE 0x0 280 #define V3D_SMS_ISOLATING_FOR_RESET 0xa 281 #define V3D_SMS_RESETTING 0xb 282 #define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc 283 #define V3D_SMS_POWER_OFF_STATE 0xd 284 285 #define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset)) 286 #define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset)) 287 288 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 289 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 290 291 struct v3d_job { 292 struct drm_sched_job base; 293 294 struct kref refcount; 295 296 struct v3d_dev *v3d; 297 298 /* This is the array of BOs that were looked up at the start 299 * of submission. 300 */ 301 struct drm_gem_object **bo; 302 u32 bo_count; 303 304 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 305 struct dma_fence *irq_fence; 306 307 /* scheduler fence for when the job is considered complete and 308 * the BO reservations can be released. 309 */ 310 struct dma_fence *done_fence; 311 312 /* Pointer to a performance monitor object if the user requested it, 313 * NULL otherwise. 314 */ 315 struct v3d_perfmon *perfmon; 316 317 /* File descriptor of the process that submitted the job that could be used 318 * to collect per-process information about the GPU. 319 */ 320 struct v3d_file_priv *file_priv; 321 322 /* Pointers to this job's per-fd and global queue stats. */ 323 struct v3d_stats *client_stats; 324 struct v3d_stats *global_stats; 325 326 /* Callback for the freeing of the job on refcount going to 0. */ 327 void (*free)(struct kref *ref); 328 329 bool has_pm_ref; 330 }; 331 332 struct v3d_bin_job { 333 struct v3d_job base; 334 335 /* GPU virtual addresses of the start/end of the CL job. */ 336 u32 start, end; 337 338 u32 timedout_ctca, timedout_ctra; 339 340 /* Corresponding render job, for attaching our overflow memory. */ 341 struct v3d_render_job *render; 342 343 /* Submitted tile memory allocation start/size, tile state. */ 344 u32 qma, qms, qts; 345 }; 346 347 struct v3d_render_job { 348 struct v3d_job base; 349 350 /* GPU virtual addresses of the start/end of the CL job. */ 351 u32 start, end; 352 353 u32 timedout_ctca, timedout_ctra; 354 355 /* List of overflow BOs used in the job that need to be 356 * released once the job is complete. 357 */ 358 struct list_head unref_list; 359 }; 360 361 struct v3d_tfu_job { 362 struct v3d_job base; 363 364 struct drm_v3d_submit_tfu args; 365 }; 366 367 struct v3d_csd_job { 368 struct v3d_job base; 369 370 u32 timedout_batches; 371 372 struct drm_v3d_submit_csd args; 373 }; 374 375 enum v3d_cpu_job_type { 376 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 377 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 378 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 379 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 380 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 381 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 382 }; 383 384 struct v3d_timestamp_query { 385 /* Offset of this query in the timestamp BO for its value. */ 386 u32 offset; 387 388 /* Syncobj that indicates the timestamp availability */ 389 struct drm_syncobj *syncobj; 390 }; 391 392 struct v3d_performance_query { 393 /* Performance monitor IDs for this query */ 394 u32 *kperfmon_ids; 395 396 /* Syncobj that indicates the query availability */ 397 struct drm_syncobj *syncobj; 398 }; 399 400 struct v3d_indirect_csd_info { 401 /* Indirect CSD */ 402 struct v3d_csd_job *job; 403 404 /* Clean cache job associated to the Indirect CSD job */ 405 struct v3d_job *clean_job; 406 407 /* Offset within the BO where the workgroup counts are stored */ 408 u32 offset; 409 410 /* Workgroups size */ 411 u32 wg_size; 412 413 /* Indices of the uniforms with the workgroup dispatch counts 414 * in the uniform stream. 415 */ 416 u32 wg_uniform_offsets[3]; 417 418 /* Indirect BO */ 419 struct drm_gem_object *indirect; 420 421 /* Context of the Indirect CSD job */ 422 struct ww_acquire_ctx acquire_ctx; 423 }; 424 425 struct v3d_timestamp_query_info { 426 struct v3d_timestamp_query *queries; 427 428 u32 count; 429 }; 430 431 struct v3d_performance_query_info { 432 struct v3d_performance_query *queries; 433 434 /* Number of performance queries */ 435 u32 count; 436 437 /* Number of performance monitors related to that query pool */ 438 u32 nperfmons; 439 440 /* Number of performance counters related to that query pool */ 441 u32 ncounters; 442 }; 443 444 struct v3d_copy_query_results_info { 445 /* Define if should write to buffer using 64 or 32 bits */ 446 bool do_64bit; 447 448 /* Define if it can write to buffer even if the query is not available */ 449 bool do_partial; 450 451 /* Define if it should write availability bit to buffer */ 452 bool availability_bit; 453 454 /* Offset of the copy buffer in the BO */ 455 u32 offset; 456 457 /* Stride of the copy buffer in the BO */ 458 u32 stride; 459 }; 460 461 struct v3d_cpu_job { 462 struct v3d_job base; 463 464 enum v3d_cpu_job_type job_type; 465 466 struct v3d_indirect_csd_info indirect_csd; 467 468 struct v3d_timestamp_query_info timestamp_query; 469 470 struct v3d_copy_query_results_info copy; 471 472 struct v3d_performance_query_info performance_query; 473 }; 474 475 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 476 477 struct v3d_submit_outsync { 478 struct drm_syncobj *syncobj; 479 }; 480 481 struct v3d_submit_ext { 482 u32 flags; 483 u32 wait_stage; 484 485 u32 in_sync_count; 486 u64 in_syncs; 487 488 u32 out_sync_count; 489 struct v3d_submit_outsync *out_syncs; 490 }; 491 492 /** 493 * __wait_for - magic wait macro 494 * 495 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 496 * important that we check the condition again after having timed out, since the 497 * timeout could be due to preemption or similar and we've never had a chance to 498 * check the condition before the timeout. 499 */ 500 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 501 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 502 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 503 int ret__; \ 504 might_sleep(); \ 505 for (;;) { \ 506 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 507 OP; \ 508 /* Guarantee COND check prior to timeout */ \ 509 barrier(); \ 510 if (COND) { \ 511 ret__ = 0; \ 512 break; \ 513 } \ 514 if (expired__) { \ 515 ret__ = -ETIMEDOUT; \ 516 break; \ 517 } \ 518 usleep_range(wait__, wait__ * 2); \ 519 if (wait__ < (Wmax)) \ 520 wait__ <<= 1; \ 521 } \ 522 ret__; \ 523 }) 524 525 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 526 (Wmax)) 527 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 528 529 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 530 { 531 /* nsecs_to_jiffies64() does not guard against overflow */ 532 if ((NSEC_PER_SEC % HZ) != 0 && 533 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 534 return MAX_JIFFY_OFFSET; 535 536 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 537 } 538 539 /* v3d_bo.c */ 540 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 541 void v3d_free_object(struct drm_gem_object *gem_obj); 542 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 543 size_t size); 544 void v3d_get_bo_vaddr(struct v3d_bo *bo); 545 void v3d_put_bo_vaddr(struct v3d_bo *bo); 546 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 547 struct drm_file *file_priv); 548 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 549 struct drm_file *file_priv); 550 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 551 struct drm_file *file_priv); 552 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 553 struct drm_file *file_priv); 554 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 555 struct dma_buf_attachment *attach, 556 struct sg_table *sgt); 557 558 /* v3d_debugfs.c */ 559 void v3d_debugfs_init(struct drm_minor *minor); 560 561 /* v3d_drv.c */ 562 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 563 u64 *active_runtime, u64 *jobs_completed); 564 565 /* v3d_fence.c */ 566 extern const struct dma_fence_ops v3d_fence_ops; 567 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue q); 568 569 /* v3d_gem.c */ 570 extern bool super_pages; 571 void v3d_init_hw_state(struct v3d_dev *v3d); 572 int v3d_gem_init(struct drm_device *dev); 573 void v3d_gem_destroy(struct drm_device *dev); 574 void v3d_reset_sms(struct v3d_dev *v3d); 575 void v3d_reset(struct v3d_dev *v3d); 576 void v3d_invalidate_caches(struct v3d_dev *v3d); 577 void v3d_clean_caches(struct v3d_dev *v3d); 578 579 /* v3d_submit.c */ 580 void v3d_job_cleanup(struct v3d_job *job); 581 void v3d_job_put(struct v3d_job *job); 582 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 583 struct drm_file *file_priv); 584 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 585 struct drm_file *file_priv); 586 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 587 struct drm_file *file_priv); 588 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 589 struct drm_file *file_priv); 590 591 /* v3d_irq.c */ 592 int v3d_irq_init(struct v3d_dev *v3d); 593 void v3d_irq_enable(struct v3d_dev *v3d); 594 void v3d_irq_disable(struct v3d_dev *v3d); 595 void v3d_irq_reset(struct v3d_dev *v3d); 596 597 /* v3d_mmu.c */ 598 int v3d_mmu_flush_all(struct v3d_dev *v3d); 599 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 600 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 601 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 602 603 /* v3d_power.c */ 604 int v3d_power_suspend(struct device *dev); 605 int v3d_power_resume(struct device *dev); 606 607 static __always_inline int v3d_pm_runtime_get(struct v3d_dev *v3d) 608 { 609 return pm_runtime_resume_and_get(v3d->drm.dev); 610 } 611 612 static __always_inline int v3d_pm_runtime_put(struct v3d_dev *v3d) 613 { 614 return pm_runtime_put_autosuspend(v3d->drm.dev); 615 } 616 617 /* v3d_sched.c */ 618 void v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info, 619 unsigned int count); 620 void v3d_performance_query_info_free(struct v3d_performance_query_info *query_info, 621 unsigned int count); 622 struct v3d_stats *v3d_stats_alloc(void); 623 void v3d_stats_release(struct kref *refcount); 624 void v3d_job_update_stats(struct v3d_job *job); 625 int v3d_sched_init(struct v3d_dev *v3d); 626 void v3d_sched_fini(struct v3d_dev *v3d); 627 628 static inline struct v3d_stats *v3d_stats_get(struct v3d_stats *stats) 629 { 630 kref_get(&stats->refcount); 631 return stats; 632 } 633 634 static inline void v3d_stats_put(struct v3d_stats *stats) 635 { 636 kref_put(&stats->refcount, v3d_stats_release); 637 } 638 639 /* v3d_perfmon.c */ 640 void v3d_perfmon_init(struct v3d_dev *v3d); 641 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 642 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 643 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 644 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 645 bool capture); 646 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 647 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 648 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 649 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 650 struct drm_file *file_priv); 651 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 652 struct drm_file *file_priv); 653 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 654 struct drm_file *file_priv); 655 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data, 656 struct drm_file *file_priv); 657 int v3d_perfmon_set_global_ioctl(struct drm_device *dev, void *data, 658 struct drm_file *file_priv); 659 660 /* v3d_sysfs.c */ 661 int v3d_sysfs_init(struct device *dev); 662 void v3d_sysfs_destroy(struct device *dev); 663