1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/spinlock_types.h> 7 #include <linux/workqueue.h> 8 9 #include <drm/drm_encoder.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_gem_shmem_helper.h> 12 #include <drm/gpu_scheduler.h> 13 14 #include "uapi/drm/v3d_drm.h" 15 16 struct clk; 17 struct platform_device; 18 struct reset_control; 19 20 #define GMP_GRANULARITY (128 * 1024) 21 22 #define V3D_MAX_QUEUES (V3D_CPU + 1) 23 24 static inline char *v3d_queue_to_string(enum v3d_queue queue) 25 { 26 switch (queue) { 27 case V3D_BIN: return "bin"; 28 case V3D_RENDER: return "render"; 29 case V3D_TFU: return "tfu"; 30 case V3D_CSD: return "csd"; 31 case V3D_CACHE_CLEAN: return "cache_clean"; 32 case V3D_CPU: return "cpu"; 33 } 34 return "UNKNOWN"; 35 } 36 37 struct v3d_queue_state { 38 struct drm_gpu_scheduler sched; 39 40 u64 fence_context; 41 u64 emit_seqno; 42 43 u64 start_ns; 44 u64 enabled_ns; 45 u64 jobs_sent; 46 }; 47 48 /* Performance monitor object. The perform lifetime is controlled by userspace 49 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 50 * request, and when this is the case, HW perf counters will be activated just 51 * before the submit_cl is submitted to the GPU and disabled when the job is 52 * done. This way, only events related to a specific job will be counted. 53 */ 54 struct v3d_perfmon { 55 /* Tracks the number of users of the perfmon, when this counter reaches 56 * zero the perfmon is destroyed. 57 */ 58 refcount_t refcnt; 59 60 /* Protects perfmon stop, as it can be invoked from multiple places. */ 61 struct mutex lock; 62 63 /* Number of counters activated in this perfmon instance 64 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 65 */ 66 u8 ncounters; 67 68 /* Events counted by the HW perf counters. */ 69 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 70 71 /* Storage for counter values. Counters are incremented by the 72 * HW perf counter values every time the perfmon is attached 73 * to a GPU job. This way, perfmon users don't have to 74 * retrieve the results after each job if they want to track 75 * events covering several submissions. Note that counter 76 * values can't be reset, but you can fake a reset by 77 * destroying the perfmon and creating a new one. 78 */ 79 u64 values[] __counted_by(ncounters); 80 }; 81 82 struct v3d_dev { 83 struct drm_device drm; 84 85 /* Short representation (e.g. 33, 41) of the V3D tech version 86 * and revision. 87 */ 88 int ver; 89 bool single_irq_line; 90 91 void __iomem *hub_regs; 92 void __iomem *core_regs[3]; 93 void __iomem *bridge_regs; 94 void __iomem *gca_regs; 95 struct clk *clk; 96 struct reset_control *reset; 97 98 /* Virtual and DMA addresses of the single shared page table. */ 99 volatile u32 *pt; 100 dma_addr_t pt_paddr; 101 102 /* Virtual and DMA addresses of the MMU's scratch page. When 103 * a read or write is invalid in the MMU, it will be 104 * redirected here. 105 */ 106 void *mmu_scratch; 107 dma_addr_t mmu_scratch_paddr; 108 /* virtual address bits from V3D to the MMU. */ 109 int va_width; 110 111 /* Number of V3D cores. */ 112 u32 cores; 113 114 /* Allocator managing the address space. All units are in 115 * number of pages. 116 */ 117 struct drm_mm mm; 118 spinlock_t mm_lock; 119 120 struct work_struct overflow_mem_work; 121 122 struct v3d_bin_job *bin_job; 123 struct v3d_render_job *render_job; 124 struct v3d_tfu_job *tfu_job; 125 struct v3d_csd_job *csd_job; 126 struct v3d_cpu_job *cpu_job; 127 128 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 129 130 /* Spinlock used to synchronize the overflow memory 131 * management against bin job submission. 132 */ 133 spinlock_t job_lock; 134 135 /* Used to track the active perfmon if any. */ 136 struct v3d_perfmon *active_perfmon; 137 138 /* Protects bo_stats */ 139 struct mutex bo_lock; 140 141 /* Lock taken when resetting the GPU, to keep multiple 142 * processes from trying to park the scheduler threads and 143 * reset at once. 144 */ 145 struct mutex reset_lock; 146 147 /* Lock taken when creating and pushing the GPU scheduler 148 * jobs, to keep the sched-fence seqnos in order. 149 */ 150 struct mutex sched_lock; 151 152 /* Lock taken during a cache clean and when initiating an L2 153 * flush, to keep L2 flushes from interfering with the 154 * synchronous L2 cleans. 155 */ 156 struct mutex cache_clean_lock; 157 158 struct { 159 u32 num_allocated; 160 u32 pages_allocated; 161 } bo_stats; 162 }; 163 164 static inline struct v3d_dev * 165 to_v3d_dev(struct drm_device *dev) 166 { 167 return container_of(dev, struct v3d_dev, drm); 168 } 169 170 static inline bool 171 v3d_has_csd(struct v3d_dev *v3d) 172 { 173 return v3d->ver >= 41; 174 } 175 176 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 177 178 /* The per-fd struct, which tracks the MMU mappings. */ 179 struct v3d_file_priv { 180 struct v3d_dev *v3d; 181 182 struct { 183 struct idr idr; 184 struct mutex lock; 185 } perfmon; 186 187 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 188 189 u64 start_ns[V3D_MAX_QUEUES]; 190 191 u64 enabled_ns[V3D_MAX_QUEUES]; 192 193 u64 jobs_sent[V3D_MAX_QUEUES]; 194 }; 195 196 struct v3d_bo { 197 struct drm_gem_shmem_object base; 198 199 struct drm_mm_node node; 200 201 /* List entry for the BO's position in 202 * v3d_render_job->unref_list 203 */ 204 struct list_head unref_head; 205 206 void *vaddr; 207 }; 208 209 static inline struct v3d_bo * 210 to_v3d_bo(struct drm_gem_object *bo) 211 { 212 return (struct v3d_bo *)bo; 213 } 214 215 struct v3d_fence { 216 struct dma_fence base; 217 struct drm_device *dev; 218 /* v3d seqno for signaled() test */ 219 u64 seqno; 220 enum v3d_queue queue; 221 }; 222 223 static inline struct v3d_fence * 224 to_v3d_fence(struct dma_fence *fence) 225 { 226 return (struct v3d_fence *)fence; 227 } 228 229 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 230 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 231 232 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 233 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 234 235 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 236 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 237 238 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 239 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 240 241 struct v3d_job { 242 struct drm_sched_job base; 243 244 struct kref refcount; 245 246 struct v3d_dev *v3d; 247 248 /* This is the array of BOs that were looked up at the start 249 * of submission. 250 */ 251 struct drm_gem_object **bo; 252 u32 bo_count; 253 254 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 255 struct dma_fence *irq_fence; 256 257 /* scheduler fence for when the job is considered complete and 258 * the BO reservations can be released. 259 */ 260 struct dma_fence *done_fence; 261 262 /* Pointer to a performance monitor object if the user requested it, 263 * NULL otherwise. 264 */ 265 struct v3d_perfmon *perfmon; 266 267 /* File descriptor of the process that submitted the job that could be used 268 * for collecting stats by process of GPU usage. 269 */ 270 struct drm_file *file; 271 272 /* Callback for the freeing of the job on refcount going to 0. */ 273 void (*free)(struct kref *ref); 274 }; 275 276 struct v3d_bin_job { 277 struct v3d_job base; 278 279 /* GPU virtual addresses of the start/end of the CL job. */ 280 u32 start, end; 281 282 u32 timedout_ctca, timedout_ctra; 283 284 /* Corresponding render job, for attaching our overflow memory. */ 285 struct v3d_render_job *render; 286 287 /* Submitted tile memory allocation start/size, tile state. */ 288 u32 qma, qms, qts; 289 }; 290 291 struct v3d_render_job { 292 struct v3d_job base; 293 294 /* GPU virtual addresses of the start/end of the CL job. */ 295 u32 start, end; 296 297 u32 timedout_ctca, timedout_ctra; 298 299 /* List of overflow BOs used in the job that need to be 300 * released once the job is complete. 301 */ 302 struct list_head unref_list; 303 }; 304 305 struct v3d_tfu_job { 306 struct v3d_job base; 307 308 struct drm_v3d_submit_tfu args; 309 }; 310 311 struct v3d_csd_job { 312 struct v3d_job base; 313 314 u32 timedout_batches; 315 316 struct drm_v3d_submit_csd args; 317 }; 318 319 enum v3d_cpu_job_type { 320 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 321 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 322 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 323 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 324 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 325 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 326 }; 327 328 struct v3d_timestamp_query { 329 /* Offset of this query in the timestamp BO for its value. */ 330 u32 offset; 331 332 /* Syncobj that indicates the timestamp availability */ 333 struct drm_syncobj *syncobj; 334 }; 335 336 /* Number of perfmons required to handle all supported performance counters */ 337 #define V3D_MAX_PERFMONS DIV_ROUND_UP(V3D_PERFCNT_NUM, \ 338 DRM_V3D_MAX_PERF_COUNTERS) 339 340 struct v3d_performance_query { 341 /* Performance monitor IDs for this query */ 342 u32 kperfmon_ids[V3D_MAX_PERFMONS]; 343 344 /* Syncobj that indicates the query availability */ 345 struct drm_syncobj *syncobj; 346 }; 347 348 struct v3d_indirect_csd_info { 349 /* Indirect CSD */ 350 struct v3d_csd_job *job; 351 352 /* Clean cache job associated to the Indirect CSD job */ 353 struct v3d_job *clean_job; 354 355 /* Offset within the BO where the workgroup counts are stored */ 356 u32 offset; 357 358 /* Workgroups size */ 359 u32 wg_size; 360 361 /* Indices of the uniforms with the workgroup dispatch counts 362 * in the uniform stream. 363 */ 364 u32 wg_uniform_offsets[3]; 365 366 /* Indirect BO */ 367 struct drm_gem_object *indirect; 368 369 /* Context of the Indirect CSD job */ 370 struct ww_acquire_ctx acquire_ctx; 371 }; 372 373 struct v3d_timestamp_query_info { 374 struct v3d_timestamp_query *queries; 375 376 u32 count; 377 }; 378 379 struct v3d_performance_query_info { 380 struct v3d_performance_query *queries; 381 382 /* Number of performance queries */ 383 u32 count; 384 385 /* Number of performance monitors related to that query pool */ 386 u32 nperfmons; 387 388 /* Number of performance counters related to that query pool */ 389 u32 ncounters; 390 }; 391 392 struct v3d_copy_query_results_info { 393 /* Define if should write to buffer using 64 or 32 bits */ 394 bool do_64bit; 395 396 /* Define if it can write to buffer even if the query is not available */ 397 bool do_partial; 398 399 /* Define if it should write availability bit to buffer */ 400 bool availability_bit; 401 402 /* Offset of the copy buffer in the BO */ 403 u32 offset; 404 405 /* Stride of the copy buffer in the BO */ 406 u32 stride; 407 }; 408 409 struct v3d_cpu_job { 410 struct v3d_job base; 411 412 enum v3d_cpu_job_type job_type; 413 414 struct v3d_indirect_csd_info indirect_csd; 415 416 struct v3d_timestamp_query_info timestamp_query; 417 418 struct v3d_copy_query_results_info copy; 419 420 struct v3d_performance_query_info performance_query; 421 }; 422 423 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 424 425 struct v3d_submit_outsync { 426 struct drm_syncobj *syncobj; 427 }; 428 429 struct v3d_submit_ext { 430 u32 flags; 431 u32 wait_stage; 432 433 u32 in_sync_count; 434 u64 in_syncs; 435 436 u32 out_sync_count; 437 struct v3d_submit_outsync *out_syncs; 438 }; 439 440 /** 441 * __wait_for - magic wait macro 442 * 443 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 444 * important that we check the condition again after having timed out, since the 445 * timeout could be due to preemption or similar and we've never had a chance to 446 * check the condition before the timeout. 447 */ 448 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 449 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 450 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 451 int ret__; \ 452 might_sleep(); \ 453 for (;;) { \ 454 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 455 OP; \ 456 /* Guarantee COND check prior to timeout */ \ 457 barrier(); \ 458 if (COND) { \ 459 ret__ = 0; \ 460 break; \ 461 } \ 462 if (expired__) { \ 463 ret__ = -ETIMEDOUT; \ 464 break; \ 465 } \ 466 usleep_range(wait__, wait__ * 2); \ 467 if (wait__ < (Wmax)) \ 468 wait__ <<= 1; \ 469 } \ 470 ret__; \ 471 }) 472 473 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 474 (Wmax)) 475 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 476 477 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 478 { 479 /* nsecs_to_jiffies64() does not guard against overflow */ 480 if ((NSEC_PER_SEC % HZ) != 0 && 481 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 482 return MAX_JIFFY_OFFSET; 483 484 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 485 } 486 487 /* v3d_bo.c */ 488 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 489 void v3d_free_object(struct drm_gem_object *gem_obj); 490 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 491 size_t size); 492 void v3d_get_bo_vaddr(struct v3d_bo *bo); 493 void v3d_put_bo_vaddr(struct v3d_bo *bo); 494 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 495 struct drm_file *file_priv); 496 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 497 struct drm_file *file_priv); 498 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 499 struct drm_file *file_priv); 500 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 501 struct drm_file *file_priv); 502 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 503 struct dma_buf_attachment *attach, 504 struct sg_table *sgt); 505 506 /* v3d_debugfs.c */ 507 void v3d_debugfs_init(struct drm_minor *minor); 508 509 /* v3d_fence.c */ 510 extern const struct dma_fence_ops v3d_fence_ops; 511 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue); 512 513 /* v3d_gem.c */ 514 int v3d_gem_init(struct drm_device *dev); 515 void v3d_gem_destroy(struct drm_device *dev); 516 void v3d_reset(struct v3d_dev *v3d); 517 void v3d_invalidate_caches(struct v3d_dev *v3d); 518 void v3d_clean_caches(struct v3d_dev *v3d); 519 520 /* v3d_submit.c */ 521 void v3d_job_cleanup(struct v3d_job *job); 522 void v3d_job_put(struct v3d_job *job); 523 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 524 struct drm_file *file_priv); 525 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 526 struct drm_file *file_priv); 527 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 528 struct drm_file *file_priv); 529 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 530 struct drm_file *file_priv); 531 532 /* v3d_irq.c */ 533 int v3d_irq_init(struct v3d_dev *v3d); 534 void v3d_irq_enable(struct v3d_dev *v3d); 535 void v3d_irq_disable(struct v3d_dev *v3d); 536 void v3d_irq_reset(struct v3d_dev *v3d); 537 538 /* v3d_mmu.c */ 539 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 540 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 541 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 542 543 /* v3d_sched.c */ 544 int v3d_sched_init(struct v3d_dev *v3d); 545 void v3d_sched_fini(struct v3d_dev *v3d); 546 547 /* v3d_perfmon.c */ 548 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 549 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 550 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 551 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 552 bool capture); 553 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 554 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 555 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 556 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 557 struct drm_file *file_priv); 558 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 559 struct drm_file *file_priv); 560 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 561 struct drm_file *file_priv); 562 563 /* v3d_sysfs.c */ 564 int v3d_sysfs_init(struct device *dev); 565 void v3d_sysfs_destroy(struct device *dev); 566