1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/spinlock_types.h> 7 #include <linux/workqueue.h> 8 9 #include <drm/drm_encoder.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_gem_shmem_helper.h> 12 #include <drm/gpu_scheduler.h> 13 14 #include "uapi/drm/v3d_drm.h" 15 16 struct clk; 17 struct platform_device; 18 struct reset_control; 19 20 #define GMP_GRANULARITY (128 * 1024) 21 22 #define V3D_MAX_QUEUES (V3D_CACHE_CLEAN + 1) 23 24 static inline char *v3d_queue_to_string(enum v3d_queue queue) 25 { 26 switch (queue) { 27 case V3D_BIN: return "bin"; 28 case V3D_RENDER: return "render"; 29 case V3D_TFU: return "tfu"; 30 case V3D_CSD: return "csd"; 31 case V3D_CACHE_CLEAN: return "cache_clean"; 32 } 33 return "UNKNOWN"; 34 } 35 36 struct v3d_queue_state { 37 struct drm_gpu_scheduler sched; 38 39 u64 fence_context; 40 u64 emit_seqno; 41 42 u64 start_ns; 43 u64 enabled_ns; 44 u64 jobs_sent; 45 }; 46 47 /* Performance monitor object. The perform lifetime is controlled by userspace 48 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 49 * request, and when this is the case, HW perf counters will be activated just 50 * before the submit_cl is submitted to the GPU and disabled when the job is 51 * done. This way, only events related to a specific job will be counted. 52 */ 53 struct v3d_perfmon { 54 /* Tracks the number of users of the perfmon, when this counter reaches 55 * zero the perfmon is destroyed. 56 */ 57 refcount_t refcnt; 58 59 /* Protects perfmon stop, as it can be invoked from multiple places. */ 60 struct mutex lock; 61 62 /* Number of counters activated in this perfmon instance 63 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 64 */ 65 u8 ncounters; 66 67 /* Events counted by the HW perf counters. */ 68 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 69 70 /* Storage for counter values. Counters are incremented by the 71 * HW perf counter values every time the perfmon is attached 72 * to a GPU job. This way, perfmon users don't have to 73 * retrieve the results after each job if they want to track 74 * events covering several submissions. Note that counter 75 * values can't be reset, but you can fake a reset by 76 * destroying the perfmon and creating a new one. 77 */ 78 u64 values[] __counted_by(ncounters); 79 }; 80 81 struct v3d_dev { 82 struct drm_device drm; 83 84 /* Short representation (e.g. 33, 41) of the V3D tech version 85 * and revision. 86 */ 87 int ver; 88 bool single_irq_line; 89 90 void __iomem *hub_regs; 91 void __iomem *core_regs[3]; 92 void __iomem *bridge_regs; 93 void __iomem *gca_regs; 94 struct clk *clk; 95 struct reset_control *reset; 96 97 /* Virtual and DMA addresses of the single shared page table. */ 98 volatile u32 *pt; 99 dma_addr_t pt_paddr; 100 101 /* Virtual and DMA addresses of the MMU's scratch page. When 102 * a read or write is invalid in the MMU, it will be 103 * redirected here. 104 */ 105 void *mmu_scratch; 106 dma_addr_t mmu_scratch_paddr; 107 /* virtual address bits from V3D to the MMU. */ 108 int va_width; 109 110 /* Number of V3D cores. */ 111 u32 cores; 112 113 /* Allocator managing the address space. All units are in 114 * number of pages. 115 */ 116 struct drm_mm mm; 117 spinlock_t mm_lock; 118 119 struct work_struct overflow_mem_work; 120 121 struct v3d_bin_job *bin_job; 122 struct v3d_render_job *render_job; 123 struct v3d_tfu_job *tfu_job; 124 struct v3d_csd_job *csd_job; 125 126 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 127 128 /* Spinlock used to synchronize the overflow memory 129 * management against bin job submission. 130 */ 131 spinlock_t job_lock; 132 133 /* Used to track the active perfmon if any. */ 134 struct v3d_perfmon *active_perfmon; 135 136 /* Protects bo_stats */ 137 struct mutex bo_lock; 138 139 /* Lock taken when resetting the GPU, to keep multiple 140 * processes from trying to park the scheduler threads and 141 * reset at once. 142 */ 143 struct mutex reset_lock; 144 145 /* Lock taken when creating and pushing the GPU scheduler 146 * jobs, to keep the sched-fence seqnos in order. 147 */ 148 struct mutex sched_lock; 149 150 /* Lock taken during a cache clean and when initiating an L2 151 * flush, to keep L2 flushes from interfering with the 152 * synchronous L2 cleans. 153 */ 154 struct mutex cache_clean_lock; 155 156 struct { 157 u32 num_allocated; 158 u32 pages_allocated; 159 } bo_stats; 160 }; 161 162 static inline struct v3d_dev * 163 to_v3d_dev(struct drm_device *dev) 164 { 165 return container_of(dev, struct v3d_dev, drm); 166 } 167 168 static inline bool 169 v3d_has_csd(struct v3d_dev *v3d) 170 { 171 return v3d->ver >= 41; 172 } 173 174 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 175 176 /* The per-fd struct, which tracks the MMU mappings. */ 177 struct v3d_file_priv { 178 struct v3d_dev *v3d; 179 180 struct { 181 struct idr idr; 182 struct mutex lock; 183 } perfmon; 184 185 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 186 187 u64 start_ns[V3D_MAX_QUEUES]; 188 189 u64 enabled_ns[V3D_MAX_QUEUES]; 190 191 u64 jobs_sent[V3D_MAX_QUEUES]; 192 }; 193 194 struct v3d_bo { 195 struct drm_gem_shmem_object base; 196 197 struct drm_mm_node node; 198 199 /* List entry for the BO's position in 200 * v3d_render_job->unref_list 201 */ 202 struct list_head unref_head; 203 }; 204 205 static inline struct v3d_bo * 206 to_v3d_bo(struct drm_gem_object *bo) 207 { 208 return (struct v3d_bo *)bo; 209 } 210 211 struct v3d_fence { 212 struct dma_fence base; 213 struct drm_device *dev; 214 /* v3d seqno for signaled() test */ 215 u64 seqno; 216 enum v3d_queue queue; 217 }; 218 219 static inline struct v3d_fence * 220 to_v3d_fence(struct dma_fence *fence) 221 { 222 return (struct v3d_fence *)fence; 223 } 224 225 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 226 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 227 228 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 229 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 230 231 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 232 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 233 234 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 235 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 236 237 struct v3d_job { 238 struct drm_sched_job base; 239 240 struct kref refcount; 241 242 struct v3d_dev *v3d; 243 244 /* This is the array of BOs that were looked up at the start 245 * of submission. 246 */ 247 struct drm_gem_object **bo; 248 u32 bo_count; 249 250 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 251 struct dma_fence *irq_fence; 252 253 /* scheduler fence for when the job is considered complete and 254 * the BO reservations can be released. 255 */ 256 struct dma_fence *done_fence; 257 258 /* Pointer to a performance monitor object if the user requested it, 259 * NULL otherwise. 260 */ 261 struct v3d_perfmon *perfmon; 262 263 /* File descriptor of the process that submitted the job that could be used 264 * for collecting stats by process of GPU usage. 265 */ 266 struct drm_file *file; 267 268 /* Callback for the freeing of the job on refcount going to 0. */ 269 void (*free)(struct kref *ref); 270 }; 271 272 struct v3d_bin_job { 273 struct v3d_job base; 274 275 /* GPU virtual addresses of the start/end of the CL job. */ 276 u32 start, end; 277 278 u32 timedout_ctca, timedout_ctra; 279 280 /* Corresponding render job, for attaching our overflow memory. */ 281 struct v3d_render_job *render; 282 283 /* Submitted tile memory allocation start/size, tile state. */ 284 u32 qma, qms, qts; 285 }; 286 287 struct v3d_render_job { 288 struct v3d_job base; 289 290 /* GPU virtual addresses of the start/end of the CL job. */ 291 u32 start, end; 292 293 u32 timedout_ctca, timedout_ctra; 294 295 /* List of overflow BOs used in the job that need to be 296 * released once the job is complete. 297 */ 298 struct list_head unref_list; 299 }; 300 301 struct v3d_tfu_job { 302 struct v3d_job base; 303 304 struct drm_v3d_submit_tfu args; 305 }; 306 307 struct v3d_csd_job { 308 struct v3d_job base; 309 310 u32 timedout_batches; 311 312 struct drm_v3d_submit_csd args; 313 }; 314 315 struct v3d_submit_outsync { 316 struct drm_syncobj *syncobj; 317 }; 318 319 struct v3d_submit_ext { 320 u32 flags; 321 u32 wait_stage; 322 323 u32 in_sync_count; 324 u64 in_syncs; 325 326 u32 out_sync_count; 327 struct v3d_submit_outsync *out_syncs; 328 }; 329 330 /** 331 * __wait_for - magic wait macro 332 * 333 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 334 * important that we check the condition again after having timed out, since the 335 * timeout could be due to preemption or similar and we've never had a chance to 336 * check the condition before the timeout. 337 */ 338 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 339 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 340 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 341 int ret__; \ 342 might_sleep(); \ 343 for (;;) { \ 344 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 345 OP; \ 346 /* Guarantee COND check prior to timeout */ \ 347 barrier(); \ 348 if (COND) { \ 349 ret__ = 0; \ 350 break; \ 351 } \ 352 if (expired__) { \ 353 ret__ = -ETIMEDOUT; \ 354 break; \ 355 } \ 356 usleep_range(wait__, wait__ * 2); \ 357 if (wait__ < (Wmax)) \ 358 wait__ <<= 1; \ 359 } \ 360 ret__; \ 361 }) 362 363 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 364 (Wmax)) 365 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 366 367 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 368 { 369 /* nsecs_to_jiffies64() does not guard against overflow */ 370 if ((NSEC_PER_SEC % HZ) != 0 && 371 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 372 return MAX_JIFFY_OFFSET; 373 374 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 375 } 376 377 /* v3d_bo.c */ 378 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 379 void v3d_free_object(struct drm_gem_object *gem_obj); 380 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 381 size_t size); 382 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 383 struct drm_file *file_priv); 384 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 385 struct drm_file *file_priv); 386 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 387 struct drm_file *file_priv); 388 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 389 struct dma_buf_attachment *attach, 390 struct sg_table *sgt); 391 392 /* v3d_debugfs.c */ 393 void v3d_debugfs_init(struct drm_minor *minor); 394 395 /* v3d_fence.c */ 396 extern const struct dma_fence_ops v3d_fence_ops; 397 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue); 398 399 /* v3d_gem.c */ 400 int v3d_gem_init(struct drm_device *dev); 401 void v3d_gem_destroy(struct drm_device *dev); 402 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 403 struct drm_file *file_priv); 404 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 405 struct drm_file *file_priv); 406 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 407 struct drm_file *file_priv); 408 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 409 struct drm_file *file_priv); 410 void v3d_job_cleanup(struct v3d_job *job); 411 void v3d_job_put(struct v3d_job *job); 412 void v3d_reset(struct v3d_dev *v3d); 413 void v3d_invalidate_caches(struct v3d_dev *v3d); 414 void v3d_clean_caches(struct v3d_dev *v3d); 415 416 /* v3d_irq.c */ 417 int v3d_irq_init(struct v3d_dev *v3d); 418 void v3d_irq_enable(struct v3d_dev *v3d); 419 void v3d_irq_disable(struct v3d_dev *v3d); 420 void v3d_irq_reset(struct v3d_dev *v3d); 421 422 /* v3d_mmu.c */ 423 int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo, 424 u32 *offset); 425 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 426 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 427 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 428 429 /* v3d_sched.c */ 430 int v3d_sched_init(struct v3d_dev *v3d); 431 void v3d_sched_fini(struct v3d_dev *v3d); 432 433 /* v3d_perfmon.c */ 434 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 435 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 436 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 437 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 438 bool capture); 439 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 440 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 441 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 442 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 443 struct drm_file *file_priv); 444 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 445 struct drm_file *file_priv); 446 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 447 struct drm_file *file_priv); 448 449 /* v3d_sysfs.c */ 450 int v3d_sysfs_init(struct device *dev); 451 void v3d_sysfs_destroy(struct device *dev); 452